基于quartus ii110的modelsim仿真

1、Quartus自從9.0版本以后就沒有自帶仿真工具。需要進行仿真要另外安裝仿真工具。下面就以altera-modelsim6.6d 版本介紹一個簡單的VHDL語言編寫的程序的仿真步驟。Quartus工具為11.0版本。1）.新建一個工程。以與非門為例。打開quartus11.0工具欄的file->new->New Quartus II Project.點擊OK。點Next創(chuàng)建工程文件夾，如andnotgate。輸入工程名稱。點Next先別管它，點Next選擇芯片型號，因為是只是仿真，可以隨便選?；蛘吣J。點Next.選擇仿真工具，這里選擇ModelSim-Altera.點Next.

2、點Finish。新建了一個工程。2）.向新建工程添加VHDL源文件File->new->VHDL File->OK編寫源程序：library ieee;use ieee.std_logic_1164.all;entity andnotgate isport(a,b:in std_logic; c:out std_logic );end entity andnotgate;architecture rt1 of andnotgate isbegin c<=not(a and b);end rt1;保存源程序在新建的工程中File->save as保存。編譯源文件：點

3、擊Start compilation編譯成功。3）.利用modelsim進行波形仿真要進行仿真必須先創(chuàng)建一個testbench的仿真激勵文件。testbench文件的編寫可以利用軟件提供的模板進行修改。生成testbench模板processing->start->start test bench template writer->OK打開新生成的testbench模板。在新建工程里的simulation->modelsim里的后綴為.vht的文件。修改testbench文件，主要工作是加入要輸入的信號以及輸出的時間。生成的模板為LIBRARY ieee; USE ie

4、ee.std_logic_1164.all; ENTITY andnotgate_vhd_tst ISEND andnotgate_vhd_tst;ARCHITECTURE andnotgate_arch OF andnotgate_vhd_tst IS- constants - signals SIGNAL a : STD_LOGIC;SIGNAL b : STD_LOGIC;SIGNAL c : STD_LOGIC;COMPONENT andnotgatePORT (a : IN STD_LOGIC;b : IN STD_LOGIC;c : OUT STD_LOGIC);END COMPO

5、NENT;BEGINi1 : andnotgatePORT MAP (- list connections between master ports and signalsa => a,b => b,c => c);init : PROCESS - variable declarations BEGIN - code that executes only once WAIT; END PROCESS init; always : PROCESS - optional sensitivity list - ( ) - variable declarations BEGIN -

6、code executes for every event on sensitivity list WAIT; END PROCESS always; END andnotgate_arch;修改后LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY andnotgate_vhd_tst ISEND andnotgate_vhd_tst;ARCHITECTURE andnotgate_arch OF andnotgate_vhd_tst IS- constants constant clk_period: time := 40 ns; -定義一個時

7、間常數(shù)。 - signals SIGNAL a : STD_LOGIC;SIGNAL b : STD_LOGIC;SIGNAL c : STD_LOGIC;COMPONENT andnotgatePORT (a : IN STD_LOGIC;b : IN STD_LOGIC;c : OUT STD_LOGIC);END COMPONENT;BEGINi1 : andnotgatePORT MAP (- list connections between master ports and signalsa => a,b => b,c => c);init : PROCESS -

8、variable declarations BEGIN -給變量a、b輸入信號。 - code that executes only once a<='0'-20ns a輸出為0.b<='0'-20ns b輸出為0.c=1,輸出正確wait for clk_period/2;a<='1'-20ns a輸出為1b<='1'-20ns b輸出為1,c=0，輸出正確wait for clk_period/2;a<='1'b<='0'-c輸出為1，輸出正確wait for

9、 clk_period/2; WAIT; END PROCESS init; always : PROCESS - optional sensitivity list - ( ) - variable declarations BEGIN - code executes for every event on sensitivity list WAIT; END PROCESS always; END andnotgate_arch;編譯testbench.成功編譯。接著，Assignments->settings->simulation->compile test bench->Test Benches按照上述輸入test bench name,這里為andnotgate.在第二項輸入testbench文件里的實體名，這里為andnotgate_vhd_tst在第三項輸入testbench文件里的實例名，這里為andnotgate.在File name 一欄，選擇生成的testbench模板。點擊Add。全部OK3）.查看仿真波形Tools