Verlex al Solution：verplex形式解

1、cadence confidential1cadence design systems, inc.cadence formal verification2003 beijing internationalmicroelectronics symposiumc. michael changvice president, formal verificationcadence confidential2cadence formal overview formal verification market leader complete formal verification solution prov

2、en technology - 1000s of design tapeouts comprehensive asic vendor & foundry support 300 customers worldwidefirmwareir dropspowermixed signal intfyieldrace conditionslow pathclockingnoisefunctional0%10%20%30%40%50%60%70%80%100% 74%33%31%31%24%23%21%14%11%10%october 2000collett international half

3、 of all chips today require 1 or more re-spins74% of all re-spins are due to functional errors0%10%20%30%40%50%60%19981999200020012002*verplexavant!synopsysotherssource: dataquest, * edacavant! + synopsysavant! + synopsyscadence confidential3ensures consistency of two designsexhaustive verification

4、using mathematical algorithmsorders of magnitude faster than simulationno test vectors requiredpinpoints errors quicklysimplifies analysis and debug of implementation errorsequivalence checking (ec) introductiongate:post synth,p&r etc.rtlorgateimplementation verificationconformal eccadence confi

5、dential4conformal solutioncomprehensive equivalence checking solutionmemorymemorydatapathdatapathdatapath datapathmemorymemorymemorymemorymemorymemoryrandom logicrandomlogic custom logic, i/o cells custom logic, i/o cells custom logic, i/o cells custom logic, i/o cellsec for random logicverifies syn

6、thesized logicec for embedded memoryverifies custom memoriesec for complex datapathverifies compiled datapathec for digital customverifies custom logic, io cells, librariessemantic & structural checksverifies buses and synthesis pragmasec for layoutverifies physical integrationclock domain cross

7、ing checksverifies clock synchronizationcadence confidential5used throughout the implementation processindependently developed technologyproduction proven on 1000s of designsbest performance“conformal by far blows away formality in speed and capacity.”- bob lawrence, agere systemsconformalequivalenc

8、echeckerconformal ensures implementation equivalenceconformal solutionimplementation verificationcadence confidential6conformal solutionextends ec to complex datapathtrends indicate increased usage of advanced datapath optimizationused to create high performance and area optimized circuitsconformal

9、provides formal verification solution for complex datapathexhaustive verification magnitudes faster than simulationeasier to pin-point errors and debugconformal ecdatapath synthesisgatertlequivalence checkedverifying datapath circuits has been very difficult and time consuming in the past, but we ha

10、ve found conformal dp to be very efficient in comparing different types of datapath circuits. hiroshi furukawa, system-on-a-chip design division of nec micro systemscadence confidential7operator mergingabcyx+abcymergedoperatoradvanced pipeline supportconformal solutioncomplex datapath supporthandles

11、 advanced datapath optimization techniques including operator merging and advanced pipeliningflexible flattened or hierarchicalsupports wide variety of datapath architectures from many datapath synthesis vendors first ec tool to successfully verify complex datapath circuitscadence confidential8confo

12、rmal solutionclosing the rtl to gds verification gapfinal circuitfinal gdsrtl modelgate modellvsecphysical design layout integration circuit optimization netlist conversion gds edits physical design process can introduce logic errors creating a risk of silicon failurelvs doesnt check logic errorscad

13、ence confidential9rtl modelgate modelecfinal circuitfinal gdslvsphysical design layout integration circuit optimization netlist conversion gds edits equivalencecheckercircuitabstractionconformal ecconformal solutionclosing the rtl to gds verification gapconformal ensures rtl to gds equivalencycadenc

14、e confidential10traditional verification method (spice) inadequate for large circuitsconformal provides exhaustive verification capabilities magnitudes faster than simulationsupports io cells, custom datapath, and standard cell librariesconformal solutionextends ec to digital custom circuitsequivale

15、nce checkedrtlcircuitconformal eccadence confidential11targets customer designed embedded memoriesexhaustive verification without vectorsverifies complex control, scan, bist, etc magnitudes faster than simulationsupports ram (single & multi-port), cam (binary & ternary), and register fileseq

16、uivalencecheckerconformal ec solutioncircuitabstractionequivalence checkedrtlspice netlistrtl withmemprimitivememoryprimitivescadencememoryprimitiveconformal solutionextends ec to memoriescadence confidential12conformal solutionproviding a safer ec environment complements ec flow automatic extractio

17、n and verification: clock domain crossing (cdc):clock synchronization & data transfer validation semantics:verification of synthesis pragmas & assumptions structural:implementation checks including bus & tri-statecan validate checks that dont exist in rtl finds difficult implementation b

18、ugscadence confidential13clk aclk baadivergent synchronizersgraycode violationsdata stability violationspotential cdc glitchesmetastability problemsconformal detectsclock topology problems pinpoint problems quickly automatic detection of clock domains and crossings structural verification of multipl

19、e clock domain synchronization functional verification for data stability violations automates error-prone manual post static timing analysis process reduces risk of clock related re-spins prevents late clock related iterations in the design cycleconformal solution clock domain checkingcadence confi

20、dential14rtlalways (a or b or s) begin case (s1:0) /synthesis full_case 2b01: q = a; 2b10: q = b; endcaseendgate-levelsimulations0rtl: s1gate: qaasynthesisbbaabaconformal solution semantic checks conditions that may create mismatches between rtl and gate-level simulationsfull caseparallel casex-assi

21、gnmentrange overflow conformal checks if unexpected conditions can exist in design:s1:0 = 0,0, s1,0 = 1,1 finds functional mismatches that are otherwise missed or detected only by gate level simulation late in design cycle equivalency can not find this type of errorec follows synthesis interpretatio

22、nconformal finds semantic corner-case bugs earliercadence confidential15conformal solution structural checks class of bugs typically found late in design cycle, if at allmay not be present in “rtl” , scan insertion errorsintroduced during design integrationintroduced during implementation and ecos bus checksbus contentionbus or net driven by conflicting databus floatingbus is not driven by any signaltri-state stuck-at problem with tri-state driver enable set