第四章邏輯門電路作業(yè)題(參考答案)

1、第四章 邏輯門電路（Logic Gates Circuits）1知識要點CMOS邏輯電平和噪聲容限；CMOS邏輯反相器、與非門、或非門、非反相門、與或非門電路的結(jié)構(gòu)；CMOS邏輯電路的穩(wěn)態(tài)電氣特性：帶電阻性負載的電路特性、非理想輸入時的電路特性、負載效應、不用的輸入端及等效的輸入/輸出電路模型；動態(tài)電氣特性：轉(zhuǎn)換時間、傳輸延遲、電流尖峰、扇出特性；特殊的輸入/輸出電路結(jié)構(gòu)：CMOS傳輸門、三態(tài)輸出結(jié)構(gòu)、施密特觸發(fā)器輸入結(jié)構(gòu)、漏極開路輸出結(jié)構(gòu)。重點：1CMOS邏輯門電路的結(jié)構(gòu)特點及與邏輯表達式的對應關(guān)系；2CMOS邏輯電平的定義和噪聲容限的計算；3邏輯門電路扇出的定義及計算；4邏輯門電路轉(zhuǎn)換時間

2、、傳輸延遲的定義。難點：1CMOS互補網(wǎng)絡(luò)結(jié)構(gòu)的分析和設(shè)計；2邏輯門電路對負載的驅(qū)動能力的計算。（1）PMOS和NMOS場效應管的開關(guān)特性MOSFET管實際上由4部分組成：Gate，Source，Drain和Backgate，Source和Drain之間由Backgate連接，當Gate對Backgate的電壓超過某個值時，Source和Drain之間的電介質(zhì)就會形成一個通道，使得兩者之間產(chǎn)生電流，從而導通管子，這個電壓值稱為閾值電壓。對PMOS管而言，閾值電壓是負值，而對NMOS管而言，閾值電壓是正值。也就是說，在邏輯電路中，NMOS管和PMOS管均可看做受控開關(guān)，對于高電平1，NMOS導通

3、，PMOS截斷 ；對于低電平0，NMOS截斷，PMOS導通。（2）CMOS門電路的構(gòu)成規(guī)律每個CMOS門電路都由NMOS電路和PMOS電路兩部分組成，并且每個輸入都同時加到一個NMOS管和一個PMOS管的柵極（Gate）上。對正邏輯約定而言，NMOS管的串聯(lián)（Series Connection）可實現(xiàn)與操作（Implement AND Operation），并聯(lián)（Parallel Connection）可實現(xiàn)或操作（Implement OR Operation）。PMOS電路與NMOS電路呈對偶關(guān)系，即當NMOS管串聯(lián)時，其相應的PMOS管一定是并聯(lián)的；而當NMOS管并聯(lián)時，其相應的PMOS管

4、一定需要串聯(lián)?；具壿嬯P(guān)系體現(xiàn)在NMOS管的網(wǎng)絡(luò)上，由于NMOS網(wǎng)絡(luò)接地，輸出需要反相（取非）。（3）CMOS邏輯電路的穩(wěn)態(tài)電氣特性 一般來說，器件參數(shù)表中用以下參數(shù)來說明器件的邏輯電平定義：VOHmin 輸出為高電平時的最小輸出電壓VIHmin 能保證被識別為高電平時的最小輸入電壓VOLmax 能保證被識別為低電平時的最大輸入電壓VILmax 輸出為低電平時的最大輸出電壓不同邏輯種類對應的參數(shù)值不同。輸入電壓主要由晶體管的開關(guān)門限電壓決定，而輸出電壓主要由晶體管的“導通”電阻決定。噪聲容限是指芯片在最壞輸出電壓情況下，多大的噪聲電平會使得輸出電壓被破壞成不可識別的輸入值。對于輸出是高電平的情

5、況，其最壞的輸出電壓是VOHmin，如果要使該電壓能在輸入端被正確識別為高電平，即被噪聲污染后的電壓值應該不小于VIHmin，則噪聲容限為VOHmin-VIHmin。對于輸出是低電平的情況，噪聲容限為VILmax -VOLmax。輸出電流的定義如下。IOLmax：輸出低態(tài)且仍能維持輸出電壓不大于VOLmax時，輸出端能吸收的最大電流；IOHmax：輸出高態(tài)且仍能維持輸出電壓不小于VOHmin時，輸出端可提供的最大電流。（4）扇出邏輯門的扇出（fanout）是指該門電路在不超出其最壞情況負載規(guī)格的條件下能驅(qū)動的輸入端的個數(shù)。扇出不僅依賴于輸出端的特性，還依賴于它驅(qū)動的輸入端的特性。扇出的計算必須

6、考慮輸出的兩種可能狀態(tài)：高電平狀態(tài)和低電平狀態(tài)。直流扇出能力的計算方法為：最大輸出電流/最大輸入電流。一個門電路的高電平扇出和低電平扇出不一定相等。通常，門電路的總扇出應為高電平扇出和低電平扇出中的較小值。（5）CMOS電路的動態(tài)特性轉(zhuǎn)換時間可分為輸出上升時間tr和輸出下降時間tf，其值的大小和門的導通電阻與負載電容之積成正比。傳輸延遲時間tp指的是從輸入變化到輸出變化所需的時間。其值取決于器件內(nèi)部的結(jié)構(gòu)與信號傳輸?shù)穆窂?；同一個器件，不同輸入/輸出間的傳輸延遲可能不同，由多種因素決定。（6）CMOS電路的功耗輸出不變時的CMOS電路功耗稱為靜態(tài)功耗。CMOS電路在狀態(tài)轉(zhuǎn)換時消耗的電能稱為動態(tài)功

7、耗，其來源是輸出端上的電容性負載CL，輸出從低到高轉(zhuǎn)換時，電流流過P溝道晶體管給負載充電，類似地，輸出從高到低轉(zhuǎn)換時，電流流過N溝道晶體管給負載放電，這兩種情況下晶體管導通的電阻都消耗功率。充電開始時電壓變化為VDD，結(jié)束時電壓變化很小，故平均電壓變化為VDD/2，則每次轉(zhuǎn)換消耗的電能為，若每秒鐘變化2f次，則由電容性負載引起的動態(tài)功耗為。2Exercises 4.1 The Stub Series Terminalted low Voltage(SSTV) logic family, used for SDRAM modules, defines a LOW signal to be in

8、the range 0.00.7V, and a HIGH signal to be in the range 1.72.5V. Under a positive-logic convention, indicate the logic value associated with each of the following signal levels:(a) 0.0V(b) 0.7V(c) 1.7V(d) -0.6V (e) 1.6V(f) -2.0V(g) 2.5V(h) 3.3V(a) 0(b) 0(c) 1(d) undefined (e) undefined(f) undefined(

9、g) 1(h) undefined4.2 Repeat exercise 4.1 using a negative-logic convention.(a) 1(b) 1(c) 0(d) undefined(e) undefined(f) undefined(g) 0(h) undefined4.3 True or false: For a given set of input values, a NAND gate produces the opposite output as a NOR gate.When the two inputs are different, it will be

10、ture.4.4 For a given silicon area, which is likely to be faster, a CMOS NAND gate or a CMOS NOR?CMOS NAND will be faster than CMOS NOR.4.5 Which has fewer transistors, a CMOS inverting gate or a noninverting gate?CMOS inverting gate has fewer transistors.4.6 For each of the following resistive loads

11、, determine whether the output drive specifications of the 74HC00 over the commercial operating range are exceeded (use V= 0.33V，VOHmin = 3.84V and VCC = 5.0 V). You may not exceed IOLmax (4mA) or IOHmax (4mA) in any state.(1) 1.2k W to VCC and 820 W to GND(2) 470 W to VCC and 470 W to GND74HC00VccV

12、cc1.2k W820 WVoVin1Vin2R1R2(1) VThev = Vcc×R2 / (R1+R2) = 5×820 / (1200+820) 2.03VI Short = Vcc / R1RThev = VThev / I Short= R1×R2 / (R1+R2)= 1200×820 / (1200+820) 487.13 WVOHmin = 3.84V IOH = (VOHmin-VThev ) / RThev 3.7 mA < IOHmax = 4 mAVOLmax = 0.33V IOL = (VThev - VOLmax)

13、/ RThev 3.5 mA < IOLmax = 4 mA因此，沒有超出商用工作范圍，可以正常驅(qū)動負載。74HC00VccVcc270330VoVin1Vin2R1R274HC00VccVcc470 W470 WVoVin1Vin2R1R2(2) VThev = Vcc×R2 / (R1+R2) = 5 / 2= 2.5VI Short = Vcc / R1RThev = VThev / I Short= R1×R2 / (R1+R2)= 470 / 2= 235 WVOHmin = 3.84V IOH = (VOHmin-VThev ) / RThev 5.7 m

14、A > IOHmax = 4 mAVOLmax = 0.33V IOL = (VThev - VOLmax) / RThev 9.2 mA > IOLmax = 4 mA因此，超出了商用工作范圍，不能驅(qū)動負載。4.7 A particular Schmitt-trigger inverter has = 0.8 V, = 2.0 V, =1.7 V, and = 1.2 V. How much hysteresis does it have? Hysteresis = -= 1.7-1.2 = 0.5V4.8 Discuss the pros and cons of larger

15、versus smaller pull-up resistors for open-drain CMOS outputs.較小的上拉電阻：優(yōu)點是輸出電平在上升時較快，使得其工作運行的速度較快；缺點是在輸出低電平時電源對地的電流較大，使得其功耗較大。較大的上拉電阻：優(yōu)點是在輸出低電平時電源對地的電流較小，使得其功耗較??；缺點是輸出電平在上升時較慢，使得其工作運行的速度較慢。4.9 How many diodes are required for an n-input diode AND gate?n diodes are required.4.10 Compute the maximum fan

16、out for each of the following cases of a TTL output driving multiple TTL inputs. Also indicate how much “excess” driving capability is available in the LOW or HIGH state for each case. ( Refer to datasheets in Appendix )(1) 74LS driving 74AS (2) 74LS driving 74F (1) 根據(jù)數(shù)據(jù)表，74LS的IOLmax = 8 mA，74AS的IIL

17、max = -0.5 mA Low-state Fan-Out = 8 / 0.5 = 1674LS的IOHmax = -400A，74AS的IIHmax = 20A High-state Fan-Out = 400 / 20 = 20因此，總的最大扇出為16。高態(tài)剩余驅(qū)動能力 = (20-16)×20 = 80A(b) 根據(jù)數(shù)據(jù)表，74LS的IOLmax = 8 mA，74F的IILmax = -0.6 mA Low-state Fan-Out = 8 / 0.6 1374LS的IOHmax = -400A，74F的IIHmax = 20A High-state Fan-Out =

18、 400 / 20 = 20因此，總的最大扇出為13。高態(tài)剩余驅(qū)動能力 = (20-13)×20 = 140A4.11 Compute the LOW-state and HIGH-state DC noise margins for each of the following cases of a TTL-compatible CMOS output driving a TTL input, or vice versa. ( Refer to datasheets in Appendix )(1) 74HCT driving 74LS(2) 74ALS driving 74HCT(

19、1) 根據(jù)數(shù)據(jù)表，74HCT的VOHminT = 3.84V，74LS的VIHmin = 2.0V High-state Noise Margin : 3.84 2.0 = 1.84V74HCT的VOLmaxT = 0.33V，74LS的VILmax = 0.8V Low-state Noise Margin : 0.8 0.33 = 0.47V(2) 根據(jù)數(shù)據(jù)表，74ALS的VOHmin = 2.7V，74HCT的VIHmin = 2.0V High-state Noise Margin : 2.7 2.0 = 0.7V74ALS的VOLmax = 0.5V，74HCT的VILmax = 0

20、.8V Low-state Noise Margin : 0.8 0.5 = 0.3V4.12 Compute the maximum fanout for each of the following case of a TTL-compatible CMOS output driving multiple inputs in a TTL logic family. Also indicate how much “excess” driving capability is available in the LOW or HIGH state for each case. ( Refer to

21、datasheets in Appendix )(1) 74HCT driving 74LS(2) 74AHCT driving 74S(1) 根據(jù)數(shù)據(jù)表，74HCT的IOLmaxT = 4 mA，74LS的IILmax = -0.4 mA Low-state Fan-Out = 4 / 0.4 = 1074HCT的IOHmaxT = -4 mA，74LS的IIHmax = 20A High-state Fan-Out = 4000 / 20 = 200因此，總的最大扇出為10。高態(tài)剩余(excess)驅(qū)動能力 = (200-10)×20 = 3.8 mA(2) 根據(jù)數(shù)據(jù)表，74AH

22、CT的IOLmaxT = 8 mA，74S的IILmax = -2.0 mA Low-state Fan-Out = 8 / 2 = 474AHCT的IOHmaxT = -8 mA，74S的IIHmax = 50A High-state Fan-Out = 8000 / 50 = 160因此，總的最大扇出為4。高態(tài)剩余(excess)驅(qū)動能力 = (160-4)×50 = 7.8 mAOptions4.13 Draw a circuit diagram, function table, and logic symbol for a CMOS gate with two inputs A and B and an output Z, where Z = 1 if A = 0 and B = 1, and Z = 0 otherwise (Hint: Only six transistors are required).Fill out the truth table fist:A BZ0 000 111 001 10Get the logic expression: Z = A · B Then draw th