電子元器件應(yīng)用-Interfacing the TLV563

1、Application ReportSLAU071 - MAY 2001INTERFACING THE TLV5639 DAC TO THE TMS320C31 DSPBy Joselito ParguianThis application report discusses the implementation of aninterface between the TLV5639 Digital-to-Analog Con-verter (DAC) and the TMS320C31 Digital-Signal Processor(DSP). The TLV5619-5639EVM will

2、 be used to demon-strate the complete circuit implementation. This EVM is theevaluation module for the TLV5639 and the TLV5619DACs that will take care of all the necessary signal manipu-lation for the control signals of the DAC. The TLV5639 isa 12-bit DAC with a microprocessor-compatible parallelint

3、erface designed for many applications, such as digitalservo control loops, digital offset and gain adjustment,industrial process control, machine- and motion-control de-vices, and mass storage devices to name a few.The software application included in this report will provide theDAC data to create a

4、 sawtooth waveform output of the DAC.The complete system to demonstrate the functionality of theTLV5639 DAC includes the TMS320C31 DSP Starter Kit(DSK), TLV5619-5639EVM, XDS510 emulator and cable,a host PC, power supply, and a custom-built interfacingcable for the DSP and the DAC. Figure 1 shows the

5、 systemblock diagram. The software interface is written in assemblylanguage using the code composer for the C3X DSP.FIGURE 1. System Block Diagram.TLV5639 DAC OVERVIEWDAC DESCRIPTIONThe TLV5639 is a CMOS, 12-bit, resistor-string voltageoutput DAC. It is programmed with a 16-bit data wordcontaining f

6、our control and 12 data bits. This device canoperate in a wide range of supply voltages from 2.7V to5.5V. The resistor-string output voltage is buffered by a 2xgain rail-to-rail output buffer. The buffer features a ClassAB output stage to improve stability and reduce settlingtime. The programmable s

7、ettling time of the DAC allows thedesigner to optimize speed versus power dissipation. Due toits ability to source up to 1mA, the internal reference canalso be used as a system reference. Additionally, with its on-chip programmable-precision voltage reference, the TLV5639simplifies overall system de

8、sign. The settling time and thereference voltage can be chosen by the control bits withinthe 16-bit data word. The device package and pin out isshown in Figure 2.The pin descriptions and functions are as follows:AGND: Ground Pin.CS: Chip Select. Input signal to enable or disable the device.LDAC: Loa

9、d DAC. Input signal used to load DAC output.OUT: DAC Analog Voltage Output.REG: Register Select. Input signal used to access control register.REF: Analog Reference Voltage Input/Output.VDD: Positive Power Supply.WE: Write Enable input used to latch data.D0-D11: Data Input Pins.FUNCTIONAL BLOCK DIAGR

10、AMThe functional block diagram of the TLV5639 DAC isshown in Figure 3.TMS320C31 DSP INTERFACEThe following sections will describe how the TMS320C31DSP will interface with the TLV5639 DAC in parallel mode.DW or PW Package(Top View)D2D3D4D5D6D7D8D9D1012345678920D119D018171615REG14AGND13OUT12REF11VDDHA

11、RDWARE CONFIGURATIONThe hardware configuration (see Figure 4) shows a typicalparallel interface connection between the DSP and the DAC.the decoder. The address decoder is necessary if there aremore than one device that the DSP is connected to. Other-wise, a single address line (A0) can be used to en

12、able theDAC, and another address line (A1) for the register-selectdata to the DAC holding latch or control register. Theof the DSP to control the loading of the value in the holdinglatch of the DAC. To update the DAC with the value in theD1110FIGURE 2. TLV5639 Package and Pin Out Diagram.SLAU071FIGU

13、RE 4. Hardware Configuration for the DSP to the DAC Interface.SOFTWARE INTERFACEThe software included in this report will provide the inter-face to demonstrate the functional operation of the DAC.The basic DSP operation will add a fixed number repeatedlyin a 32-bit register and send it out to the DA

14、C. The DACconverts the data sent by the DSP to its equivalent voltagelevel, depending on the full-scale range specified by itsvoltage reference input multiplied by two. As the 32-bitregister adds the same number repeatedly to itself, theregister eventually rolls back to zero and the process isrepeat

15、ed. This process in turn generates a ramp (sawtoothwaveform) converted by the DAC transforming the digitaldata into its analog form, as shown in Figure 5. A flowchartdiagram of the software is shown in Figure 6.SAWTOOTH WAVEFORMFIGURE 5. TLV5639 DAC Output (Sawtooth Waveform).FIGURE 6. Software Flow

16、 Chart Diagram.SLAU071OPERATIONThe functional operation of the TLV5639 DAC is imple-mented using the TMS320C31 DSP. Once the hardwareconfiguration is realized (see Figure 4 as an example), thendata transfer can be initiated.DSP CONFIGURATIONThe DSP configuration is quite simple to implement, themain

17、 concern is the primary bus control configuration. Theprimary bus is what gives the DSP control over accessing theexternal memories and peripheral devices attached to it. Theprimary bus allows the user to control wait-state generation,allowing access to slower memories and peripherals bymanipulating

18、 memory-mapped control registers associatedwith the interfaces and by using an external input signal. Theprimary bus consists of a 32-bit data bus, a 24-bit addressbus, and a set of control signals.Primary-Bus Control SignalsThe primary-bus control signals are as follows:STRB:Primary Interface Acces

19、s Strobe. LOW when anexternal access is performed.Specifies memory read (active HIGH) or write (activeLOW) mode.Hold external memory interface.Hold Acknowledge for external memory interface. Indicates external primary interface is ready to beaccessed.The 32-bit primary-bus control register is mapped

20、 intomemory at location 808064H and contains the control bitsfor the primary bus. Table I shows the primary-bus controlregister-bit name abbreviations and Table II shows thefunctions of each bit.Configuring the primary bus requires proper selection of thebit fields, as described in Table II. The ext

21、ernal deviceaccessed by the DSP in this application report does notrequire any complicated configuration, since it is fairly fastand has no signals necessary to acknowledge or interrupt theDSP. Therefore, the configuration word selected particularlyfor this application report is 01018H. As noticed,

22、the resetvalue is preserved for most of the bit fields, except thatWTCNT is set to zero (WTCNT = 000), since the externaldevice (DAC) does not need to slow the DSP down whileperforming its operation, nor acknowledges back to the DSPas mentioned earlier. This selected configuration word sim-ply initi

23、alizes the primary bus with a zero wait state, a banksize of 256 words, and the DSP controlling the external buscompletely. Now DSP operation can be initiated.PRIMARY-BUS CONTROL REGISTERBITNAMEVALUE31-16RESERVEX(1)15-13RESERVEX(1)121110BNKCMPR/W9876WTCNTR/W54SWWR/W32HIZR/W1NOHOLDHOLDSTR/WR(2)TABLE

24、I. Primary-Bus Control Register.ABBREVIATIONHOLDSTNOHOLDRESET VALUE00NAMEHold Status BitPort Hold SignalFUNCTION DESCRIPTIONThis bit signals whether the port is held or not. This status bit is valid whether the port is heldby software or hardware.Enable or disable port to be held by external HOLD si

25、gnal. If disabled, the C3X takes overthe external bus and controls it, regardless of serviced or pending requests by externaldevices.If set (HIZ = 1), the port is put in Hold mode. This is equivalent to the external HOLD signal.This 2-bit field defines the mode of wait-state generation in conjunctio

26、n with WTCNT.This 3-bit field specifies the number of cycles to use when in software wait mode for thegeneration of internal wait states. The range is 0 to 7 H1/H3 cycles.This 5-bit field specifies the number of MSBs of the address to be used to define the bank size.HIZSWWWTCNTBNKCMPInternal HoldSof

27、tware Wait ModeSoftware Wait ModeBank CompareTABLE II. Primary-Bus Control Register Bit Definitions.SLAU071PARALLEL INTERFACEbits of the DSP (D4-D15) are used to connect to the DACOnce the DSP is configured and initialized properly indata pins (D0-D11) in hardware. This preserves the truesoftware to

28、 operate in parallel mode, then the data transfer isvalue of the data that the DAC receives. Since the shift ofachieved, as shown in Figure 7. The TLV5639 DAC latchesdata is done by hardware, the software must then compen-sate for the data shift as well. Therefore, to compensate insoftware, the valu

29、e must first be shifted to the left four bitREG when the data is written. If REG = 0, then the DACpositions before writing it out to the DAC.holding latch is selected and the data is a DAC output. IfAnother way to do this is to set the value of the control wordREG = 1, then the control register is s

30、elected and the data isdata in the program code with the derived value shifted toa configuration data for the DAC. As mentioned in thethe left by four (see preceding example). This would elimi-Hardware Configuration section of this application report,nate the logical shift that the DSP would perform

31、 and savean extra cycle. For example, the derived value to set thethe WE signal of the DAC. Address lines A0 and A1 areDAC for 2V internal reference and to operate in fast modeconnected to the address decoder, since the TLV5619-5639is 0011EVM has two DACs onboard, as well as to separatelyapplication

32、 report). Therefore, the actual control word dataH (refer to the Control Data Bits section of thiscontrol the TLV5639 DAC holding latch and its control(shifted to the left by four) that must be written to the DACregister. 80A002H enables the device and selects the DACis 0110H. If the derived value i

33、s not shifted, and instead theholding latch, while 80A003original value (0011H also enables the device andwill be configured to use external reference and operate inH) is written to the DAC, then the DACLOW by XF0 the entire time the program is executing, tofast mode. This is because the DAC has rec

34、eived the valuecontinuously provide the holding latch with the most currentX001H (X = dont care) which interprets to the configurationvalue for the DAC output.of the one mentioned earlier.The control data format in Table III lists the meaning of theDATA FORMATbits within the control register.The DSP

35、 transfers the data in 16-bit format (D0-D15). Sincethe DAC uses 12-bits of data, only the 12 most significantFIGURE 7. Timing Diagram.DAC CONTROL REGISTERBITD11D10D9D8D7D6D5D4D3D2D1D0NAMEREF1REF0PWRSPDVALUESX(1)X(1)X(1)X(1)X(1)X(1)X(1)0(1)0(1)X(1)0(1)0(1)X = Dont CareNOTE: (1) = Default Values.TABL

36、E III. DAC Control Register Data Format.SLAU0715CONTROL DATA BITSThe control data written to the control register is derived byproperly selecting the desired mode of operation for theDAC using Tables IV and V.BITSPD(D0)PWR(D1)VALUE0101MODESlowFastNormalPower DownTABLE IV. Speed and Power Mode Config

37、uration.REF10011REF00101REFERENCEExternal1,024V Internal2,048V InternalExternalthe system is. It goes into detail as describing the blockdiagram of the DAC and its functional operation. The DACcontrol data and register, as well as the data format, werecovered to avoid any confusion, particularly str

38、essing theshifting of the data by hardware. Refer to the TLV5639datasheet for more detailed specifications and information.Once the hardware is built, the only challenge is to write theinterfacing software to complete the system. If everythinggoes well, then the output (see Figure 5) will be seen co

39、mingout of the DAC output, once probed and displayed in theoscilloscope. This is assuming that the user is attempting todisplay a ramp output, as given in the example code ofAppendix A.REFERENCES1.TLV5639C, TLV5639I Data Sheet (SLAS189)2.TMS320C3X Users Guide Manual (SPRU031)3.TMS320C3X DSP Starter

40、Kit Users Guide Manual(SPRU163)4.TLV5619, TLV5639 DAC EVM Manual (SLAU071)5.Code Composer Studio Users Guide (SPRU328)6.TMS320C3X, C4X Assembly Language Tools UsersGuide (SPRU035)NOTE: If an external reference voltage is applied to the REF pin, thenexternal reference must be selected.TABLE V. Refere

41、nce Bit Configuration to Select ReferenceSource and Voltage.SUMMARYA simple solution is presented in this application report tointerface the TLV5639 DAC to the TMS320C31 DSP. Itpresented the hardware configuration and showed how simpleSLAU071 Author: Joselito Parguian Company: Texas Instruments TLV5

42、639 decode Offset A1A0 /CE REG 0 0 0 1 0Disabled 1 0 1 0 1Write DAC19 / Not Used / 2 1 0 1 0Write DAC39 3 1 1 0 0Write DAC39 REG/LEGAL DISCLAIMER/ The source code programs included herein contain Texas Instruments copyrighted/ material and is protected by copyright laws and international copyright t

43、reaties, as/ well as other intellectual property laws. Texas Instruments hereby grant a copyright/ clearance to use these programs solely with or in conjunction with Texas Instruments/ products. Texas Instruments reserves all rights not expressly granted herein./ TEXAS INSTRUMENTS MAKES NO WARRANTIE

44、S OR REPRESENTATIONS/ THAT THE SOURCE CODE PROGRAMS INCLUDED HEREIN ARE MERCHANTABLE / OF FIT FOR ANY PARTICULAR PURPOSE./.title“TLV5639.ASM”.globalSTART.dataDAC.set2;REG.set3;REGVAL.set0; TLV5639 register valueDAC_BASE.word80A000h; use this external addresses 80A000h or; 0C00000h as base address fo

45、r DACp_buscon.set808064h; Primary bus control;.textSTARTldpp_buscon;ldi01018h,R0;stiR0,p_buscon; 0-wsldi022h,IOF; XF0=/LDAC=0; XF1=0 for /G of U7BldiDAC_BASE,AR0;SLAU0717APPENDIX A. (Cont.)ldiREGVAL,R0; Configure the DAC register (SPD = 1, Ext REF)lsh4,R0; Shift data to compensate for HW data shift

46、stiR0,+AR0(REG); (other than REGVAL=0);ldi0,R0;LOOPaddi100,R0; Generate rampstiR0,+AR0(DAC);bLOOP;.endSLAU071 Author: Joselito Parguian Company: Texas Instruments This is where all interrupt vectors are defined. The user can add here any specific interrupt vectors that will be used in the program/LEGAL DISCLAIMER/ The source code programs included herein contain Texas Instruments copyrighted/ material and is pr