EDAx點(diǎn)陣滾動(dòng)動(dòng)畫顯示

1、四、課程設(shè)計(jì)的總體步驟1、單個(gè)字符的顯示（如：黃）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xianshi isport( clk2:in std_logic;rck,sck:out std_logic;si:out std_logic);end ;architecture one of xianshi issignal sel:std_logic_vector(3 downto 0);signal q: std_logic_vector(31 downto 0);signa

2、l i:integer range 0 to 31;signal coi:std_logic;begin process(sel,clk1)begincase sel is when others =>null; end case; if clk1'event and clk1='1'then si<=q(i);i<=i+1;coi<='0' if i=31 then i<=0;coi<='1'sel<=sel+'1' end if; rck<=not coi; end if

3、;end process;sck<=clk1;end ;時(shí)序仿真：從圖中可以看出，當(dāng)clk1在第32個(gè)上升沿rck變?yōu)榈碗婎l，sck與clk1是同一電頻，故此程序滿足要求。 2、多個(gè)字符的跳動(dòng)顯示（如：黃小紅）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xianshi isport( clk1:in std_logic;clk2:in std_logic;rck,sck:out std_logic;si:out std_logic);end ;architecture o

4、ne of xianshi issignal lie:std_logic_vector(3 downto 0);signal sel:std_logic_vector(3 downto 0);signal q: std_logic_vector(31 downto 0);signal i:integer range 0 to 31;signal coi:std_logic;begin process(sel,clk1,clk2)beginif clk2'event and clk2='1' then lie<=lie+'1' end if; cas

5、e lie is when "0000"=> case sel is when others =>null; end case; when"0001"=> case sel is when others =>null; end case; when"0010"=> case sel is when others =>null; end case; when others=>null; end case; if clk1'event and clk1='1'then si

6、<=q(i);i<=i+1;coi<='0' if i=31 then i<=0;coi<='1'sel<=sel+'1' end if; rck<=not coi; end if;end process;sck<=clk1;end ; 時(shí)序仿真：從上圖看出，當(dāng)clk1在第32個(gè)上升沿rck變?yōu)榈碗婎l，sck與clk1是同一電頻，故此程序滿足要求。3、漢字的滾動(dòng)和動(dòng)畫顯示（如：黃小紅+笑臉）：library ieee;use ieee.std_logic_1164.all;use ieee.std_

7、logic_unsigned.all;entity xianshi isport( clk1:in std_logic;clk2:in std_logic;rck,sck:out std_logic;si:out std_logic);end ;architecture one of xianshi issignal lie:std_logic_vector(3 downto 0);signal sel:std_logic_vector(3 downto 0);signal q: std_logic_vector(31 downto 0);signal i:integer range 0 to

8、 31;signal coi:std_logic;begin process(sel,clk1,clk2)beginif clk2'event and clk2='1' then lie<=lie+'1' end if; case lie is when "0000"=> case sel is when others =>null; end case; when"0001"=> case sel is when others =>null; end case; when"0

9、010"=> case sel is when others =>null; end case; when"0011"=> case sel is when others =>null; end case; when"0100"=> case sel is when others =>null; end case; when"0101"=> case sel is when others =>null; end case; when"0110"=> c

10、ase sel is when others =>null; end case; when"0111"=> case sel is when others =>null; end case; when"1000"=> case sel is when others =>null; end case; when"1001"=> case sel is when others =>null; end case; when"1010"=> case sel is when

11、others =>null; end case; when"1011"=> case sel is when others =>null; end case; when"1100"=> case sel is when others =>null; end case; when"1101"=> case sel is when others =>null; end case; when"1110"=> case sel is when others =>null

12、; end case; when"1111"=> case sel is when others =>null; end case;when others =>null; end case; if clk1'event and clk1='1'then si<=q(i);i<=i+1;coi<='0' if i=31 then i<=0;coi<='1'sel<=sel+'1' end if; rck<=not coi; end if;end

13、process;sck<=clk1;end ；時(shí)序仿真：從上圖看出，當(dāng)clk1在第32個(gè)上升沿rck變?yōu)榈碗婎l，sck與clk1是同一電頻，si為輸出電頻，故此程序滿足要求。五、結(jié)論與收獲在三周的EDA課程設(shè)計(jì)過程中，我對(duì)VHDL語言有了更加深刻的認(rèn)識(shí)。VHDL是超高速集成電路的硬件描述語言，它能夠描述硬件的結(jié)構(gòu)、行為與功能。另外，VHDL具有并發(fā)性，采用自上而下的結(jié)構(gòu)式設(shè)計(jì)方法，適合大型設(shè)計(jì)工程的分工合作。在編寫程序的時(shí)候，我才發(fā)現(xiàn)能看懂程序和能自己寫程序是兩個(gè)完全不同的概念，自己一開始寫程序時(shí)，即便是一個(gè)很簡單的功能模塊，在編譯時(shí)也可能產(chǎn)生很多錯(cuò)誤，在不斷的改錯(cuò)過程中，自己對(duì)VHDL語言的語法結(jié)構(gòu)有了深刻的理解，對(duì)編譯過程中常見的錯(cuò)誤也有了全面的認(rèn)識(shí)。通過這十三周的課程設(shè)計(jì)，我在熟悉了基于FPGA設(shè)計(jì)的同時(shí)，也學(xué)到了很多在學(xué)習(xí)課本知識(shí)時(shí)所體會(huì)不到的東西。完成此次設(shè)計(jì)后，我不僅能對(duì)Quartus II開發(fā)仿真軟件熟練操作，能達(dá)到學(xué)以致用，同時(shí)還掌握了矩陣鍵盤和16×16點(diǎn)陣的工作原理。經(jīng)過這一過程，我發(fā)現(xiàn)平常的學(xué)習(xí)在注重理論知識(shí)的掌握同時(shí)，要加強(qiáng)實(shí)驗(yàn)環(huán)節(jié)，只有通過不斷