產(chǎn)品delta tau pmac運(yùn)動(dòng)控制器6

1、Power PMAC ASIC Setup ElementsJune 2011Delta Tau Machine Interface ASICsCustom digital ICs containing key machine-interface logicDesigned by Delta Tau for each generation of controllerBuilt by “silicon foundries” to Delta Tau specificationsBuilt using “gate array” technology ICs are called “Gates”Mo

2、st UMAC accessory boards are built around one of these ICsAlmost all machine I/O information servo and non-servo passes through these ICsICs appear to CPU as sets of memory-mapped registersPower PMAC provides data structure to access registers (and parts of registers) for each ICScript language can

3、access partial-word and whole-word elementsC language can access whole-word elements only (and thru API functions) must mask and shift for partial-word componentsSaved setup elements permit automatic software configuration of hardware interfacesPMAC2-Style ASICs“DSPGATE1” PMAC2-style Servo ICUsed on

4、 ACC-24E2, ACC-24E2A, ACC-24E2S, ACC-51E boards4 channels servo interface circuitry supports digital and analog interfacesSystem clock generation circuitryPower PMAC accesses with Gate1i data structure“DSPGATE2” PMAC2-style MACRO ICUsed on ACC-5E board16 nodes of MACRO-ring I/O registers (4 in, 4 ou

5、t per node)2 channels servo interface circuitry supports digital and analog interfaces48 digital I/O points (most share pins with servo circuitry)System clock generation circuitryPower PMAC accesses with Gate2i data structure“IOGATE” PMAC2-style Digital I/O ICUsed on ACC-14E, ACC-65E, ACC-66E, ACC-6

6、7E, ACC-68E boards48 digital I/O points, programmable direction and polarityPower PMAC accesses with GateIoi data structurePMAC2-Style “DSPGATE1” Block DiagramAppears to processor as 64 memory-mapped 24-bit registers4 global control registers15 registers per channelPlaced into high 24 bits of Power

7、PMACs 32-bit data busPMAC3-Style ASIC“DSPGATE3” PMAC3-style Machine-Interface ICUsed on UMAC ACC-24E3 axis-interface board assembliesUsed on UMAC ACC-5E3 MACRO-interface boardUsed in Power PMAC Brick ( ing)Used in Power PMAC Ethernet Ultralite ( ing)Combines functionality of all PMAC2-style ASICs in

8、to oneImproves all aspects of functionality (speed, resolution, flexibility, etc.)4 channels servo interface circuitry supports digital and analog interfaces4 banks 32 digital I/O points (3 banks share pins with servo channels)32 nodes of MACRO-ring I/O registers (4 in, 4 out per node)System clock g

9、eneration circuitryPower PMAC accesses with Gate3i data structurePMAC3-Style “DSPGATE3” Block DiagramAppears to processor as 512 memory-mapped 32-bit registers32 registers per servo channel8 multi-channel control registers16 GPIO registers256 MACRO data registersASIC Structure Name AliasesASIC data

10、structure represents full software access to hardware containing the ASICSome users want to use hardware name in programs, not ASIC nameCan use “alias” name of hardware for data structure in Script Feature not available in C (but can do #define text substitution)Alias names for Gate1iAcc24E2i, Acc24

11、E2Ai, Acc24E2Si, Acc51EiAlias name for Gate2iAcc5EiAlias names for Gate3iAcc24E3i, Acc5E3i, Acc59E3iAlias names for GateIoiAcc14Ei, Acc65Ei, Acc66Ei, Acc67Ei, Acc68EiIn alias name, index value i is the same as for IC nameRepresents address within this class of hardwarePMAC2 Servo IC Global Setup Ele

12、mentsDSPGATE1 Servo ASIC multi-channel control variables“i” is Power PMAC IC number 0 19* (different numbering from Turbo)Gate1i.PwmPeriod/ Sets PWM and MaxPhase frequencyGate1i.PhaseClockDiv / f(Phase)=f(MaxPhase)/(PCD+1)Gate1i.ServoClockDiv/ f(Servo)=f(Phase)/(SCD+1)Gate1i.HardwareClockCtrl/ Sets

13、HW clock frequenciesGate1i.PwmDeadTime/ Also PFM pulse widthGate1i.DacStrobe/ Serial strobe word sets # of bitsGate1i.AdcStrobe/ Serial strobe word sets timingGate1i.PhaseServoDir / Input or output for this ASICGate1i.ClockCtrl/ Whole word (for C access)Gate1i.PwmCtrl/ Whole word (for C access) * Po

14、wer PMAC index i = 2 * m ( where m is Turbo PMAC IC number)PMAC2 Servo IC Channel Setup Elements“i” is Power PMAC IC index 0 19 Power PMAC IC index i = 2 * Turbo PMAC IC number m “j” is Power PMAC channel index 0 3 (for HW channel 1 4)Power PMAC channel index j = hardware channel n - 1Gate1i.Chanj.E

15、ncCtrl/ Encoder decode control= 0: Pulse-and direction CW= 4: Pulse-and-direction CCW= 3: x4 quadrature CW= 7: x4 quadrature CCW= 8: Internal pulse-and-direction= 12: MLDT pulse timingGate1i.Chanj.Equ1Ena/ Compare on own or 1st channelGate1i.Chanj.CaptCtrl/ Specify trigger edgesBit 0 = 1: Use index

16、in triggerBit 1 = 1: Use flag in triggerBit 2 = 1: Invert indexBit 3 = 1: Invert flagGate1i.Chanj.CaptFlagSel/ Specify trigger flag used= 0: Use HOMEn flag= 1: Use MLIMn flag= 2: Use PLIMn flag= 3: Use USERn flagPMAC2 Servo IC Channel Setup ElementsGate1i.Chanj.GatedIndexSel/ Trigger on “gated” inde

17、x= 0: Use ungated index= 1: Use index gated to 1 quad state wideGate1i.Chanj.IndexGateState / High/high or low/low= 0: Use high/high quad state= 1: Use low/low quad stateGate1i.Chanj.Output Mode/ PWM, DAC, PFMBit 0 = 0: A/B phases PWMBit 0 = 1: A/B phases DACBit 1 = 0: C phase PWMBit 1 = 1: C phase

18、PFMGate1i.Chanj.OutputPol/ High-true or low-trueBit 0 = 0: A/B phases high-trueBit 0 = 1: A/B phases low-trueBit 1 = 0: C phase high-trueBit 1 = 1: C phase low-trueGate1i.Chanj.PfmDirPol/ High-true or low-true= 0: Positive direction is low= 1: Positive direction is highGate1i.Chanj.OneOverTEna/ Hard

19、ware 1/T calculations= 0: HW 1/T disabled= 1: HW 1/T enabled (not supported)Gate1i.Chanj.Ctrl/ Whole word for C accessASIC Position Compare FunctionalityAvailable in both PMAC2 and PMAC3 ASICsEach channel has own compare circuitryToggles “EQU” output state in hardware when encoder count reaches pres

20、et valueComparison made every encoder sample clock (SCLK) cycle (in MHz)No need for software intervention after initial setupFor precise triggering of outputs (e.g. lasers) and measurementsCan compare to own channels count, or first channels count, as set by Gateni.Chanj.Equ1EnaCan set both sides of

21、 output pulse (“A” and “B”)Can set “auto-increment” distance for repeated pulse intervalSupports pulse output frequencies of several MHzNo high-frequency software routine required for uniform pulse trainPMAC2 Servo IC Position Compare ElementsTwo non-saved 24-bit compare-position elementsGate1i.Chan

22、j pAGate1i.Chanj pBUnits of whole counts, referenced to power-on/reset positionBoth toggle channel compare output when encoder counter value passesNon-saved 24-bit auto-increment element, units of whole countsGate1i.Chanj pAddValue added to/subtracted from CompB when CompA reachedValue added to/subt

23、racted from CompA when CompB reachedInitial values of CompA and CompB must “bracket” starting positionMinimum (non-zero) effective increment of 4 counts2-bit non-saved initial compare output forcing elementGate1i.Chanj.EquWriteBit 1 (value 2) is state to be forcedBit 0 (value 1) = 1 causes this stat

24、e to be forced (auto-cleared to 0)Position Compare Output PatternsPMAC3 ASIC Write-Protect MechanismMost saved setup elements in DSPGATE3 are “write protected”Cannot change the values of these elements unless IC register for Gate3i.WpKey contains the proper value ($AAAAAAAA)Procedure for writing to

25、write-protected element:Write value of $AAAAAAAA to Gate3i.WpKeyWrite new desired value to write-protected elementASIC automatically clears value of Gate3i.WpKeyPower PMAC Script environment automatically copies value of software element Sys.WpKey to Gate3i.WpKey before writing to protected elementU

26、ser simply writes key value once to Sys.WpKey to permit changesValue of Sys.WpKey is not saved, so must be written in after each power-up/reset to permit changesIDE element setup controls automatically set key value for youIn C environment, must use an explicit write to Gate3i.WpKey before each writ

27、e to protected elementPMAC3 ASIC Global Full-Word Setup ElementsThese access full 32-bit register; C programs must use these“i” is Power PMAC IC number 0 15Gate3i.PhaseServoClockCtrl/ Sets system clock frequencies*Gate3i.HardwareClockCtrl/ Sets hardware control clock freqs*Gate3i.DacStrobe/ DAC stro

28、be word sets # of bitsGate3i.AdcAmpCtrl/ Setup info for current ADCs*Gate3i.AdcEncCtrl/ Setup info for position ADCs*Gate3i.ResolverCtrl/ Sets resolver excitation parametersGate3i.SerialEncCtrl/ Sets serial encoder protocolGate3i.MacroModeA/ Ring configuration/statusGate3i.MacroEnableA/ Ring node ac

29、tivationGate3i.MacroModeB/ Ring configuration/statusGate3i.MacroEnableB/ Ring node activation * These have partial-word elements directly accessible by script languagePMAC3 IC System Clock GenerationPMAC3 ASIC Global Partial-Word ElementsC-programs cannot access these must use full-word elementsPart

30、s of Gate3i.PhaseServoClockCtrl full-word elementGate3i.PhaseFreq/ Internal phase clock frequency (Hz)Gate3i.PhaseClockMult/ Output phase clock multiplication factorGate3i.PhaseClockDiv/ Input phase clock division factorGate3i.PhaseServoDir/ Input or output of phase & servo clocksGate3i.EncLatchDela

31、y/ Delay before latching sine encoder dataParts of Gate3i.HardwareClockCtrl full-word elementGate3i.AdcAmpClockDiv/ f(AdcAmpClk) = 100 MHz / 2n n = 015Gate3i.AdcEncClockDiv/ f(AdcEncClk) = 100 MHz / 2n n = 015Gate3i.DacClockDiv/ f(DacClk) = 100 MHz / 2n n = 015Gate3i.EncClockDiv/ f(EncClk) = 100 MHz

32、 / 2n n = 015Gate3i.FiltClockDiv/ f(FiltClk) = f(EncClk) / 2n n = 015Gate3i.ClockPol/ DAC and ADC clock high/low polarityGate3i.ServoClockDiv/ f(Servo) = f(Phase) / (n+1) n = 015PMAC3 ASIC Global Partial-Word ElementsC-programs cannot access these must use full-word elementsParts of Gate3i.AdcAmpCtr

33、l full-word element these set up “amplifer” ADC interface (usually for current feedback)Gate3i.AdcAmpStrobe/ Strobe word shifted out to amplifier ADCsGate3i.AdcAmpDelay/ Delay in start of strobe to amplifier ADCsGate3i.AdcAmpUtoS/ Enable unsigned-to-signed conversionGate3i.AdcAmpHeaderBits/ # of “he

34、ader bits” to expect before dataParts of Gate3i.AdcEncCtrl full-word element the set up “encoder” ADC interface (usually for sine-encoder or resolver feedback)Gate3i.AdcEncStrobe/ Strobe word shifted out to encoder ADCsGate3i.AdcEncDelay/ Delay in start of strobe to encoder ADCsGate3i.AdcEncUtoS/ En

35、able unsigned-to-signed conversionGate3i.AdcEncHeaderBits/ # of “header bits” to expect before dataPMAC3 ASIC Channel Full-Word Setup Elements“i” is Power PMAC IC number 0 15“j” is Power PMAC channel number 0 3 (for HW channel 1 4)Gate3i.Chanj.InCtrl/ Control word for input functions/ Encoder decode

36、, capture control/ timer mode, ADC data formatGate3i.Chanj.OutCtrl/ Control word for output functions/ Output type, PWM frequency,/ compare control, output flagsGate3i.Chanj.AdcOffset0/ Correction bias for AdcEnc0Added to primary Phase A input before arctangent & sum-of-squares calcsGate3i.Chanj.Adc

37、Offset1/ Correction bias for AdcEnc1Added to primary Phase B input before arctangent & sum-of-squares calcsGate3i.Chanj.PfmWidth/ Pulse width for PFM outputThese are full-word (32-bit) elements; InCtrl and OutCtrl have partial-word elements accessible in the Script environmentPMAC3 ASIC Channel Incr

38、emental Encoder CircuitryPMAC3 ASIC Channel Input Control ElementsGate3i.Chanj.EncCtrl/ Encoder decode mode= 0: Pulse-and direction CW= 4: Pulse-and-direction CCW= 3: x4 quadrature CW= 7: x4 quadrature CCW= 8: Internal pulse-and-dir CW= 12: Internal pulse-and-dir CCWGate3i.Chanj.TimerMode/ Timer mod

39、e = 0: Hardware 1/T extension= 1: MLDT pulse-echo timing= 2: Trigger input timing= 3: PFM pulse countingGate3i.Chanj.CaptCtrl/ Capture trigger edge specificationBit 0 = 1: Use index in triggerBit 1 = 1: Use flag in triggerBit 2 = 1: Invert indexBit 3 = 1: Invert flagGate3i.Chanj.CaptFlagSel/ Capture

40、 flag type used= 0: Use HOME flag= 1: Use MLIM flag= 2: Use PLIM flag= 3: Use USER flagGate3i.Chanj.CaptFlagChan/ Channel for capture flag used= 0: Flag from ICs 1st channel= 1: Flag from ICs 2nd channel= 2: Flag from ICs 2nd channel= 3: Flag from ICs 3rd channelPMAC3 ASIC Channel Input Control Elem

41、entsGate3i.Chanj.GatedIndexSel/ Capture w/ “ungated” or “gated” index= 0: Use ungated index= 1: Use index gated to 1 quad state wideGate3i.Chanj.IndexGateState/ Select “gating” quadrature state= 0: Use high/high quad state= 1: Use low/low quad stateGate3i.Chanj.IndexDemuxEna/ Get UVW Halls from muxe

42、d index= 0: Get Halls direct from UVW inputs= 1: Demux Halls from index by quad stateGate3i.Chanj.FlagFilt2Ena/ Use 2nd filter before reading flag inputs= 0: Filtered at SCLK frequency only= 1: Filtered at lower FILCLK frequencyGate3i.Chanj.AtanEna/ Use arctan of ADCs for fractional count= 0: Dont c

43、ombine arctangent value into encoder-count registers= 1: Use arctangent value as low 14 bits of PhaseCapt, ServoCapt registersGate3i.Chanj.SerialEncEna/ Enable serial encoder circuitry= 0: Set SENC_MODEn low (disable)= 1: Set SENC_MODEn high (enable)Gate3i.Chanj.PackInData/ Combine ADC pairs into on

44、e register= 0: A & B ADCs in own register= 1: A & B ADCs share 32-bit register(Sharing register significantly speeds digital current-loop execution)DSPGATE3 Servo Output ChannelPMAC3 ASIC Channel Output Control ElementsGate3i.Chanj.OutputMode/ Select PWM, DAC, PFM for phasesBit k = 0: Phase k is PWM

45、 outBit k = 1: Phase k is DAC (A,B,C) or PFM (D)Gate3i.Chanj.OutputPol/ High-true or low-true outputsGate3i.Chanj.PfmDirPol/ High/low direction sense for PFM out= 0: Positive direction is low= 1: positive direction is highGate3i.Chanj.PfmOutFormat / Pulse-and-direction or quadrature= 0: Pulse-and-di

46、r out for PFM= 1: Quadrature out for PFM (1 edge per pulse)Gate3i.Chanj.PwmFreqMult/ f(PWM) = f(Phase) * (n+1) / 2Gate3i.Chanj.PackOutData/ Separate or combine phase output cmds= 0: Phase cmds in 4 separate regs= 1: A & C, B & D phase cmds combinedGate3i.Chanj.PwmDeadTime / Delay in top/bottom turn-on timeTo prevent shoot-thru current as other transistor is turning offUnits of 53.33 nano