數(shù)字電路設(shè)計(jì)課件第9講互連

數(shù)字集成電路第九講互連問(wèn)題數(shù)字集成電路第九講互連問(wèn)題互連參數(shù)的影響?降低可靠性?影響性能

增加延時(shí)

增加功耗參數(shù)的分類?電容?電阻?電感互連參數(shù)的影響?降低可靠性?影響性能參數(shù)的分類?電容?9.2INTERCONNECTDealingwithCapacitance9.2INTERCONNECTDealingwith9.2.1電容串?dāng)_效應(yīng)9.2.1電容串?dāng)_效應(yīng)電容串?dāng)_效應(yīng)

動(dòng)態(tài)節(jié)點(diǎn)3x1mmoverlap:0.19VdisturbanceCYCXYVDDPDNCLKCLKIn1In2In3YX2.5V0V電容串?dāng)_效應(yīng)

動(dòng)態(tài)節(jié)點(diǎn)3x1mmoverlap:0電容串?dāng)_效應(yīng)

被驅(qū)動(dòng)節(jié)點(diǎn)tXY=RY(CXY+CY)Keeptime-constantsmallerthanrisetimeV(Volt)00.50.450.40.35010.80.6t(nsec)0.40.2XYVXRYCXYCYtr↑電容串?dāng)_效應(yīng)

被驅(qū)動(dòng)節(jié)點(diǎn)tXY=RY(CXY+CY)Ke克服電容串?dāng)_的方法避免浮空節(jié)點(diǎn)對(duì)串?dāng)_敏感的節(jié)點(diǎn)，如預(yù)充電總線等，應(yīng)當(dāng)增加保持器件以降低阻抗敏感節(jié)點(diǎn)應(yīng)當(dāng)很好地與全擺幅信號(hào)隔離在滿足時(shí)序約束的范圍內(nèi)盡可能加大上升（下降）時(shí)間這會(huì)對(duì)短路功耗有影響在敏感的低擺幅布線網(wǎng)絡(luò)中采用差分信號(hào)傳輸方法，使串?dāng)_信號(hào)變?yōu)椴粫?huì)影響電路工作的共模干擾信號(hào)同一層上的兩條導(dǎo)線平行走線的距離不要太長(zhǎng)，減小線間電容兩個(gè)信號(hào)之間增加屏蔽線，能有效地使線間電容變?yōu)橐粋€(gè)接地電容，從而消除干擾不同層上信號(hào)之間的線間電容可以通過(guò)增加額外的布線層來(lái)進(jìn)一步減小克服電容串?dāng)_的方法避免浮空節(jié)點(diǎn)屏蔽GNDGND屏蔽線襯底

(GND)屏蔽層VDD屏蔽GNDGND屏蔽線襯底(GND)屏蔽層VDD9.2.2串?dāng)_與性能Cc-

當(dāng)相鄰的信號(hào)線向相反的方向翻轉(zhuǎn)時(shí)，延時(shí)增加延時(shí)依賴于相鄰信號(hào)線的活動(dòng)Miller效應(yīng)

-Bothterminalsofcapacitorareswitchedinoppositedirections

(0Vdd,Vdd

0)-Effectivevoltageisdoubledandadditionalchargeisneeded

(fromQ=CV)9.2.2串?dāng)_與性能Cc-當(dāng)相鄰的信號(hào)線向相反的方向翻轉(zhuǎn)時(shí)串?dāng)_對(duì)延時(shí)的影響risratiobetweencapacitancetoGNDandtoneighbor在最壞情況下，g＝5，表明僅僅由于線上翻轉(zhuǎn)方向的影響，導(dǎo)線延時(shí)和最好情形之間就可以有500％的差別！tp,k=gCw(0.38Rw+0.69RD)Cw=cwL;Rw=rwLCc串?dāng)_對(duì)延時(shí)的影響risratiobetweenca解決方法（I）估計(jì)和改進(jìn)：經(jīng)過(guò)細(xì)致的參數(shù)提取和模擬可以確定延時(shí)的瓶頸，然后對(duì)電路進(jìn)行適當(dāng)?shù)男薷淖畛Ｊ褂玫姆椒āＨ秉c(diǎn)：在整個(gè)設(shè)計(jì)生產(chǎn)過(guò)程中需要多次的反復(fù)，費(fèi)時(shí)能動(dòng)性的版圖生成：在導(dǎo)線的布線程序中考慮相鄰導(dǎo)線的影響，以保證滿足性能方面的要求很有吸引力但是所要求的EDA工具非常復(fù)雜解決方法（I）估計(jì)和改進(jìn)：經(jīng)過(guò)細(xì)致的參數(shù)提取和模擬可以確定延解決方法（2）可預(yù)測(cè)的結(jié)構(gòu)：使用預(yù)先定義的、已知的或保守的布線結(jié)構(gòu)，保證電路既能滿足設(shè)計(jì)者提出的技術(shù)要求，又能使串?dāng)_不會(huì)引起失效密集型布線結(jié)構(gòu)避免最壞情形的產(chǎn)生編解碼技術(shù)解決方法（2）可預(yù)測(cè)的結(jié)構(gòu)：使用預(yù)先定義的、已知的或保守的布結(jié)構(gòu)化可預(yù)測(cè)的連線結(jié)構(gòu)Example:DenseWireFabric([SunilKathri])Trade-off:

線間串?dāng)_電容小了40倍，代價(jià)：2%的延時(shí)開銷，5％的面積和總電容開銷Also:FPGAs,VPGAs結(jié)構(gòu)化可預(yù)測(cè)的連線結(jié)構(gòu)Example:DenseWire數(shù)據(jù)編碼消除最惡劣情形EncoderDecoderBusInOut數(shù)據(jù)編碼消除最惡劣情形EncoderDecoderBusIn電容負(fù)載和電路性能復(fù)雜的設(shè)計(jì)中單個(gè)門常常需要驅(qū)動(dòng)很大的扇出，因而具有很大的電容負(fù)載總線、時(shí)鐘網(wǎng)絡(luò)、全局控制信號(hào)（set/reset)存儲(chǔ)器中的讀寫信號(hào)最壞情形發(fā)生在芯片內(nèi)外接口，此時(shí)負(fù)載有封裝導(dǎo)線、印刷電路板導(dǎo)線、連接的器件的輸入電容組成片外負(fù)載可以大至50pF，是標(biāo)準(zhǔn)片上負(fù)載的數(shù)千倍電容負(fù)載和電路性能復(fù)雜的設(shè)計(jì)中單個(gè)門常常需要驅(qū)動(dòng)很大的扇出，驅(qū)動(dòng)大電容負(fù)載VinVoutCLVDD

TransistorSizingCascadedBuffers驅(qū)動(dòng)大電容負(fù)載VinVoutCLVDDTransistor使用級(jí)聯(lián)緩沖器CL=20pFInOut12N0.25mmprocessCin=

2.5fFtp0=30psF=CL/Cin=8000fopt=3.6N=7tp=0.97ns(SeeChapter5)使用級(jí)聯(lián)緩沖器CL=20pFInOut12N0.25輸出緩沖器設(shè)計(jì)TransistorSizesforoptimally-sizedcascadedbuffertp

=0.97ns0.25mmprocess,CL=20pF需要一些柵極寬度大約為1.5mm的超大晶體管?。?！無(wú)法接受，因?yàn)橐粋€(gè)復(fù)雜芯片需要很多這樣的驅(qū)動(dòng)器！?。≥敵鼍彌_器設(shè)計(jì)TransistorSizesforop解決方法在大多數(shù)情況下并不需要達(dá)到最優(yōu)的緩沖器延時(shí)。片外通信常常能以片上時(shí)鐘速度的幾分之一進(jìn)行。放寬延時(shí)要求仍然可以使片外時(shí)鐘速度超過(guò)100MHz，但卻大大降低了對(duì)緩沖的要求。解決方法在大多數(shù)情況下并不需要達(dá)到最優(yōu)的緩沖器延時(shí)。片外通信DelayasaFunctionofFandN101357NumberofbufferstagesN91110,0001000100tp/tp0F=100F=1000F=10,000tp/tp0DelayasaFunctionofFandN輸出驅(qū)動(dòng)設(shè)計(jì)TradeoffPerformanceforAreaandEnergyGiventpmaxfindNandfAreaEnergy選擇較大的f有助于減小面積輸出驅(qū)動(dòng)設(shè)計(jì)TradeoffPerformancefo輸出驅(qū)動(dòng)器設(shè)計(jì)－再次考慮TransistorSizesofredesignedcascadedbuffertp

=1.89ns輸出驅(qū)動(dòng)器設(shè)計(jì)－再次考慮TransistorSizeso大尺寸晶體管的實(shí)現(xiàn)G(ate)S(ource)D(rain)MultipleContactssmalltransistorsinparallelReducesdiffusioncapacitanceReducesgateresistance大尺寸晶體管意味著很長(zhǎng)的柵極連線，而較長(zhǎng)的多晶硅線具有較高的電阻，從而降低了開關(guān)性能大尺寸晶體管的實(shí)現(xiàn)G(ate)S(ource)D(rain)BondingPadDesignBondingPadOutInVDDGND100mmGNDOutBondingPadDesignBondingPadOESDProtectionWhenachipisconnectedtoaboard,thereisunknown(potentiallylarge)staticvoltagedifferenceEqualizingpotentialsrequires(large)chargeflowthroughthepadsDiodessinkthischargeintothesubstrate–needguardringstopickitup.ESDProtectionWhenachipiscESDProtectionDiodeESDProtectionDiode芯片封裝Bondwires(~25m)areused

toconnectthepackagetothechip

Padsarearrangedinaframe

aroundthechipPadsarerelativelylarge

(~100min0.25mtechnology),

withlargepitch(100m)Manychipsareasare‘padlimited’芯片封裝Bondwires(~25m)areusePadFrameLayoutDiePhotoPadFrameLayoutDiePhoto驅(qū)動(dòng)器電路Analternativeis‘flip-chip’:PadsaredistributedaroundthechipThesolderingballsareplacedonpadsThechipis‘flipped’ontothepackageCanhavemanymorepads驅(qū)動(dòng)器電路Analternativeis‘flip-c三態(tài)緩沖InEnEnVDDOutOut=In.En+Z.EnVDDInEnEnOutIncreasedoutputdrive三態(tài)緩沖InEnEnVDDOutOut=In.En+互連DealingwithResistance互連DealingwithResistance9.3電阻效應(yīng)的影響WehavealreadylearnedhowtodriveRCinterconnectImpactofresistanceiscommonlyseeninpowersupplydistribution:IRdropVoltagevariationsPowersupplyisdistributedtominimizetheIRdropandthechangeincurrentduetoswitchingofgates9.3電阻效應(yīng)的影響Wehavealreadylear9.3.1RIIntroducedNoiseVDD-△VM1XIR9RfpreVDDIV△V△9.3.1RIIntroducedNoiseVDD-電源/地分布電源/地分布使用第三層金屬走電源/地(EV4)在EV4設(shè)計(jì)中，增加了又厚又寬的第三層金屬線Powersuppliedfromtwosidesofthedievia3rdmetallayer2ndmetallayerusedtoformpowergrid90%of3rdmetallayerusedforpower/clockroutingMetal3Metal2Metal1CourtesyCompaq使用第三層金屬走電源/地(EV4)在EV4設(shè)計(jì)中，增加了又4層金屬方法(EV5)

－3,4層用于電源/地的走線4th“coarseandthick”metallayeraddedtothetechnologyforEV5designPowersuppliedfromfoursidesofthedieGridstrappingdoneallincoarsemetal90%of3rdand4thmetalsusedforpower/clockroutingMetal3Metal2Metal1Metal4CourtesyCompaq4層金屬方法(EV5)

－3,4層用于電源/地的走線4th2referenceplanemetallayersaddedtothetechnologyforEV6designSolidplanesdedicatedtoVdd/VssSignificantlylowersresistanceofgridLowerson-chipinductance6層金屬方法–EV6Metal4Metal2Metal1RP2/VddRP1/VssMetal3CourtesyCompaq2referenceplanemetallayers電阻與功耗分布問(wèn)題Source:Cadence

RequiresfastandaccuratepeakcurrentpredictionHeavilyinfluencedbypackagingtechnologyBeforeAfter電阻與功耗分布問(wèn)題Source:CadenceRequi9.3.2Electromigration(1)電遷移9.3.2Electromigration(1)電遷移Electromigration(2)電遷移的發(fā)生率取決于溫度、晶體結(jié)構(gòu)和平均電流密度。其中在設(shè)計(jì)中，只有平均電流密度可控。通常使電流保持在低于0.5~1mA/um可以防止電遷移。Electromigration(2)電遷移的發(fā)生率取決于9.3.3ResistivityandPerformanceDiffusedsignal

propagationDelay~L2CN-1CNC2R1R2C1TrVinRN-1RNThedistributedrc-line9.3.3ResistivityandPerformaTheGlobalWireProblemChallenges精確的同步和正確的操作設(shè)計(jì)技術(shù)新互連材料插入中繼器優(yōu)化互連結(jié)構(gòu)TheGlobalWireProblemChallenInterconnectProjections

Low-kdielectricsBothdelayandpowerarereducedbydroppinginterconnectcapacitanceTypesoflow-kmaterialsinclude:inorganic(SiO2),organic(Polyimides)andaerogels(ultralow-k)eInterconnectProjections

Low-kInterconnectProjections:CopperCopperisplannedinfullsub-0.25mmprocessflowsandlarge-scaledesigns(IBM,Motorola,IEDM97)Withcladdingandothereffects,Cu~2.2mW-cmvs.3.5forAl(Cu)40%reductioninresistanceElectromigrationimprovement;100Xlongerlifetime(IBM,IEDM97)Electromigrationisalimitingfactorbeyond0.18mmifAlisused(HP,IEDM95)ViasInterconnectProjections:CoppDiagonalWiringyxdestinationManhattansourcediagonal

20+%InterconnectlengthreductionClockspeed

Signalintegrity

Powerintegrity

15+%Smallerchips

plus30+%viareductionCourtesyCadenceX-initiativeDiagonalWiringyxdestinationMaUsingBypassesDriverPolysiliconwordlinePolysiliconwordlineMetalwordlineMetalbypassDrivingawordlinefrombothsidesUsingametalbypassWLWLKcellsUsingBypassesDriverPolysilicoReducingRC-delayRepeater(chapter5)ReducingRC-delayRepeater(chapRepeaterInsertion(Revisited)TakingtherepeaterloadingintoaccountForagiventechnologyandagiveninterconnectlayer,thereexistsanoptimallengthofthewiresegmentsbetweenrepeaters.Thedelayofthesewiresegmentsisindependentoftheroutinglayer!RepeaterInsertion(Revisited)9.4INTERCONNECTDealingwithInductanceSKIPPED9.4INTERCONNECTDealingwithThe“Network-on-a-Chip”Embedded

ProcessorsMemorySub-systemAccelatorsConfigurable

AcceleratorsPeripheralsInterconnectBackplaneThe“Network-on-a-Chip”EmbeddeLdi/dtImpactofinductanceonsupplyvoltages:ChangeincurrentinducesachangeinvoltageLongersupplylineshavelargerLCLV’DDVDDLi(t)VoutVinGND’LLdi/dtImpactofinductanceonLdi/dt:Simulation00.511.52x10-900.511.522.5Vout

(V)00.511.52x10-900.020.04iL

(A)00.511.52x10-900.51VL

(V)time(nsec)00.511.52x10-900.511.522.500.511.52x10-900.020.0400.511.52x10-900.51time(nsec)Inputrise/falltime:50psecInputrise/falltime:800psecdecoupledWithoutinductorsWithinductorsLdi/dt:Simulation00.511.52xDealingwithLdi/dtSeparatepowerpinsforI/Opadsandchipcore.Multiplepowerandgroundpins.Carefulselectionofthepositionsofthepowerandgroundpinsonthepackage.Increasetheriseandfalltimesoftheoff-chipsignalstothemaximumextentallowable.Schedulecurrent-consumingtransitions.Useadvancedpackagingtechnologies.Adddecouplingcapacitancesontheboard.Adddecouplingcapacitancesonthechip.DealingwithLdi/dtSeparatepoChoosingtheRightPinChoosingtheRightPinDecouplingCapacitorsDecouplingcapacitorsareadded:ontheboard(rightunderthesupplypins)onthechip(underthesupplystraps,nearlargebuffers)DecouplingCapacitorsDecouplinDe-couplingCapacitorRatiosEV4totaleffectiveswitchingcapacitance=12.5nF 128nFofde-couplingcapacitancede-coupling/switchingcapacitance~10xEV513.9nFofswitchingcapacitance160nFofde-couplingcapacitanceEV634nFofeffectiveswitchingcapacitance320nFofde-couplingcapacitance--notenough!Source:B.Herrick(Compaq)De-couplingCapacitorRatiosEVEV6De-couplingCapacitanceDesignforIdd=25A@Vdd=2.2V,f=600MHz0.32-μFofon-chipde-couplingcapacitancewasaddedUndermajorbussesandaroundmajorgriddedclockdriversOccupies15-20%ofdiearea1-μF2-cm2WirebondAttachedChipCapacitor(WACC)significantlyincreases“Near-Chip”de-coupling160Vdd/VssbondwirepairsontheWACCminimizeinductanceSource:B.Herrick(Compaq)EV6De-couplingCapacitanceDesEV6WACCSource:B.Herrick(Compaq)EV6WACCSource:B.Herrick(CoTheTransmissionLineTheWaveEquationVinVoutrgcrrxgcrgcgcllllTheTransmissionLineTheWaveDesignRulesofThumbTransmissionlineeffectsshouldbeconsideredwhentheriseorfalltimeoftheinputsignal(tr,tf)issmallerthanthetime-of-flightofthetransmissionline(tflight).tr(tf)<<2.5tflightTransmissionlineeffectsshouldonlybeconsideredwhenthetotalresistanceofthewireislimited:

R<5Z0Thetransmissionlineisconsideredlosslesswhenthetotalresistanceissubstantiallysmallerthanthecharacteristicimpedance,

R<Z0/2DesignRulesofThumbTransmissShouldwebeworried?Transmissionlineeffectscauseovershootingandnon-monotonicbehaviorClocksignalsin400MHzIBMMicroprocessor(measuredusinge-beamprober)[Restle98]Shouldwebeworried?TransmissMatchedTerminationZ0ZLZ0SeriesSourceTerminationZ0Z0ZSParallelDestinationTerminationMatchedTerminationZ0ZLZ0SerieSegmentedMatchedLineDriverZ0c1c2s0s1s2sncnZLGNDVDDInSegmentedMatchedLineDriverZParallelTermination─

TransistorsasResistors0.5NormalizedResistance(V)1PMOSwith-1VbiasNMOS-PMOSPMOSonlyNMOSonly1.5VR

(Volt)22.502OutMrVddOutMrVddVbbOutMrpMrnVddParallelTermination─

TransistOutputDriverwithVaryingTerminationsVout

(V)Vout

(V)1234time(sec)ReviseddesignwithmatcheddriverimpedanceVsVdVin567801012341234InitialdesignVsVdVin56780101234VinL=2.5nHVDDVsVdVDDClampingDiodesCL=5pFCLL=2.5nHL=2.5nHZ0=50W275120OutputDriverwithVaryingTerThe“Network-on-a-Chip”Embedded

ProcessorsMemorySub-systemAccelatorsConfigurable

AcceleratorsPeripheralsInterconnectBackplaneThe“Network-on-a-Chip”Embedde數(shù)字集成電路第九講互連問(wèn)題數(shù)字集成電路第九講互連問(wèn)題互連參數(shù)的影響?降低可靠性?影響性能

增加延時(shí)

增加功耗參數(shù)的分類?電容?電阻?電感互連參數(shù)的影響?降低可靠性?影響性能參數(shù)的分類?電容?9.2INTERCONNECTDealingwithCapacitance9.2INTERCONNECTDealingwith9.2.1電容串?dāng)_效應(yīng)9.2.1電容串?dāng)_效應(yīng)電容串?dāng)_效應(yīng)

動(dòng)態(tài)節(jié)點(diǎn)3x1mmoverlap:0.19VdisturbanceCYCXYVDDPDNCLKCLKIn1In2In3YX2.5V0V電容串?dāng)_效應(yīng)

動(dòng)態(tài)節(jié)點(diǎn)3x1mmoverlap:0電容串?dāng)_效應(yīng)

被驅(qū)動(dòng)節(jié)點(diǎn)tXY=RY(CXY+CY)Keeptime-constantsmallerthanrisetimeV(Volt)00.50.450.40.35010.80.6t(nsec)0.40.2XYVXRYCXYCYtr↑電容串?dāng)_效應(yīng)

被驅(qū)動(dòng)節(jié)點(diǎn)tXY=RY(CXY+CY)Ke克服電容串?dāng)_的方法避免浮空節(jié)點(diǎn)對(duì)串?dāng)_敏感的節(jié)點(diǎn)，如預(yù)充電總線等，應(yīng)當(dāng)增加保持器件以降低阻抗敏感節(jié)點(diǎn)應(yīng)當(dāng)很好地與全擺幅信號(hào)隔離在滿足時(shí)序約束的范圍內(nèi)盡可能加大上升（下降）時(shí)間這會(huì)對(duì)短路功耗有影響在敏感的低擺幅布線網(wǎng)絡(luò)中采用差分信號(hào)傳輸方法，使串?dāng)_信號(hào)變?yōu)椴粫?huì)影響電路工作的共模干擾信號(hào)同一層上的兩條導(dǎo)線平行走線的距離不要太長(zhǎng)，減小線間電容兩個(gè)信號(hào)之間增加屏蔽線，能有效地使線間電容變?yōu)橐粋€(gè)接地電容，從而消除干擾不同層上信號(hào)之間的線間電容可以通過(guò)增加額外的布線層來(lái)進(jìn)一步減小克服電容串?dāng)_的方法避免浮空節(jié)點(diǎn)屏蔽GNDGND屏蔽線襯底

(GND)屏蔽層VDD屏蔽GNDGND屏蔽線襯底(GND)屏蔽層VDD9.2.2串?dāng)_與性能Cc-

當(dāng)相鄰的信號(hào)線向相反的方向翻轉(zhuǎn)時(shí)，延時(shí)增加延時(shí)依賴于相鄰信號(hào)線的活動(dòng)Miller效應(yīng)

-Bothterminalsofcapacitorareswitchedinoppositedirections

(0Vdd,Vdd

0)-Effectivevoltageisdoubledandadditionalchargeisneeded

(fromQ=CV)9.2.2串?dāng)_與性能Cc-當(dāng)相鄰的信號(hào)線向相反的方向翻轉(zhuǎn)時(shí)串?dāng)_對(duì)延時(shí)的影響risratiobetweencapacitancetoGNDandtoneighbor在最壞情況下，g＝5，表明僅僅由于線上翻轉(zhuǎn)方向的影響，導(dǎo)線延時(shí)和最好情形之間就可以有500％的差別！tp,k=gCw(0.38Rw+0.69RD)Cw=cwL;Rw=rwLCc串?dāng)_對(duì)延時(shí)的影響risratiobetweenca解決方法（I）估計(jì)和改進(jìn)：經(jīng)過(guò)細(xì)致的參數(shù)提取和模擬可以確定延時(shí)的瓶頸，然后對(duì)電路進(jìn)行適當(dāng)?shù)男薷淖畛Ｊ褂玫姆椒?。缺點(diǎn)：在整個(gè)設(shè)計(jì)生產(chǎn)過(guò)程中需要多次的反復(fù)，費(fèi)時(shí)能動(dòng)性的版圖生成：在導(dǎo)線的布線程序中考慮相鄰導(dǎo)線的影響，以保證滿足性能方面的要求很有吸引力但是所要求的EDA工具非常復(fù)雜解決方法（I）估計(jì)和改進(jìn)：經(jīng)過(guò)細(xì)致的參數(shù)提取和模擬可以確定延解決方法（2）可預(yù)測(cè)的結(jié)構(gòu)：使用預(yù)先定義的、已知的或保守的布線結(jié)構(gòu)，保證電路既能滿足設(shè)計(jì)者提出的技術(shù)要求，又能使串?dāng)_不會(huì)引起失效密集型布線結(jié)構(gòu)避免最壞情形的產(chǎn)生編解碼技術(shù)解決方法（2）可預(yù)測(cè)的結(jié)構(gòu)：使用預(yù)先定義的、已知的或保守的布結(jié)構(gòu)化可預(yù)測(cè)的連線結(jié)構(gòu)Example:DenseWireFabric([SunilKathri])Trade-off:

線間串?dāng)_電容小了40倍，代價(jià)：2%的延時(shí)開銷，5％的面積和總電容開銷Also:FPGAs,VPGAs結(jié)構(gòu)化可預(yù)測(cè)的連線結(jié)構(gòu)Example:DenseWire數(shù)據(jù)編碼消除最惡劣情形EncoderDecoderBusInOut數(shù)據(jù)編碼消除最惡劣情形EncoderDecoderBusIn電容負(fù)載和電路性能復(fù)雜的設(shè)計(jì)中單個(gè)門常常需要驅(qū)動(dòng)很大的扇出，因而具有很大的電容負(fù)載總線、時(shí)鐘網(wǎng)絡(luò)、全局控制信號(hào)（set/reset)存儲(chǔ)器中的讀寫信號(hào)最壞情形發(fā)生在芯片內(nèi)外接口，此時(shí)負(fù)載有封裝導(dǎo)線、印刷電路板導(dǎo)線、連接的器件的輸入電容組成片外負(fù)載可以大至50pF，是標(biāo)準(zhǔn)片上負(fù)載的數(shù)千倍電容負(fù)載和電路性能復(fù)雜的設(shè)計(jì)中單個(gè)門常常需要驅(qū)動(dòng)很大的扇出，驅(qū)動(dòng)大電容負(fù)載VinVoutCLVDD

TransistorSizingCascadedBuffers驅(qū)動(dòng)大電容負(fù)載VinVoutCLVDDTransistor使用級(jí)聯(lián)緩沖器CL=20pFInOut12N0.25mmprocessCin=

2.5fFtp0=30psF=CL/Cin=8000fopt=3.6N=7tp=0.97ns(SeeChapter5)使用級(jí)聯(lián)緩沖器CL=20pFInOut12N0.25輸出緩沖器設(shè)計(jì)TransistorSizesforoptimally-sizedcascadedbuffertp

=0.97ns0.25mmprocess,CL=20pF需要一些柵極寬度大約為1.5mm的超大晶體管！??！無(wú)法接受，因?yàn)橐粋€(gè)復(fù)雜芯片需要很多這樣的驅(qū)動(dòng)器?。。≥敵鼍彌_器設(shè)計(jì)TransistorSizesforop解決方法在大多數(shù)情況下并不需要達(dá)到最優(yōu)的緩沖器延時(shí)。片外通信常常能以片上時(shí)鐘速度的幾分之一進(jìn)行。放寬延時(shí)要求仍然可以使片外時(shí)鐘速度超過(guò)100MHz，但卻大大降低了對(duì)緩沖的要求。解決方法在大多數(shù)情況下并不需要達(dá)到最優(yōu)的緩沖器延時(shí)。片外通信DelayasaFunctionofFandN101357NumberofbufferstagesN91110,0001000100tp/tp0F=100F=1000F=10,000tp/tp0DelayasaFunctionofFandN輸出驅(qū)動(dòng)設(shè)計(jì)TradeoffPerformanceforAreaandEnergyGiventpmaxfindNandfAreaEnergy選擇較大的f有助于減小面積輸出驅(qū)動(dòng)設(shè)計(jì)TradeoffPerformancefo輸出驅(qū)動(dòng)器設(shè)計(jì)－再次考慮TransistorSizesofredesignedcascadedbuffertp

=1.89ns輸出驅(qū)動(dòng)器設(shè)計(jì)－再次考慮TransistorSizeso大尺寸晶體管的實(shí)現(xiàn)G(ate)S(ource)D(rain)MultipleContactssmalltransistorsinparallelReducesdiffusioncapacitanceReducesgateresistance大尺寸晶體管意味著很長(zhǎng)的柵極連線，而較長(zhǎng)的多晶硅線具有較高的電阻，從而降低了開關(guān)性能大尺寸晶體管的實(shí)現(xiàn)G(ate)S(ource)D(rain)BondingPadDesignBondingPadOutInVDDGND100mmGNDOutBondingPadDesignBondingPadOESDProtectionWhenachipisconnectedtoaboard,thereisunknown(potentiallylarge)staticvoltagedifferenceEqualizingpotentialsrequires(large)chargeflowthroughthepadsDiodessinkthischargeintothesubstrate–needguardringstopickitup.ESDProtectionWhenachipiscESDProtectionDiodeESDProtectionDiode芯片封裝Bondwires(~25m)areused

toconnectthepackagetothechip

Padsarearrangedinaframe

aroundthechipPadsarerelativelylarge

(~100min0.25mtechnology),

withlargepitch(100m)Manychipsareasare‘padlimited’芯片封裝Bondwires(~25m)areusePadFrameLayoutDiePhotoPadFrameLayoutDiePhoto驅(qū)動(dòng)器電路Analternativeis‘flip-chip’:PadsaredistributedaroundthechipThesolderingballsareplacedonpadsThechipis‘flipped’ontothepackageCanhavemanymorepads驅(qū)動(dòng)器電路Analternativeis‘flip-c三態(tài)緩沖InEnEnVDDOutOut=In.En+Z.EnVDDInEnEnOutIncreasedoutputdrive三態(tài)緩沖InEnEnVDDOutOut=In.En+互連DealingwithResistance互連DealingwithResistance9.3電阻效應(yīng)的影響WehavealreadylearnedhowtodriveRCinterconnectImpactofresistanceiscommonlyseeninpowersupplydistribution:IRdropVoltagevariationsPowersupplyisdistributedtominimizetheIRdropandthechangeincurrentduetoswitchingofgates9.3電阻效應(yīng)的影響Wehavealreadylear9.3.1RIIntroducedNoiseVDD-△VM1XIR9RfpreVDDIV△V△9.3.1RIIntroducedNoiseVDD-電源/地分布電源/地分布使用第三層金屬走電源/地(EV4)在EV4設(shè)計(jì)中，增加了又厚又寬的第三層金屬線Powersuppliedfromtwosidesofthedievia3rdmetallayer2ndmetallayerusedtoformpowergrid90%of3rdmetallayerusedforpower/clockroutingMetal3Metal2Metal1CourtesyCompaq使用第三層金屬走電源/地(EV4)在EV4設(shè)計(jì)中，增加了又4層金屬方法(EV5)

－3,4層用于電源/地的走線4th“coarseandthick”metallayeraddedtothetechnologyforEV5designPowersuppliedfromfoursidesofthedieGridstrappingdoneallincoarsemetal90%of3rdand4thmetalsusedforpower/clockroutingMetal3Metal2Metal1Metal4CourtesyCompaq4層金屬方法(EV5)

－3,4層用于電源/地的走線4th2referenceplanemetallayersaddedtothetechnologyforEV6designSolidplanesdedicatedtoVdd/VssSignificantlylowersresistanceofgridLowerson-chipinductance6層金屬方法–EV6Metal4Metal2Metal1RP2/VddRP1/VssMetal3CourtesyCompaq2referenceplanemetallayers電阻與功耗分布問(wèn)題Source:Cadence

RequiresfastandaccuratepeakcurrentpredictionHeavilyinfluencedbypackagingtechnologyBeforeAfter電阻與功耗分布問(wèn)題Source:CadenceRequi9.3.2Electromigration(1)電遷移9.3.2Electromigration(1)電遷移Electromigration(2)電遷移的發(fā)生率取決于溫度、晶體結(jié)構(gòu)和平均電流密度。其中在設(shè)計(jì)中，只有平均電流密度可控。通常使電流保持在低于0.5~1mA/um可以防止電遷移。Electromigration(2)電遷移的發(fā)生率取決于9.3.3ResistivityandPerformanceDiffusedsignal

propagationDelay~L2CN-1CNC2R1R2C1TrVinRN-1RNThedistributedrc-line9.3.3ResistivityandPerformaTheGlobalWireProblemChallenges精確的同步和正確的操作設(shè)計(jì)技術(shù)新互連材料插入中繼器優(yōu)化互連結(jié)構(gòu)TheGlobalWireProblemChallenInterconnectProjections

Low-kdielectricsBothdelayandpowerarereducedbydroppinginterconnectcapacitanceTypesoflow-kmaterialsinclude:inorganic(SiO2),organic(Polyimides)andaerogels(ultralow-k)eInterconnectProjections

Low-kInterconnectProjections:CopperCopperisplannedinfullsub-0.25mmprocessflowsandlarge-scaledesigns(IBM,Motorola,IEDM97)Withcladdingandothereffects,Cu~2.2mW-cmvs.3.5forAl(Cu)40%reductioninresistanceElectromigrationimprovement;100Xlongerlifetime(IBM,IEDM97)Electromigrationisalimitingfactorbeyond0.18mmifAlisused(HP,IEDM95)ViasInterconnectProjections:CoppDiagonalWiringyxdestinationManhattansourcediagonal

20+%InterconnectlengthreductionClockspeed

Signalintegrity

Powerintegrity

15+%Smallerchips

plus30+%viareductionCourtesyCadenceX-initiativeDiagonalWiringyxdestinationMaUsingBypassesDriverPolysiliconwordlinePolysiliconwordlineMetalwordlineMetalbypassDrivingawordlinefrombothsidesUsingametalbypassWLWLKcellsUsingBypassesDriverPolysilicoReducingRC-delayRepeater(chapter5)ReducingRC-delayRepeater(chapRepeaterInsertion(Revisited)TakingtherepeaterloadingintoaccountForagiventechnologyandagiveninterconnectlayer,thereexistsanoptimallengthofthewiresegmentsbetweenrepeaters.Thedelayofthesewiresegmentsisindependentoftheroutinglayer!RepeaterInsertion(Revisited)9.4INTERCONNECTDealingwithInductanceSKIPPED9.4INTERCONNECTDealingwithThe“Network-on-a-Chip”Embedded

ProcessorsMemorySub-systemAccelatorsConfigurable

AcceleratorsPeripheralsInterconnectBackplaneThe“Network-on-a-Chip”EmbeddeLdi/dtImpactofinductanceonsupplyvoltages:ChangeincurrentinducesachangeinvoltageLongersupplylineshavelargerLCLV’DDVDDLi(t)VoutVinGND’LLdi/dtImpactofinductanceonLdi/dt:Simulation00.511.52x10-900.511.522.5Vout

(V)00.511.52x10-900.020.04iL

(A)00.511.52x10-900.51VL

(V)time(nsec)00.511.52x10-900.511.522.500.511.52x10-900.020.0400.511.52x10-900.51time(nsec)Inputrise/falltime:50psecInputrise/falltime:800psecdecoupledWithoutinductorsWithinductorsLdi/dt:Simulation00.511.52xDealingwithLdi/dtSeparatepowerpinsforI/Opadsandchipcore.Multiplepowerandgroundpins.Carefulselectionofthepositionsofthepowerandgroundpinsonthepackage.Increasetheriseandfalltimesoftheoff-chipsignalstothemaximumextentallowable.Schedulecurrent-consumingtransitions.Useadvancedpackagingtechnologies.Adddecouplingcapacitancesontheboard.Adddecouplingcapacitancesonthechip.DealingwithLdi/dtSeparatepoChoosingtheRightPinChoosingtheRightPinDecouplingCapacitorsDecouplingcapacitorsareadded:ontheboard(rightunderthesupplypins)onthechip(underthesupplystraps,nearlargebuffers)DecouplingCapacitorsDecouplinDe-couplingCapacitorRatiosEV4totaleffectiveswitchingcapacitance=12.5nF 128nFofde-couplingcapacitancede-coupling/switchingcapacitance~10xEV513.9nFofswitchingcapacitance160nFofde-couplingcapacitanceEV634nFofeffectiveswitchingcapacitance320nFofde-couplingcapacitance--notenough!Source:B