基帶板原理圖設(shè)計(jì)文檔

--.z..z.1、系統(tǒng)框圖

基帶板原理圖設(shè)計(jì)文檔根據(jù)與41所溝通，系統(tǒng)框圖如下，基帶板與RF、主控板、時(shí)序板、中頻R*和中頻T*板的連接關(guān)系如下，為了實(shí)現(xiàn)LTE基帶處理的各種功能和與其他各個(gè)處理板的數(shù)據(jù)交換和接口需要，進(jìn)展了基帶板原理圖設(shè)計(jì)。2、功能要求：基帶板要完成的功能包括：協(xié)議軟件的處理、物理層軟件的處理、系統(tǒng)定時(shí)和對(duì)RF的控制數(shù)據(jù)處理。為了完成這些容，系統(tǒng)包含arm、dsp和fpga三個(gè)主要器件，其中ARM完成協(xié)議軟件處理、DSP負(fù)責(zé)處理物理層軟件中的局部容、FPGA完成系統(tǒng)定時(shí)和物理層算法的局部容。3、系統(tǒng)框圖ARM:完成操作系統(tǒng)及協(xié)議、應(yīng)用等功能，其支持的借口比較豐富；接口描述：DRAMcontroller：DDRRAM；SROMcontroller：FLASH，與DSP、FPGA共用，用于boot代碼的存儲(chǔ)；FPGA上的RAM，預(yù)留，防止協(xié)議中有算法需要用硬件實(shí)現(xiàn)；雙端口RAM1，用于與DSP交換數(shù)據(jù)；雙端口RAM2，用于與41所應(yīng)用板交換數(shù)據(jù)；I2C：用于power、clk芯片的控制；I2S：用于codic和bluetooth；SPI：與FPGA間發(fā)送控制信息；UART：用于trace;USB：用于應(yīng)用；GPIO：用于與FPGA和DSP之間產(chǎn)生硬件中斷；JTAG：調(diào)試接口；DSP:完成物理層流程及算法；EMIFA：FLASH，與ARM、FPGA共用，用于boot代碼的存儲(chǔ)；FPGA上的RAM，用于與FPGA數(shù)據(jù)交換；雙端口RAM1，用于與ARM交換數(shù)據(jù)；DDR2：DDRRAM；I2C：與FPGA相連，用于交換控制信息；McBSP0：用于CODICMcBSP1：與FPGA相連，用于交換數(shù)據(jù)信息；RapidIO：與FPGA相連，用于交換數(shù)據(jù)信息；GPIO：用于與FPGA和ARM之間產(chǎn)生硬件中斷；FPGA:完成系統(tǒng)定時(shí)、射頻數(shù)據(jù)的接收及局部物理層算法；PCI：用于與射頻交換數(shù)據(jù)，需要確認(rèn)。4、時(shí)鐘設(shè)計(jì)LET要求的采樣時(shí)鐘：122.88MHzARM工作時(shí)鐘：12MHz，可以通過(guò)外部的晶振提供或外部的時(shí)鐘提供；27MHz，用于其中的*些模塊，可以選擇是否使能；32.768KHz，看門(mén)狗時(shí)鐘；DSP工作時(shí)鐘：CLKIN1：33.3~66.6MHz 選50MHzCLKIN2：12.5~26.7MHz 選25MHzEMIFCLK：160或200MHz選200SRIOCLK：125或或312.5MHz 選擇125MHz備156.25MHz20MHz，通過(guò)TICDCE937產(chǎn)生DSPARM的輸入時(shí)鐘OUTFreqY120MHzToFPGAY225MHzDSPPLL1Y3125MHzSRIOY450MHzDSPPLL2Y5200MHzDSP_EMIFAY612MHzARMY748MHzY8122.88MHzLTEtoFPGAY9122.88MHz考慮到板子單獨(dú)使用和與41所接口使用的情況：?jiǎn)为?dú)使用安上述設(shè)置使用4141122.88MHzCPLD15.36MHz再輸出到CDCE946后產(chǎn)生相應(yīng)的其他時(shí)鐘，輸入為：OUTFreqY225MHzDSPPLL1Y3125MHzSRIOY450MHzDSPPLL2Y5200MHzDSP_EMIFAY612MHzARMY748MHzSRIOCLK：125312.55電源設(shè)計(jì)需求：6410、、、3.3VMHz選擇125MHz備156.25MHz--SignalVDDALIVEI/OPDescriptionInternalpowerforaliveblockVoltage1.2VDDARMPInternalpowerforARM1176coreandcache1.1/1.2VDDINTPInternalpowerforlogic1.2VDDMPLLPPowerforMPLLcore1.2VDDAPLLPPowerforAPLLcore1.2VDDEPLLPPowerforEPLLcore1.2VDDOTGPPowerforUSBOTGPHY3.3VDDOTGIPInternalpowerforUSBOTGPHY1.2VDDMMCPIOpowerforSDMMC1.8~3.3VDDHIPIOpowerforHostI/F1.8~3.3VDDLCDPIOpowerforLCD1.8~3.3VDDPCMPIOpowerforPCM(AudioI/F?I2S,AC97)1.8~3.3VDDE*TPIOpowerfore*ternalI/F(UART,I2C,CameraI/F,etc.)1.8~3.3VDDSYSPIOpowerforsystemcontrol.(Clock,reset,operationmode,JTAG,etc)1.8~3.3VDDUHPPowerforUSBHost3.3VDDADCPPowerforADCcoreandIO3.3VDDDACPPowerforDACcoreandIO3.3VDDRTCPPowerforRTClogicandIO1.8~3.0VDDM0PIOpowerforMemoryPort01.8~3.3VDDSSPIOpowerforATAIOmu*edinMEM0port1.8~3.3VDDM1PIOpowerforMemoryPort11.8/2.56455SignalI/OSignalI/OREFSSTLDescription(DVDD1/2)-VreferenceforSSTLbuffer(DDR2MemoryController).ThisinputvoltagecanbegenerateddirectlyfromDDD18usingtwo1-kresistorstoformaresistordividercircuit.(DVDD1/2)-VreferenceforHSTLbuffer(EMACRGMII).REFHSTLcanbeVoltVA1.8VVREFHSTLA1.5V. z.--generateddirectlygenerateddirectlyfromDDD15usingtwo1-kdividercircuit.resistorstoformaresistorDDADDRMDD12DVDDRS1.8-VI/Osupplyvoltage.〔SRIOregulatorsupply〕1.8AVASRIOanalogsupply:1.25-VI/Osupplyvoltage(-1000and-1200devices)1.2-VI/Osupplyvoltage(-850and-720devices).Donotusecoresupply.1.21.2AVDLL1A1.8-VI/Osupplyvoltage.1.8AVDLL2A1.8-VI/Osupplyvoltage.1.8DV SDV SAV ADV SDVDD18 SDVDD33 SCV SFPGASignalVCCAU*VCCINTVCCOSRIOinterfacesupply:1.25-Vcoresupplyvoltage(-1000and-1200devices)1.2-Vcoresupplyvoltage(-850and-720devices).thesourceforthissupplyvoltagemustbethesameasthatofCVMainSRIOsupply:1.25-VI/Osupplyvoltage(-1000and-1200devices)1.2-VI/Osupplyvoltage(-850and-720devices).Donotusecoresupply.SRIOterminationsupply:1.25-VI/Osupplyvoltage(-1000and-1200devices).1.2-VI/Osupplyvoltage(-850and-720devices).Donotusecoresupply.1.8-Vor1.5-VI/OsupplyvoltagefortheRGMIIfunctionoftheEMAC.1.8-VI/Osupplyvoltage(DDR2MemoryController)3.3-VI/Osupplyvoltage1.25-Vcoresupplyvoltage(-1000and-1200devices).1.2-Vcoresupplyvoltage(-850and-720devices).I/O Description. z.DD1.21.21.21.21.21.21.81.51.83.31.21.2DDTDD15DD--.z..z.電源選擇：FPGA：VCCAU*2.53ATPS74401VCCINT1.010APTH04T240WVCCO3.310APTH04T240WDSP、ARM1.86APTH08T230W/TPS511001.21.81.21.83.31.25TPS65051PTH08T230WPTH04T240WPTH04T240WMasterSelectMAP1008,16OutputJTAG1011Input(TCK)SlaveSelectMAP1108,16,32InputSlaveSerial1111InputConfigurationModeMasterSerialMasterSPIMasterBPI-UpMasterBPI-DownM[2:0]ConfigurationModeMasterSerialMasterSPIMasterBPI-UpMasterBPI-DownM[2:0]000001011BusWidth118,168,16CCLKDirectionOutputOutputOutputOutputSlaveSelectMAP模式下：可以設(shè)置為DSPboot還是armboot，需要的信號(hào)：CCLK： 寫(xiě)使CS_B： 片選RDWR_B：GPIOslaveserial模式下：可以設(shè)置為DSPboot還是armCCLK： GPIOD_IN： GPIOAEA19/BOOTMODE3AEA18/BOOTMODE2AEA17/BOOTMODE1AEA16/BOOTMODE0AEA19/BOOTMODE3AEA18/BOOTMODE2AEA17/BOOTMODE1AEA16/BOOTMODE0設(shè)置Boot模式：0000-Noboot(defaultmode)0001-Hostboot(HPI)0010-Reserved0011-Reserved0100-EMIFA8-bitROMbootCFGGP[2:0]pinsmustbesetto000bduringresetforproperoperationofthePCIbootmode.0101-MasterI2Cboot0110-SlaveI2Cboot0111-Hostboot(PCI)1000thru1111-SerialRapidI/ObootconfigurationsAEA15/AECLKIN_SEL 0 EMIFA輸入時(shí)鐘選擇-AECLKIN(defaultmode)-SYSCLK4(CPU/*)ClockRate.TheSYSCLK4clockrateissoftwareselectabletheSoftwarePLL1Controller.Bydefault,SYSCLK4isselectedasCPU/8clockrate.AEA14/HPI_WIDTH 1

HPI總線寬度選擇-HPIoperatesasanHPI16(default).(HPIbusis16bitswide.HD[15:0]pinsareusedandtheremainingHD[31:16]pinsarereservedpinsintheHi-Zstate.)-HPIoperatesasanHPI32.AEA13/LENDIANAEA12/UTOPIA_EN

設(shè)置 DeviceEndianmode(LENDIAN)-SystemoperatesinBigEndianmode-SystemoperatesinLittleEndianmode(default)1 UTOPIAEnablebit(UTOPIA_EN)UTOPIAperipheralenable(functional)-UTOPIAdisabled;EthernetMAC(EMAC)andMDIOenable(default).EMAC/MDIOconfiguration(interface)[MII,RMII,GMIIorthestandaloneRGMII]controlledbytheMACSEL[1:0]bits.-UTOPIAenabled;EMACandMDIOdisabled[e*ceptwhentheMACSEL[1:0]bits11then,theEMAC/MDIORGMIIinterfaceisstillfunctional].AndifMACSEL[1:0]=11,theRGMIIstandalonepinfunctionscanbeused.AEA11AEA10/MACSEL1AEA9/MACSEL0

1 1kEMAC/MDIOinterfaceselectbitsAEA8/PCI_EEAI 0 AEA8:PCIauto-initializationviae*ternalI2CEEPROMIfthePCIperipheralisdisabled(PCI_ENpin=0),thispinmustnotbepulledup.0-PCIauto-initializationthroughI2CEEPROMisdisabled(default).1-PCIauto-initializationthroughI2CEEPROMisenabled.AEA7AEA6/PCI66 0 PCIFrequencySelection(PCI66)0-PCIoperatesat33MHz(default).1-PCIoperatesat66MHz.

IfthePCIperipheralisdisabled(PCI_EN=0),thispinmustnotbepulledup.AEA5/MCBSP1_ENASEYAS4C/LKOUT_ENAEA3AEA2/CFGGP2AEA1/CFGGP1

001000

McBSP1Enablebit(MCBSP1_EN)0-GPIOpinfunctionsenabled(default).1-McBSP1pinfunctionsenabled.SYSCLKOUTEnablepin(SYSCLKOUT_EN)0-GP[1]pinfunctionoftheSYSCLK4/GP[1]pinenabled(default).1-SYSCLK4pinfunctionoftheSYSCLK4/GP[1]pinenabled.SRIO使能：上拉SRIO不使能：下拉Configurat