設(shè)計參考、源碼手冊1746個zhcs336a

ZHCS336A–JUNE2011–REVISEDAUGUST查詢樣品 應(yīng)用范3至6節(jié)串聯(lián)電池支持，支持所有化學(xué)成 IC之間無需組±1mV146μs

bq76PL536A36節(jié)串聯(lián)鋰離子電池轉(zhuǎn)換器(ADC)；獨(dú)立電池電壓及溫度保護(hù)功能；電池平衡技術(shù)以及為用戶電路供電的高精度5V穩(wěn)壓器。9組ADC輸入（6組電池電壓、1組6體磚型 電壓及2組溫度輸入）和1組通用輸入 ECC-OTP寄存器中的配置數(shù)

ADC(ECC)OTPEPROM中，可為電池管理系統(tǒng)實(shí)現(xiàn)更高電源電壓范圍：6V至30V（連續(xù)），乃至36 5-V、3-mA集成型高精度LDO bq76PL536A可垂直堆棧，無需在IC之間添加 (SPIbq76PL536A之間運(yùn)行，從而Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddierstheretoappearsattheendofthisdatasheet.Copyright?2011–2012,TexasInstrumentsCopyright?2011–2012,TexasInstrumentsPRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheInstrumentsstandardwarranty.Productionprocessingdoes EnglishDataSheet:necessarilyincludetestingofallThesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedevicecedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.TYPICAL ???CELL_2-5???CELL_2-5Figure1.???CELL_2-5PINPIN ogVREFOHost-to-deviceinterface–ALERTconditiondetectedinthisorhigher(North)ICurrent-modeinputindicatingasystemstatuschangefromthenext-higherCurrent-modeoutputindicatingasystemstatuschangetothenextlowerOSwitched1-mAlimitedoutputfromPPower-supplyvoltage,connecttomost-positivecell+,tietoBAT2onPPower-supplyvoltage,connecttomost-positivecell+,tietoBAT1onOCell-balancecontrolOCell-balancecontrol8OCell-balancecontrol(1)Key:I=digitalinput,AI=oginput,O=digitaloutput,OD=open-drainoutput,T=3-stateoutput,P=6OCell-balancecontrol4OCell-balancecontrol2OCell-balancecontrolIHost-to-deviceinterface–initiatesasynchronousconversion.Pinhas250-nAinternalsinktoCurrent-modeoutputtothenext-higherbq76PL536AtoinitiateaIInputfromtheadjacentlowerbq76PL536AtoinitiateaIHost-to-deviceinterface–active-lowchipselectfromhost.Internal100-kΩpullupCurrent-modeoutputusedtoselectthenext-higherbq76PL536AforSPIICurrent-modeinputSPIchip-select(slave-select)fromthenext-lowerOHost-to-deviceinterface–conversioncomplete,data-readyICurrent-modeinputindicatingconversiondataisreadyfromnext-higherCurrent-modeoutputindicatingconversiondataisreadytothenextlowerOHost-to-deviceinterface–FAULTconditiondetectedinthisorhigher(North)ICurrent-modeinputindicatingasystemstatuschangefromthenext-higherCurrent-modeGeneral-purpose(differential)oginput,connecttoVSSifGeneral-purpose(differential)oginput,connecttoVSSifDigitalopen-drainI/O.A10-kΩto2-MΩpullup IHostinterfaceenable,0=enable,1=PInternalog5-VLDObypassconnection,requires2.2-μFceramiccapacitorforPInternaldigital5-VLDObypassconnection1,requires2.2-μFceramiccapacitorforstability.ThispinistiedinternallytoLDOD2.ThispinshouldbetiedtoLDOD2externally.PInternaldigital5-VLDObypassconnection2,requires2.2-μFceramiccapacitorforstability.ThispinistiedinternallytoLDOD1.ThispinshouldbetiedtoLDOD1externally.–No–No–NoP5-VuserLDOoutput,requires2.2-μFceramiccapacitorforIHost-to-deviceinterface–SPIclockfromCurrent-modeoutputSPIclocktothenext-higherICurrent-modeinputSPIclockfromthenext-lowerIHost-to-deviceinterface–datafromhosttodevice(hostMOSICurrent-modeoutputforSPIdatatothenext-higherICurrent-modeinputforSPIdatafromthenext-lowerOHost-to-deviceinterface–datafromdevicetohost(hostMISOsignal),3-statepin,250-nAinternalICurrent-modeinputforSPIdatafromthenext-lowerCurrent-modeoutputforSPIdatatothenext-lowerIFactorytestpin.ConnecttoVSSinusercircuitry.Thispinincludes~100-kΩinternalDifferentialtemperaturesensorDifferentialtemperaturesensorDifferentialtemperaturesensorDifferentialtemperaturesensorSense-voltageinputterminalfornegativeterminaloffirstcellSensevoltageinputterminalforpositiveterminalofthefirst9Sensevoltageinputterminalforthepositiveterminalofthesecond7Sensevoltageinputterminalforthepositiveterminalofthethird5Sensevoltageinputterminalforthepositiveterminalofthe3Sensevoltageinputterminalforthepositiveterminalofthefifth1SensevoltageinputterminalforthepositiveterminalofthesixthPInternalogvoltagereference(+),requires10-μF,low-ESRceramiccapacitortoAGNDfor34,P25,P––ThermalpadonbottomofPowerPAD?package;thismustbesolderedtosimilar-sizecopperareaonPCBandconnectedtoVSS,tomeetstatedspecificationsherein.Providesheat-sinkingtopart.PINOUT

6463626160646362616059585756555453525150171819202122232425262728293031ORDERINGPART–40°CTo64TQFPPowerPADbq76PL536APAP(1)Thebq76PL536APAPcanbeorderedintapeandreelasbq76PL536APAPT(ty1000)orbq76PL536APAPR(ty250).FUNCTIONALBLOCK

1.25V5V1.25V5V(User14bit+-LDO-LDO-CELLBALANCING

Figure2.bq76PL536ABlockLEVELLEVELSHIFTANDABSOLUTEUMoveroperating-airtemperaturerange(unlessotherwisenoted)Supplyvoltagerange,–0.3toVBATvoltagetoanyotherBATtoany–0.3toVInputvoltagerange,V–0.3toV–0.3toVCntoVCn-1,n=1to0toTS1+,TS1–,TS2+,–0.3to–0.3to–0.3toVREG50+DRDY_N,SDO_N,FAULT_N,VBAT–1toVBAT+CONV_S,SDI_S,SCLK_S,–2toOutputvoltagerange,CONV_N,SDI_N,SCLK_N,–0.3toVDRDY_S,SDO_S,FAULT_S,–0.3to–0.3toVREG50+CB1…CB6(CBREF=–0.3toREG50,–0.3toJunctionStoragetemperaturerange,–65toStressesbeyondthoselistedunderAbsoluteumRatingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly;functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder mendedOperatingConditionsisnotimplied.Exposuretoabsolute- um-ratedconditionsforextendedperiodsmayaffectdevicereliability.AllvoltagesarewithrespecttoVSSofthisdeviceexceptwhereotherwiseMENDEDOPERATINGTypicalvaluesstatedwhereTA=25oCandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40?Cto85oCandVBAT=7.2Vto30V(unlessotherwisenoted)SupplyVVCn–VC(n–1V00VC(n–TS1+,TS1–,TS2+,0Non-topICinDRDY_N,SDO_N,FAULT_N,BAT+TopICinDRDY_N,SDO_N,FAULT_N,Non-bottomICinCONV_S,SDI_S,SCLK_S,BottomICinCONV_S,SDI_S,SCLK_S,Non-bottomICinCONV_N,SDI_N,SCLK_N,1VBottomICinCONV_N,SDI_N,SCLK_N,Non-topICinDRDY_S,SDO_S,FAULT_S,BAT–TopICinDRDY_S,SDO_S,FAULT_S,ExternalREG50ExternalVREFExternalLDOxOperatingn=1toDevicespecificationsstatedwithinthisELECTRICALSUPPLYTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40°Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TESTSupplyNoloadatREG50,SCLK_N,SDI_N,SDO_N,FAULT_N,CONV_N,DRDY_S,ALERT_N,TSx,AUX,orCBx;CB_CTRL=0;CBT_CONTROL=0;CONV_H=0(notconverting),IO_CTRL[SLEEP]=ISupplyNoloadatREG50,SCLK_N,SDI_N,SDO_N,FAULT_N,CONV_N,DRDY_S,ALERT_N,TSx,AUX,orCBx;CB_CTRL=0;CBT_CONTROL=0;CONV_H=0(notconverting),IO_CTRL[SLEEP]=SupplyNoloadatREG50,SCLK_N,SDI_N,SDO_N,FAULT_N,CONV_N,DRDY_S,ALERT_N,TSx,orAUX;NoDCloadatCBx;CB_CTRL≠0;CBT_CONTROL≠0;CONV_H=0(notconverting),IO_CTRL[SLEEP]=0SupplyNoloadatREG50,SCLK_N,SDI_N,SDO_N,FAULT_N,CONV_N,DRDY_S,ALERT_N,TSxorCBx;CONV_S=1(conversionactive),IO_CTRL[SLEEP]= SupplyThermalshutdownactivated;ALERT_STATUS[TSD]=REG50,INTEGRATED5-VTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40°Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TESTOutputIREG50OUT≤0.5mA,C=2.2μFto225VΔVREG50LLine6V≤BAT≤27V,IREG50OUT=2Load0.2mA≤IREG50OUT≤20.2mA≤IREG50OUT≤5CurrentumAUX5AUXI=1mA,max.capacitance=VREG50Capacitor:CVAUX≤CVREG50/10ΩLEVELSHIFTTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40°Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TESTNorth1transmitterSCLK_N,CS_N,SDI_N,North0transmitterCS_N,1North0transmitterSCLK_N,SDI_N(BASEdeviceCS_H=1North0transmitterSCLK_N,SDI_N(BASEdeviceCS_H=South1receiverSCLK_S,CS_S,SDI_S,SouthreceiverSCLK_S,CS_S,SDI_S,South1transmitterALERT_N,FAULT_S,South0transmitterALERT_S,FAULT_S,1South0transmitterSDO_S(BASEdeviceCS_H=147North1receiverSDO_N,ALERT_N,FAULT_N,NorthreceiverSDO_N,ALERT_N,FAULT_N,CInputHOSTTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40°Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TESTLogic-leveloutputvoltage,high;SDO_H,FAULT_H,ALERT_H,DRDYCL=20pF,IOH<5 VLogic-leveloutputvoltage,low;SDO_H,FAULT_H,ALERT_H,DRDYCL=20pF,IOL<5VLogic-levelinputvoltage,high;SCLK_H,SDI_H,CS_H,2VLogic-levelinputvoltage,low;SCLK_H,SDI_H,CS_H,VCInputcapacitanceSCLK_H,SDI_H,CS_H,5InputleakagecurrentSCLK_H,SDI_H,CS_H,1(1)TotalsimultaneouscurrentdrawnfromallpinsislimitedbyLDODcurrentto≤10GENERALPURPOSEINPUT/OUTPUTTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40°Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TEST Logic-levelinputvoltage,Vin≤2V Logic-levelinputvoltage,V Outputhigh-voltagepullupdbyexternal~100-kΩV Logic-leveloutputvoltage,IOL=1VC Input5 Inputleakage1CELLBALANCINGCONTROLOUTPUTTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40°Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TESTOutput1V<VCELL<5OutputVCn-VOG-TO-DIGITALADCCommonTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40°Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TESTCONVhightoconversionstart(1)ADC_CONTROL[ADC_ON]=6ADC_CONTROL[ADC_ON]=ConversiontimeperselectedADC_CONTROL[ADC_ON]=16InputleakageNotIfADC_CONTROL[ADC_ON]=0,add500μstoconversiontimetoallowADCsubsystemtostabilize.Thisisself-timedbytheAdditional50ms(POR)isrequiredbeforefirstconversionaftera)initialcellconnection;orb)VBATfallsbelowADCspecificationsvalidwhendeviceisprogrammedfor6-μsconversiontimeperchannel,FUNC_CONFIG[ADCT1:0]=PlustCONV_START,i.e.,ifdeviceisprogrammedforsixchannelconversions,totaltimeisapproximay6×6+6=42VCn(Cell)TypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40?Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted),FUNCTION_CONFIG[]=01xxxx00bforalltestconditions(6-μsconversiontimeTESTInputvoltageVCn–VCn–1,wheren=1to06VVoltage14VN=VCnto–10°C≤TA≤50°C,1.2V<VN<4.55–40°C≤TA≤85°C,1.2V<VN<4.58REffective2CInputcapacitance1VIN=30VmaynotliewithintherangeofmeasuredvaluesduetooffsetvoltagelimitanddeviceSeetextforspecificconversionADCisfactorytrimmedattheconversionspeedof~6μs/channel(FUNC_CONFIG[ADCT1:0]=01b).Useofadifferentconversion-speedsettingmayaffectmeasurementaccuracy.VBAT(VBRICK)TypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40?Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted),FUNCTION_CONFIG[]=01xxxx00bforalltestconditionsTESTInputvoltagerange(1),BATntoVSSFUNCTION_CONFIG[]=0VVoltage14VoltageTotalCInput1REffective0VmaynotliewithintherangeofmeasuredvaluesduetooffsetvoltagelimitanddeviceSeetextforspecificconversionGPAITypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40?Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted),FUNCTION_CONFIG[]=0101xx00bforalltestconditionsTESTInputvoltagerange,(1)GPAI+toGPAI–0VVoltage14Voltageaccuracy,VIN=GPAI+–GPAI–0.25V≤VIN≤2.57VIN=1.25V,TA=CInputREffective0VmaynotliewithintherangeofmeasuredvaluesduetooffsetvoltagelimitanddeviceSeetextforspecificconversionTSnTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40?Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted),FUNCTION_CONFIG[]=01xxxx00bforallTestConditionsTESTInputvoltagerange,(1)TSn+0V0VmaynotliewithintherangeofmeasuredvaluesduetooffsetvoltagelimitanddeviceTSnMeasurement(TypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40?Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted),FUNCTION_CONFIG[]=01xxxx00bforallTestConditionsTESTVoltage14bits,REG50=5(Resolution≈Ratioaccuracy,%of0.25V≤VIN≤2.4CInputREffectiveinputSeetextforspecificconversionTHERMALTESTShutdownVBAT=20Recovery8UNDERVOLTAGELOCKOUT(UVLO)andPOWER-ONRESETTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40?Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TEST5VDelaytolocked-outV≤VUVLO45VDelaytodisabledV≤VPORResetdelayV≥VPOR+VoltagedeltabetweentripVUVLO–VPOR(VBATVVoltagedeltabetweentripVUVLO–VPOR(VBATVBATTERYPROTECTIONTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40?Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TESTOVdetectionthreshold25VOVdetectionthresholdprogramOVdetectionOVdetectionthreshold3.3≤VOV_SET≤0OVdetectionthresholdVOV_SET<3.3orVOV_SET>0UVdetectionthresholdUVdetectionthresholdprogramUVdetectionUVdetectionthreshold0OTdetectionthresholdVREG50=512VOTdetectionthresholdprogramSeeVOTdetectionthresholdT=40°CtoVOTresetT=40°CtoCOVandCUVthresholdsmustbesetsuchthatCOV–CUV≥300 mendedcomponents.ConsultTable1intextforvoltagelevelsSeeTable1fortripBATTERYPROTECTIONDELAYTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40?Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TESTOVdetectiondelay-time0OVdetectiondelay-timeCOVT[μs/ms]=COVT[μs/ms]=UVdetectiondelay-time0UVdetectiondelay-timeCUVT[7](μs/ms)=CUVT[7](μs/ms)=OTdetectiondelay-time0OTdetectiondelay-imeOV,UV,andOTdetectiondelay-timeCUVT,(COVT)≥500ProtectioncomparatordetectionVOTorVOVorVUVthresholdexceededby10mVUnderdoubleormultiplefaultconditions(ofasingletype),thesecondorgreaterfaultmayhaveitsdelaytimeshortenedbyuptothesteptimeforthefault.I.e.,thesecondandsubsequentCOVfaultsoccurringwithinthedelaytimeperiodforthefirstfaultmayhavetheirdelaytimeshortenedbyupto100μs.OTPEPROMPROGRAMMINGTypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40?Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TESTProgrammingVBAT≥207VProgrammingProgrammingACTIMINGSPIDATATypicalvaluesstatedwhereTA=25°CandVBAT=20V,Min/MaxvaluesstatedwhereTA=–40?Cto85°CandVBAT=7.2Vto27V(unlessotherwisenoted)TESTSCLKSCLK_Hdutycycle,t(HIGH)/t(SCLK)ort(LOW)/CS_Hleadtime,CS_HlowtoCS_Hlagtime.LastclocktoCS_HCS_HhightoCS_Hlow(inter-packetdelay3CS_Haccesstime(2):CS_HlowtoSDO_HdataCS_Hdisabletime(2):CS_HhightoSDO_HhighSDI_Hinput-datasetupSDI_Hinput-dataholdtVALSDO_Houtput-datavalidtimeSCLK_HedgetoSDO_HvalidCL≤20(1)umSCLKfrequencyislimitedbythenumberofbq76PL536Adevicesintheverticalstack.The umlistedheremaynotberealizableinsystemsduetodelaysandlimitsimposedbyothercomponentsincludingwiring,connectors,PCBmaterialandrouting,etc.Seetextfordetails.Timelistedisforsingle tt(SCLKtCSFigure3.SPIHostInterfaceVerticalCommunicationsTypicalvaluesstatedwhereTA=25oCandVBAT=20V(unlessotherwiseTEST HOST= HOST= Propagationdelay,CS_HtoHOST= Propagationdelay,CS_StoHOST= Propagationdelay,SDI_HtoHOST= Propagationdelay,SDI_StoHOST= HOST= HOST= Propagationdelay,SDO_NHOST= Propagationdelay,SDO_NHOST= HOST= HOST= HOST= HOST= HOST= HOST=TypicalvaluesarequotedinceofMIN/MAXfordesignguidanceonly.Actualpropagationdelaydependsheavilyonwiringandcapacitanceinthesignalpath.TheseparametersarenottestedinproductionduetothesedependenciesonsystemdesignOG-TO-DIGITALCONVERSIONGeneralTheintegrated14-bit(unsigned)high-speedsuccessiveapproximationregister(SAR)og-to-digitalconverterusesanintegratedband-gapreferencevoltage(VREF)forthecellandbrickmeasurements.TheADChasafront-endmultiplexerfornineinputs–sixcells,twotemperaturesensors,andonegeneral-purposeoginput(GPAI).TheGPAIinputcanfurtherbemultiplexedtomeasurethebrickvoltagebetweentheBATxpinandVC0orthevoltagebetweentheGPAI+andGPAI–pins.TheADCandreferencearefactorytrimmedtocompensateforgain,offset,andtemperature-inducederrorsforallinputs.Themeasurementresultisnotallowedtorolloverduetooffseterroratthetopandbottomoftherange,i.e.,areadingnearzerodoesnotunderflowto0x03ffduetooffseterror,andvice-versa.Theconverterreturns14validunsignedmagnitudebitsinthefollowing<00xxxxxxEachwordisreturnedinbig-endianformatinaregisterpairconsistingoftwoadjacent8-bitregisters.TheMSBofthewordislocatedinthelower-addressregisterofthepair,i.e.,dataforcell1isreturnedinregisters0x03and0x04as00xxxxxxxxxxxxxxb.3to6SeriesCellWhenfewerthan6cellsareused,themost-positivecellvoltageoftheseriesstringshouldbeconnectedtotheBAT1/BAT2pins,throughtheRCinputnetworkshownintheReferenceSchematicsection.UnusedVCxinputsshouldbeconnectedtothenextVCxinputdownuntilaninputconnectedtoacellisreached–i.e.,inafourcellstack,VC6connectstoVC5,whichconnectstoVC4.Theinternalmultiplexercontrolcanbesettoscanonlytheinputswhichareconnectedtocells,therebyspeedingupconversionsslightly.ThemultiplexeriscontrolledbytheADC_CONTROL[CN2:0]bits.123456789123456789Figure4.Connecting<6Cells(4CellVoltageConvertingthereturnedcellmeasurementvaluetoadcvoltage(inmV)isdoneusingthefollowingformula(allvaluesareindecimal).mV=(REGMSB×256+REGLSB)×6250/Cell_1==3.35V(3350Afterconversion,REG_03==0x22;REG_04==0x4d0x22×0x100+0x4d=0x224d(8781.)8781×6250/16,383=3349.89mV≈3.35GPAIorVBATThebq76PL536AfeaturesadifferentialinputtotheADCfromtwoexternalpins,GPAI+andGPAI–.TheADCGPAIresultregistercanbeconfigured(viatheFUNCTION_CONFIG[GPAI_SRC]toprovideameasurementofthevoltageonthesetwopins,orofthebrickvoltagepresentbetweentheBATxpinsandVC0.Inthebq76PL536Adevice,theVBATmeasurementistakenfromtheBATxpintotheVC0pin,andisaseparateinputtotheADCmux.BecausethisisaseparateinputtotheADC,certaincommonsystemfaults,suchasabrokencellwire,canbeeasilydetectedusingthebq76PL536Aandsimplefirmwaretechniques.TheGPAImeasurementcanbeconfiguredtouseoneoftworeferencesviaFUNCTION_CONFIG[GPAI_REF].Eithertheinternalbandgap(VREF)orREG50canbeselected.WhenREG50isselected,theADCreturnsaratioofthevoltageattheinputsandREG50,removingtheneedforcompensationoftheREG50voltageaccuracyordriftwhenusedasasourcetoexcitethesensor.WhenthedeviceisconfiguredtomeasureVBAT(FUNCTION_CONFIG[GPAI_SRC]=1),thedeviceselectsVREFautomaticallyandignorestheFUNCTION_CONFIG[GPAI_REF]setting.ConvertingGPAIResulttoToconvertthereturnedGPAImeasurementvaluetoavoltageusingtheinternalband-gapreference(FUNCTION_CONFIG[GPAI_REF]=1),thefollowingformulaisused.mV=(REGMSB×256+REGLSB)×2500/16,383FUNCTION_CONFIG[]=0100xxxxbThevoltageconnectedtotheGPAIinputs==1.25V;Afterconversion,REG_01==0x20;REG_02==0x000x20×0x100+0x00=0x2000(8192.)8192×2500/16,383=1250ConvertingVBATResulttoToconvertthereturnedVBATmeasurementvaluetoavoltage,thefollowingformulaisV=(REGMSB×256+REGLSB)×33.333/214(33.333≈6.25/FUNCTION_CONFIG[]=0101ThesumoftheseriescellsconnectedtoVC6–VC0==20.295V;Afterconversion,REG_01==0x26;REG_02==0xf70x26×0x100+0xf7=0x26f79975×33.333/16,383=20.295TemperatureThebq76PL536AcanmeasurethevoltageTS1+,TS1–andTS2+,TS2–differentialinputsusingtheADC.Theseinputsaretypicallydrivenbyanexternalthermistor/resistordividernetwork.TheTSninputsusetheREG50outputdivideddownandinternallyconnectedastheADCreferenceduringconversions.ThisproducesaratiometricresultandeliminatestheneedforcompensationorcorrectionoftheREG50voltagedriftwhenusedtodrivethetemperaturesensors.TheREG50referenceallowsanapproximate2.5-Vfull-scaleinputattheTSninputs.Thefinalreadingislimitedbetween0and16,383,correspondingtoanexternalratioof0to0.5.TwocontrolbitsarerequiredfortheADCtoconverttheTSninputvoltagessuccessfully.ADC_CONTROL[TSn]issettocausetheADCtoconverttheTSnchannelonthenextrequestedconversioncycle.IO_CONTROL[TSn]issettocausetheFETswitchconnectingtheTSn–inputtoVSStoclose,completingthecircuitofthevoltagedivider.TheIO_CONTROL[]bitsshouldonlybesetasneededtoconservepower;athightemperatures,thermistorexcitationcurrentmayberelativelyhigh.ExternalTemperatureSensorSupport(TS1+,TS1–andTS2+,Thedeviceisintendedforusewithanominal10kΩat25oCNTCexternalthermistor(AT103equivalent)suchasthePanasonicERT-J1VG103FA,a1%device.Asuitableexternalresistor-capacitornetworkshouldbeconnectedtopositiontheresponseofthethermistorwithintherangeofinterest.ThisistypicallyRT=1.47kΩandRB1.82kΩ(1%)asshowninFigure5.Aparallelbypasscapacitorintherange1nFto47nFcedacrossthethermistorshouldbeaddedtoreducenoisecoupledintothemeasurementsystem.TheresponsetimedelaycreatedbythisnetworkshouldbeconsideredwhenenablingtherespectiveTSinputpriortoconversionandsettingtheOTdelaytimer.SeeFigure5fordetails.47

RB=0.4(RTH@40C–RTH@90C)RT=RTH@40C–2RTH@90C–Figure5.ThermistorConvertingTSnResulttoVoltageToconvertthereturnedTSnmeasurementvaluetoaratio,RTS=VTS:REG50,thefollowingformulasareThevoltageconnectedtotheTS1inputs(TS1+–TS1–)==0.661V;VREG50≈5VnominalAfterconversion,REGMSB==0x11;REGLSB==0x16ACTUAL_COUNT=0x11×0x100+0x16=0x1116(4374+2)/33,046=0.1324(ratioofTSninputsto0.1324×REG50=0.662ADCBand-GapVoltageTheADCandprotectionsubsystemsuseseparateandindependentinternalvoltagereferences.TheADCbandgap(VREF)isnominally2.5V.Thereferenceis pensatedandstable.TheinternalreferenceisbroughtouttotheVREFpinforbypassing.Ahighquality10-μFcapacitorshouldbeconnectedbetweentheVREFandAGNDpins,inveryclosephysicalproximitytothedevicepins,usingshorttracklengthstominimizetheeffectsoftrackinductanceonsignalquality.TheAGNDpinshouldbeconnectedtoVSS.DeviceVSSconnectionsshouldbebroughttoasinglepointclosetotheICtominimizelayout-inducederrors.Thedevicetabshouldalsobeconnectedtothispoint,andisaconvenientcommonVSSlocation.TheinternalVREFshouldnotbeusedexternallytothedevicebyusercircuits.ConversionConvertTwomethodsareavailabletostartaconversioncycle.TheCONV_Hpinmaybeasserted,orfirmwaremaysettheCONVERT_CTRL[CONV]bit.HardwareAsingleinterfacepin(CONV_H)isusedforconversion-startcontrolbythehost.AconversioncycleisstartedbyahardwaresignalwhenCONV_Histransitionedlow-to-highbythehost.Thehostshouldholdthisstateuntiltheconversioncycleiscompletetoavoiderroneousedgescausingaconversionstartwhenthepresentconversionisnotcomplete.ThesignalissimultaneouslysenttothehigherdeviceinthestackbytheassertionoftheCONV_Nsignal.Thebq76PL536AautomaticallysequencesthroughtheseriesofmeasurementsenabledviatheADC_CONTROL[]registerafteraconvert-startsignalisreceivedfromeithertheregisterbitorthehardwarepin.IftheCONV_Hpinisusedinthedesign,itmustbemaintainedinadefaultlowstate(~0V)toallowuseoftheADC_CONVERT[CONV]bittotriggerADCconversions.IftheCONVpiniskepthigh,theADC_CONVERT[CONV]bitdoesnotfunction,anddevicecurrentconsumptionisincreasedbythesignalingcurrent,~900μA.IftheCONV_Hpinisnotusedbytheuser’sdesign,thepinmaybeleftfloating;theinternalcurrentsinktoVSSmaintainsproperFirmwareTheCONVERT_CTRL[CONV]bitisalsousedtoinitiateaconversionbywritinga1tothebit.Itisautomaticallyresetattheendofaconversioncycle.Thebitmayonlybewrittento1;theICalwaysresetsitto0.TheBROADCASTformofpacketis mendedtostartalldeviceconversionssimultaneously.DesignerNote:TheexternalCONV_H(CONV_S)pinmustbeheldinthede-asserted(=0)statetoallowtheCONVregisterbittoinitiateconversions.Aninternalpulldownisprovidedonthepintomaintainthisstate.DataThebq76PL536AsignalsthatdataisreadywhenthelastconversiondatahasbeenstoredtotheassociateddataresultregisterbyassertingtheDRDY_Spin(DRDY_HifHOST=0)iftheDRDY_Npinisalsoasserted.DRDY_S(DRDY_H)signalsareclearedonthenextconversionstart.

IItoVVtoISRFigure6.Data-ReadyADCChannelTheADC_CONTROLregistercanbeconfiguredasCELL_SEL=VCELL1,CELL_SEL=VCELL1,VCELL2,CELL_SEL=VCELL1,VCELL2,VCELL3,CELL_SEL=VCELL1,VCELL2,VCELL3,VCELL4,CELL_SEL=VCELL1,VCELL2,VCELL3,VCELL4,VCELL5,CELL_SEL=ExternalthermistorinputTS1=ExternalthermistorinputTS2=General-purposeogGPAI=ConversionTimeTheADCconversiontimeisfixedatapproximay6μsperconvertedchannel,plus6μsoverheadatthestartoftheconversion.Totalconversiontime(μs)isapproximay6×num_channels+6.AutomaticvsManualTheADC_CONTROL[ADC_ON]bitcontrolspoweringuptheADCsectionandthemainbandgapreference.Ifthebitissetto1,theinternalcircuitsarepoweredon,andcurrentconsumptionbythepartincreases.Conversionsbeginimmediayoncommand.ThehostCPUshouldwait>500μsbeforeinitiatingthefirstconversionaftersettingthisbit.IftheADC_ONbitisfalse,anadditional500μsisrequiredtostabilizethereferencebeforeconversionsIfthesamplinginterval(timebetweenconversions)usedislessthan~10ms,manualmodeshouldbeselectedtoavoidshiftingthevoltagereference,leadingtoinaccuracyinthemeasurements.ADCApplicationAnti-AliasingAnanti-aliasingfilterisrequiredforeachVCninputVC6–VC2,consistingofa1-kΩ,1%seriesresistorand100-nFshouldbeused.A1%resistoris mended,becausetheresistorcreatesasmallerrorbyformingavoltagedividerwiththeinputimpedanceofthepart.Thepartisfactory-trimmedtocompensatefortheerrorintroducedbythefilter.SecondaryThebq76PL536Aintegratesdedicatedovervoltageandundervoltagefaultdetectionforeachcellandtwoovertemperaturefaultdetectioninputsforeachdevice.Theprotectioncircuitsuseaseparateband-gapreferencefromtheADCsystemandoperateindependently.TheprotectoralsousesseparateI/Opinsfromthemaincommunicationsbus,andthereforeiscapableofsignalingfaultsinhardwarewithoutinterventionfromthehostProtectorWhenafaultstateisdetected,therespectivefaultflagintheFAULT_STATUS[]orALERT_STATUS[]registersisset.AllflagsintheFAULTandALERTregistersarethenORedintotheDEVICE_STATUS[]FAULTandALERTbits.TheFAULTandALERTbitsinDEVICE_STATUS[]inturncausethehardwareFAULT_SorALERT_Spintobeset.ThebitsinDEVICE_STATUS[]andthehardwarepinsarelatcheduntilresetbythehostviaSPIcommand,ensuringthatthehostCPUdoesnotmissanevent.Aseparatetimerisprovidedforeachfaultsource(cellovervoltage,cellundervoltage,overtemperature)topreventfalsealarms.Eachtimerisprogrblefrom100μstomorethan3s.Thetimersmayalsobedisabled,whichcausesfaultconditionstobesensedimmediayandnotlatched.TheclearingoftheFAULTorALERTflag(andpin)occurswhentherespectiveflagiswrittentoa1,whichalsorestartstherespectivefaulttimer.ThisalsoclearstheFAULT_S(_H)orALERT_S(_H)pin.Iftheactualfaultremainspresent,theFAULT(ALERT)pinisagainassertedattheexpirationofthetimer.Thiscyclerepeatsuntilthecauseofth