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設計實驗與考核
1、設計一個帶計數(shù)使能、異步復位、帶進位輸出的增1六位二進制計數(shù)器,計數(shù)結果由共陰
極七段數(shù)碼管顯示。
答:libraryieee;
useieee.std_logic__1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
port(elk,clkl,en,clr:instd_logic;
ledout:outstd_logic_vector(6downto0);
scanout,scanoutl,co:outstd_logic);
endcounter;
architectureaofcounteris
signalent:std_logic_vector(7downto0);
signalled:std_logic_vector(6downto0);
signalscan:std__logic;
signalhex:std_logic_vector(3downto0);
begin
process(elk)
begin
if(elk*eventandelk='1')then
ifen=,rthen
ifclr=,rthen
cnt<=(others=>,O');
else
ifcnt=*00111111;*then
cnt?〃00000000〃;
co<=,]';
else
cnt<=cnt+,I);
co<=='O';
endif;
endif;
endif;
endif;
endprocess;
process(clkl)
begin
ifclkl'eventandclkl=,1'then
scan<=notscan;
endif;
Scanout=scan;
Scanoutl=notscan;
endprocess;
ledout<=notled;
hex<=cnt(7downto4)whenscan=,Telseent(3downto0);
withhexselect
1ed<=*111100rwhen"0001”,
"OlOOlOO'when'OOlO",
"OllOOOO'when'OOir,
*0011001*when*0100*.
"OOlOOlO'when'OlOr,
"OOOOOlO'when'OUO",
"llllOOO'when'Olir,
"0000000"when"1000",
"OOlOOOO'when'IOOr,
“0001000"when"1010”,
”0000011"when"1011",
“1000110"when"1100”,
"0100001"when"1101”,
”0000110"when"1110”,
"00011lO'when'llll",
”1000000"whenothers;
enda;
2、設計一個帶計數(shù)使能、同步復位、帶進位輸出的增1二十進制計數(shù)器,計數(shù)結果由共陰極
七段數(shù)碼管顯示。
答:libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
port(elk,clkl,en,clr:instd_logic;
co,scanout:outstd_logic;
ledout:outstd_logic_vector(6downto0));
endcounter;
architecturertlofcounteris
signalent:std_logic_vector(7downto0);
signalled:std_logic_vector(6downto0);
signalscan:std_logic;
signalhex:std_logic_vector(3downto0);
begin
process(elk,clr)
begin
ifclr=,rthen
cnt<=(others=>>O');
elsifelk'eventandclk=,1'then
ifen=,rthen
ifcnt="z00001001then
cnt<=/z00010000";
co<='O';
elsifcnt^OOOllOOrthen一注意此處,前面跳過了A到F的計數(shù),所以計數(shù)到11001
ent<="00000000";
co<=,r;
else
cnt<=cnt+,r;
co<=,0>;
endif;
endif;
endif;
endprocess;
process(clkl)
begin
ifclkVeventandclkl=,1'then
scan<=notscan;
endif;
endprocess;
ledout<=notled;
scanout<=scan;
hex<=cnt(7downto4)whenscan=,Telseent(3downto0);
withhexselect
led<="1111001"when"0001
"OlOOlOO'when"OOlO",
"OllOOOO'when"OOir,
"0011001zzwhen"0100",
”0010010〃when〃0101〃,
"0000010"when"0110",
"llllOOO'when"Olir,
〃0000000〃when“1000〃,
"OOlOOOO'when"lOOr,
"lOOOOOO"when'OOOO",
^lllllll^whenothers;
endrtl;
3、設計一個帶計數(shù)使能、異步復位、同步裝載的可逆七位二進制計數(shù)器,計數(shù)結果由共陰極
七段數(shù)碼管顯示。
答:libraryieee;
useieee.std_logic_U64.all;
useieee.std_logic_unsigned.all;
entitycounteris
port(elk,elks,clr,en,stdl,dir:instd_logic;
din:instd_logic_vector(6downto0);
ledout:outstd_logic_vector(6downto0);
scanout:outstd_logic);
endcounter;
architectureaofcounteris
signalent:std_logic_vector(6downto0);
signalhex:std_logic_vector(3downto0);
signalled:std_logic_vector(6downto0);
signalscan:std_logic;
begin
process(elk)
begin
if(elk*eventandclk=,T)then
ifclr=,rthen
cnt<=(others^*O');
elsifstdl=,O'then
cnt<=din;
elsifen=,1'then
ifdir=,I*then
cnt<=cnt+,r;
else
cnt<=cnt-'r;
endif;
endif;
endif;
endprocess;
process(elks)
begin
if(clks,eventandclks=,T)then
scan<=notscan;
endif;
endprocess;
scanout<=scan;
ledout<=notled;
hex<=,0?&cnt(6downto4)whenscan='1'elseent(3downto0);
withhexselect
led<="1111001—001”,
"OlOOlOO'when"OOlO",
"OllOOOO"when'OOir,
"OOllOOrwhen'OlOO",
"OOlOOlO'when"OlOl",
"OOOOOlO"when'OllO",
"llllOOO"when'Olir,
"OOOOOOO'when"IOOO",
"OOlOOOO"when'lOOr,
"OOOlOOO"when'lOlO",
"00000irwhen"10ir,
”1000110〃when〃1100〃,
"OlOOOOrwhen'llOr,
“0000110〃when〃l110”,
"OOOlllO"when'llir,
“1000000"whenothers;
enda;
4、設計一個帶計數(shù)使能、同步復位、異步裝載、可逆計數(shù)的通用計數(shù)器。計數(shù)結果由共陰極
七段數(shù)碼管顯示。
答:LIBRARYIEEE;
USEIEEE.STD_L0GIC_1164.ALL;
USEIEEE.STD_LOGIC^UNSIGNED.ALL;
ENTITYcounterIS
GENERIC(count_value:INTEGER:=9);
PORT(elk,clr,en,load,dir:INSTD_LOGIC;
data_in:ININTEGERRANGE0TOcount_value;
ledout:0UTSTD_L0GIC_VECT0R(6DOWNTO0));
ENDcounter;
ARCHITECTUREaOFcounterIS
SIGNALent:INTEGERRANGE0TOcount-value;
SIGNALled:STD_LOGIC_VECTOR(6DOWNTO0);
BEGIN
PROCESS(load,elk)
BEGIN
IFload=T'THEN
cnt<=data_in;
elsifclr=,TTHEN
cnt<=0;
ELSIF(elk'EVENTANDelk=T')THEN
IFen=fTHEN
IFdir=VTHEN
IFcnt=count_valueTHEN
cnt<=0;
ELSE
cnt<=cnt+l;
endif;
else
IFcnt=0THEN
cnt<=count_value;
else
cnt<=cnt-l;
endif;
endif;
endif;
endif;
ENDPROCESS;
ledout<=N0Tled;
WITHentSELECT
lecK^llllOOrWHEN1,
"0100100'WHEN2,
"OllOOOO'WHEN3,
"OOUOOrWHEN4,
"OOIOOIO'WHEN5,
"OOOOOIO'WHEN6,
"llllOOO'WHEN7,
"OOOOOOO'WHEN8,
"OOIOOOO'WHEN9,
"lOOOOOO'WHEN0,
"UlllirWHENothers;
ENDa;
5、設計一個具有16分頻、8分頻、4分頻和2分頻功能的多用分頻器。
答:LIBRARYIEEE;
USEIEEE.STD_L0GIC__1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdiv4IS
PORT(elk:INSTD_LOGIC;
din:INSTD_L0GIC_VECT0R(3DOWNTO0);
fout:OUTstd_LOGIC);
ENDdiv4;
ARCHITECTUREaOFdiv4IS
begin
process(elk)
variableent:std_logic_vector(3downto0);
begin
if(elk*eventandclk=,T)then
ifent="1111"then
ent:="0000”;
else
ent:=cnt+,r;
endif;
ifdin=”0000〃then
fout<=cnt(3);
elsifdin="1000"then
fout<=cnt(2);
elsifdin="1100"then
fout<=cnt(1);
elsifdin="1110"then
fout<=cnt(0);
else
fout<=,r;
endif;
endif;
endprocess;
enda;
6、設計一個正負脈寬相等的通用分頻器。
答:LIBRARYIEEE;
USEIEEE.STD_L0GIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdivIS
GENERIC(num:INTEGER:=2);
PORT
(elk:INSTD_LOGIC;
co:OUTSTD_LOGIC);
ENDdiv;
ARCHITECTURErtlOFdivIS
BEGIN
PROCESS(elk)
VARIABLEent:STD_LOGIC_VECTOR(numdownto0);
BEGIN
IF(elk*eventandclk=,T)THEN
cnt:=cnt+,r;
ENDIF;
co<=cnt(num);
ENDPROCESS;
ENDrtl;
7、根據(jù)需要設計一個多用分頻器:可以控制實現(xiàn)四種分頻形式:
第一種:5分頻
第二種:8分頻
第三種:15分頻
第四種:16分頻
答:libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port(elk:instd_logic;
en:instd_logic_vector(1downto0);
cout:outstd_logic;
ledout:outstd_logic_vector(6downto0));
endfenpin;
architecturedgnfenpinoffenpinis
signalled:std_logic_vector(6downto0);
signalhex:std_logic_vector(3downto0);
begin
process(elk)
variableent:std_logic_vector(3downto0)二“0000”;
begin
if(elk'eventANDclk=,T)then
if(en="00")then
if(cnt>=*0101/r)then
ent:="0000”;
else
ent:=cnt+'r;
endif;
cout<=cnt(2);
elsif(en="01")then
if(cnt>=/r1000*)then
ent:="0000";
cout<=,r;
else
ent:=cnt+'1';
cout<=,O';
endif;
elsif(en=〃10")then
if(ent〉="1110")then
ent:=^0000^;cout<=,I>;
else
ent:二cnt+'r;cout<=,O';
endif;
else
if(ent>=>1111*)then
ent:="0000”;
else
cnt:=cnt+,T;
endif;
cout<=cnt(3);
endif;
endif;
endprocess;
withenselect
led<=〃0000000"when"00",
"OOOlOOO'when'Or,
"0001110"when*10",
"1000000"when'ir,
*lllllll^whenothers;
ledout<=led;
enddgnfenpin;
8、設計一個M序列發(fā)生器,M序列為“11110101”
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityxulieis
port(elk:instd_logic;
fout:outstd_logic);
endxulie;
architecturefashengqiofxulieis
signalent:std_logic_vector(2downto0);
begin
process(elk)
begin
if(elk*eventANDclk=,T)then
if(ent="111")then
ent<="000";
else
cnt<=cnt+,r;
endif;
endif;
endprocess;
withentselect
fout<=,Twhen^OOO'",
'1'when"001",
'Twhen"010",
,I*when^Oll^,
'O'when"100",
Jrwhen^lOl^,
Uwhen“110”,
<rwhen,,lll,;
‘O'whenothers;
endfashengqi;
9、設計一個彩燈控制器,彩燈共有16個,每次順序點亮相鄰的四個彩燈,如此循環(huán)執(zhí)行,
循環(huán)的方向可以控制。
答:libraryieee;
useieee.stdlogic_1164.all;
entitycaidengis
port(rl,elk:instdlogic;
ledout:outstd_logic_vector(15downto0));
endcaideng;
architectureaofcaidengis
signalled:std_logic_vector(15downto0);
signalk:std_logic;
begin
process(elk)
begin
if(clk,eventandelk='1')then
if(k='O')then
led<=(O=>,l,,1=>4\2=>T,3=>T,others=>'O');
elsif(rl=,T)then
led<=led(14downto0)&led(15);
elsif(rl=,0,)then
led<=led(0)&led(15downto1);
endif;
endif;
ledout<=led;
endprocess;
enda;
10、設計一個具有左移、右移控制,同步并行裝載和串行裝載的8位串行移位寄存器
LIBRARYIEEE;
USEIEEE.STD_L0GIC_1164.ALL;
ENTITYshifterlIS
PORT(elk,clr,ser,dir,stld:INSTD_LOGIC;
din:INSTD_LOGIC_VECTOR(OTO7);
qh:OUTSTD_LOGIC);
ENDshifterl;
ARCHITECTURErtlOFshifterlIS
SIGNALreg:STD_LOGIC_VECTOR(0TO7);
begin
process(elk,clr)
begin
ifclr=,rthen
reg<=(others=〉'O');
elsifelk'eventandclk=,1'then
ifstld=,0*then
reg<=din;
else
if(dir='O')then
reg<=reg(lto7)&ser;qh<=reg(0);
else
reg<=ser®(0to6);qh<=reg(7);
endif;
endif;
endif;
endprocess;
endrtl;
11、設計一個9人表決電路,參加表決者為9人,同意為1,不同意為0,同意者過半則表
決通過,綠指示燈亮,表決不通過則紅指示燈亮。數(shù)碼管顯示贊成人數(shù)。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityselectoris
port(a:instd_logic_vector(8downto0);
clr:instd_logic;
red,gree:outstd_logic;
ledout:outstd_logic__vector(6downto0));
endselector;
architecturertlofselectoris
signalled:std_logic_vector(6downto0);
signalcount:std_logic_vector(3downto0);
begin
process(a)
variableent:std_logic_vector(3downto0);
begin
ent:=”0000”;
foriin0to8loop
ifa(i)=,Pthen
ent:=cnt+l;
endif;
endloop;
if(cnt>=,,010r,andcnt<="1001”)then
gree<=,l\
red<=,0,;
elsif(cnt>=n0000,,andcnt<="0100“)then
gree<=,0,;
red<=,r;
endif;
count<=cnt;
endprocess;
ledout<=notled;
withcountselect
led<="111100rwhen"000r,
〃0100100〃when〃0010〃,
"OllOOOO'when"OOll",
"OOllOOl'when"OlOO",
"OOlOOlO"when'OlOr,
"OOOOOlO'when"OllO",
u1111000,,when,,01ir,,
“0000000''wheiT1000”,
u0010000,,when,,100r\
^lOOOOOO^whenothers;
endrtl;
12、設計?個同步復位,異步并行裝載的8位串行左移移位寄存器
LIBRARYIEEE;
USEIEEE.STD_L0GIC_1164.ALL;
Entityexaml3is
Port(clk9clr9ser9stld:instdjogic;
Din:instd_logic_vector(0to7);
Qh:outstdjogic);
Endexam13;
Architecturertlofexaml3is
Signalreg:std_logic_vector(0to7);
Begin
Process(clk,stld)
Begin
Ifstld=,rthen
Reg<=din;
Elsifclk^ventandclk=,Fthen
Ifdr=Tthen
Regv=(others>='0');
Elsif(stld=5O?)then
Reg<=reg(lto7)&ser;
Endif;
Endif;
Endprocess;
Qh<=reg(0);
Endrtl;
13、有16個開關,編號為。到15,編號0的優(yōu)先級最高。當某一個撥碼開關為1時由共陰
極七段數(shù)碼管顯示其編號(可用16進制數(shù)顯示,亦可用十進制顯示)
答:LIBRARYIEEE;
USEIEEE.STD_L0GIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYbhxsIS
PORT(INPUT:INSTD_L0GIC_VECT0R(15D0WNT00);
LEDOUT:outSTD_L0GIC_VECT0R(6D0WNT00));
ENDbhxs;
ARCHITECTURERT1OFbhxsIS
SIGNALLED:STD_LOGIC_VECTOR(6D0WNT00);
BEGIN
process(INPUT)
begin
LEDOUT<=NOTLED;
IF(INPUT(0)=Dthen
LED<="1000000,z;
ELSIF(INPUT(l)=r)then
LED<=*UU00r;
ELSIF(INPUT(2)='l')then
LED<=A0100100";
ELSIF(INPUT(3)=T')then
LED<="0110000";
ELSIF(INPUT(4)='1')then
LED<="0011001*;
ELSIF(INPUT(5)=Dthen
LED<="0010010”;
ELSIF(INPUT(6)=Dthen
LED<=*0000010*;
ELSIF(INPUT(7)=Dthen
LED<=*1111000";
ELSIF(INPUT(8)='1')then
LED<=A0000000";
ELSIF(INPUT(9)='1')then
LED<="0010000";
ELSIF(INPUT(10)=Dthen
LED<=A0001000";
ELSIF(INPUT(11)=Dthen
LED<="00000ir;
ELSIF(INPUT(12)=Dthen
LED<="1000110";
ELSIF(INPUT(13)=Dthen
LED<="0100001”;
ELSIF(INPUT(14)=Dthen
LED<="0000110";
ELSIF(INPUT(15)=l')then
LED<=*0001110*;
ENDIF;
ENDPROCESS;
ENDRT1;
14、設計一個全自動洗衣機水位控制器。
要求:當水位超過某一上限值時,停止加水,啟動洗衣機;當水位低于某一下限值時,加
水,停止洗衣機;否則啟動洗衣機,停止加水。
LIBRARYIEEE;
USEIEEE.STD_L0GIC_1164.ALL;
Entitywasheris
Port(elk,water_high,water_low:instd_logic;
Jiashui,qidong:outstd_logic);
Endwasher;
Architecturestyleofwasheris
Typestateis(just_right,too_high,too_low);
Signalnow_state,next_state:state;
Begin
Process(now_state,water_high,water_low)
Begin
Casenow_stateis
Whenjust_right=>jiashui<=,0,;qidong<=,r;
Ifwater_low=919thennext_state<=too_low;
Elsifwater_high=,19thennext_state<=too_high;
Elsenext_state<=just_right;
Endif;
Whentoo_low=>jiashui<=,15;qidong<=,0,;
Ifwater_low=,l,thennext_state<=too_low;
Elsifwater_high=9191hennext_state<=too_high;
Elsenext_state<=just__right;
Endif;
Whentoo_high=>jiashui<=,0,;qidong<=,r;
Ifwater_low=,19thennext_state<=too_low;
Elsifwater_high=,rthennext_state<=too_high;
Elsenext_state<=just_right;
Endif;
Endcase,
Endprocess;
Process(elk)
Begin
If(clkJeventandclk=,l,)then
Now_state<=next_state;
Endif;
Endprocess;
Endstyle;
15、根據(jù)真值表設計一位全加器,然后用結構的描述方法設計一個8位加法器
LIBRARYIEEE;
USEIEEE.STD_L0GIC_1164.ALL;
ENTITYfull_adderIS
PORT(a,b,cin:INSTD_LOGIC;
s,co:OUTSTD_LOGIC);
ENDfull_adder;
ARCHITECTUREfullloffulladderis
SIGNALcomb:STD_LOGIC_VECTOR(2downto0);
BEGIN
comb<=a&b&cin;
PROCESS(comb)
BEGIN
IF(comb="000")then
s<='O';co<=,0,;
elsif(comb="001")then
s<=,r;co<=,0J;
elsif(comb="100")then
s<=,r;co<=,0J;
elsif(comb="010")then
s<=,I>;co<=,0J;
elsif(comb="011")then
s<='o';co<=,r;
elsif(comb="101")then
s<='o';co<=,r;
elsif(comb="110")then
s<=,o>;co<=,r;
else
s<=,r;co<=,r;
endif;
endprocess;
endfulll;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityfull_adder8is
port(elk,cin:instd_logic;
x,y:instd_logic_vector(7downto0);
ledout:outstd_logic_vector(6downto0);
scan_out:outstd_logic_vector(1downtoo);
co:outstd_logic);
endfull_adder8;
architecturestruoffull_adder8is
componentfull_adder
port(a,b,cin:instd_logic;
s,co:outstd_logic);
endcomponent;
signalz:std_logic_vector(6downto0);
signalsum:std_logic_vector(7downto0);
signalscan:std_logic_vector(1downto0);
signalhex:std_logic_vector(3downto0);
signalled:std_logic_vector(6downto0);
begin
uo:full_adderportmap(x(0),y(0),cin,sum(0),z(0));
ul:full_adderportmap(x(l),y(l),z(0),sum(l),z(l));
u2:full_adderportmap(x(2),y(2),z(1),sum(2),z(2));
u3:full_adderportmap(x(3),y(3),z(2),sum(3),z(3));
u4:full_adderportmap(x(4),y(4),z(3),sum(4),z(4));
u5:full_adderportmap(x(5),y(5),z(4),sum(5),z(5));
u6:full_adderportmap(x(6),y(6),z(5),sum(6),z(6));
u7:full_adderportmap(x(7),y(7),z(6),sum(7),co);
scan_out<=scan;
ledout<=notled;
process(elk)
begin
if(clk'eventandclk=,r)then
ifscan二“10”then
scan<=,,01,\
elsescan<=”10”;
endif;
endif;
endprocess;
hex<=sum(7downto4)
whenscan="10"else
sum(3downto0);
withhexselect
led<=,,1000000Mwhen,,0000,\
u111100r,when,,0001,\
u0100100,,when,,0010,\
u0110000,,when,,00ir,,
u001100r,when,,0100,\
660010010,,when,,010r;
“0000010“when“0110”,
u1111000,,when,,01ir,,
u0000000,,when5,1000,\
6<0010000,,when,,1001,\
“0001000“when“1010”,
u00000H,,when,,10ir,,
“1000110“when“l(fā)100”,
u0100001,,when?,110F\
“0001110”when"l110",
u0001110,,when,,llll,\
uXXXXXXX9,whenothers;
Endstru;
16、設計6位二進制數(shù)到BCD碼(8421碼)的轉換器。結果由共陰極數(shù)碼管顯示。
LIBRARYIEEE;
USEIEEE.STD_L0GIC_1164.ALL;
useieee.std_logic_unsigned.all;
ENTITYtransIS
PORT(
scanclk:INSTD_L0GIC;
shu:INSTD_L0GIC_VECT0R(5D0WNT00);
ledout:0UTSTD_L0GIC_VECT0R(6DOWNTO0);
scanout:outintegerrange0to1);
ENDtrans;
ARCHITECTURErtlOFtransIS
signalyh,yl:integerrange0to9;
signalscan:integerrange0to1;
signalled:std_logic_vector(6downto0);
signaly,hex:integerrange0to63;
BEGIN
y<=conv_integer(shu);
yh<=lwheny>=10andy<20else
2wheny>=20andy<30else
3wheny>=30andy<40else
4wheny>=40andy<50else
5wheny>=50andy<60else
6wheny>=60andy<64else
0;
yl<=(y-0)wheny>=0andy<10else
(y-lO)wheny>=10andy<20else
(y-20)wheny>=20andy<30else
(y-30)wheny>=30andy<40else
(y-40)wheny>=40andy<50else
(y-50)wheny>=50andy<60else
(y-60)wheny>=60andy<70else
0;
process(scanclk)
begin
if(scanclk,eventandscanclk=’1')then
ifscan=lthen
scan<=0;
else
scan<=l;
endif;
endif;
endprocess;
withscanselect
hex<=yhwhen1,
ylwhenothers;
ledout<=notled;
scanout<=scan;
withhexselect
1ed<=*1111001^when1,
"0100100'when2,
”0110000”when3,
"OOllOOrwhen4,
"OOlOOlO'when5,
*0000010*when6,
"llllOOO'when7,
"OOOOOOO'when8,
"0010000"when9,
*1000000*when0,
^llllOOPVhenothers;
ENDrtl;
17、設計一個跑馬燈控制器。一共有8個彩燈,編號為LEDO?LED7,點亮方式為:先從左
往右順序點亮,然后從右往左,如此循環(huán)往復。
答:LIBRARYIEEE;
USEIEEE.STD_L0GIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYlightenIS
PORT(
CLK:INSTD_LOGIC;
ledout:OUTSTD_L0GIC_VECT0R(7DOWNTO0));
ENDlighten;
ARCHITECTUREbOFlightenIS
SIGNALent:STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK1EVENTANDCLK='1')THEN
IF(cnt^lllOOTHEN
crrt<="0000”;
ELSE
cnt<=cnt+,r;
ENDIF;
ENDIF;
ENDPROCESS;
WITHentSELECT
ledout<="10000000"WHEN"0000”,
"oioooooo'wHErooor,
"OOIOOOOO'WHEN'OOIO",
"OOO1OOOO"WHEN"OO11",
"OOOOIOOO'WHEN'OIOO",
"OOOOO1OO"WHEN"O1O1",
"OOOOOOIO'WHEN'OHO",
"OOOOOOO1"WHEN"O111",
"OOOOOO1O"WHEN"1OOO",
”00000100"WHENT001”,
"OOOO1OOO"WHEN"1O1O",
*00010000*WHEN*10ir,
"OOlOOOOO'WHEN'llOO",
*01000000wWHEN*110r,
"lOOOOOOO'WHEN"lllO",
"OOOOOOOO'WHENOTHERS;
ENDb;
10位的
LIBRARYIEEE;
USEIEEE.STD_L0GIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYlightenIS
PORT(
CLK:INSTD_LOGIC;
ledout:OUTSTD_L0GIC_VECT0R(9DOWNTO0));
ENDlighten;
ARCHITECTUREbOFlightenIS
SIGNALent:STD_LOGIC_VECTOR(4DOWNTO0);
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK)EVENTANDCLK='1')THEN
IF(cnt=*10010')THEN
ent<=*00000*;
ELSE
cnt〈=cnt+'r;
ENDIF;
ENDIF;
ENDPROCESS;
WITHentSELECT
ledout""lOOOOOOOOO^WHEN'OOOOO",
*OlOOOOOOOO'WHEN'OOOOr,
"OOIOOOOOOO'WHEN'OOOIO",
"OOOlOOOOOO'WHEN'OOOir,
"OOOOIOOOOO'WHEN'OOIOO",
"OOOOOIOOOO'WHEN'OOIOI",
*OOOOOO1OOO"WHEN"OO110",
"OOOOOOOlOO'WHEN'OOlir,
”0000000010“WHEN"01000”,
"ooooooooorwHEN'oioor,
"OOOOOOOOIO'WHEN'OIOIO*,
"OOOOOOOIOO'WHEN'OIOI1",
"OOOOOOIOOO'WHEN'OIIOO*,
"oooooioooo'wHEronor,
"OOOOIOOOOO'WHEN'OIUO*,
"OOOlOOOOOO'WHEN'Ollir,
”0010000000"WHEN"10000*,
"OlOOOOOOOO'WHEN'lOOOl",
"1000000000"WHEN*10010*,
"OOOOOOOOOO'WHENOTHERS;
ENDb;
18、有四路數(shù)據(jù)輸入,每路數(shù)據(jù)為4位二進制數(shù),根據(jù)不同的控制信號,輸出相應的輸入數(shù)
據(jù)。同時由共陰極七段數(shù)碼管顯示輸出數(shù)據(jù)的路號。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityexam27is
port(a:instd_logic_vector(3downto0);
b:outstd_logic_vector(6downto0));
endexam27;
architecturertlofexam27is
signale:std_logic_vector(6downto0);
signalc,d:integerrange0to9;
begin
c<=conv_integer(a);
d<=10-c;
withdselect
e<="lUlOOrwhen1,
*0100100*when2,
"OHOOOO'when3,
“0011001”when4,
”0010010”when5,
”0000010”when6,
"HllOOO'when7,
^OOOOOOO'when8,
“0010000”when9,
^lOOOOOO^whenothers;
b<=note;
endrtl;
19、設計五位BCD碼(8421碼)到十六進制數(shù)的轉換器。結果由共陰極數(shù)碼管顯示。
答:libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybcd2hexis
port(shu:instd_logic_vector(4downto0);
scanclk:instd_logic;
led_out:outstd_logic_vector(6downto0);
scan_out:outintegerrange0to1);
endbcd2hex;
architecturertlofbcd2hexis
signalyh,yl:integerrange0to15;
signalscan:integerrange0to1;
signalled:std_logic__vector(6downto0);
signaly,hex:integerrange0to31;
begin
y<=conv_integer(shu);
yh<=lwheny>=16andy<32else
0;
yl<=(y-0)wheny>=0andy<16else
(y-16)wheny>=16andy<32else
0;
process(scanclk)
begin
ifscanclk,eventandscanclk='Tthen
ifscan=lthen
scan<=0;
else
scan<=l;
endif;
endif;
endprocess;
withscanselect
hex<=yhwhen1,
ylwhenothers;
led_out<=led;
scan_out<=scan;
withhexselect
led<="0000110"when1,
“1011011”when2,
”1001111〃when3,
"1100110"when4,
"nonorwhen5,
”1111101〃when6,
“0000111〃when7,
“1111111〃when8,
"1101111"when9,
“1110111〃when10,
“0011111〃when11,
“1001110〃when12,
”0111110〃when13,
“1001111〃when14,
“1000111〃when15,
"1111110"when0,
“1111110"whenothers;
endrtl;
20、用結構的描述方法設計一個跑表,計時范圍為59.99秒,有計時開始和停止計時控制,
復位控制可以對所有計時進行異步復位。計時結果由四位共陰極七段數(shù)碼管顯示。
答:libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitytimeris
port(rst,en,elk,clkls:instd_logic;
scanout:outstd_logic_vector(1downto0);
ledout:outstd_logic_vector(6downto0));
endtimer;
architectureoneoftimeris
signalscan:std__logic_vector(1downto0);
signalent:std_logic_vector(10downto0);
signalhex:integerrange9to0;
signalled:std_logic_vector(6downto0);
signalml:std_logic_vector(3downto0);
signalmh:std_logic_vector(3downto0);
signalsi:std_logic_vector(3downto0);
signalsh:std_logic_vector(3downto0);
signalmil,mhl,sll,shl:integerrange0to9;
begin
process(en,rst,clkls)
begin
ifrst=,rthen
,,
sl<=(others=>);sh<=(others=>0*)二(others=>'O');mh〈二(others=>'O');
elsifclkls,eventandclkls=,Tthen
ifen=10,then
sl<=sl+'O';sh<=sh+'0';ml<=ml+,0,;mh<=mh+'0';
elsifslX”1001〃then
si<=si+,r;
else
sl<=(others=>,0*);
ifsh<,,100r,then
sh<=sh+*r;
elsesh<=(others=>,O');
ifthenml<=ml+,T;
elseml<=(others=>,O');
ifmh<"0101"thenmh<=ml+,T;
elsemh<=(others=>,O');
endif;
endif;
endif;
endif;
endif;
endprocess;
mhl<=conv_integer(mh);
mlK=conv_integer(ml);
shl<=conv__integer(sh);
siK=conv_integer(si);
process(elk)
begin
ifelk'eventandclk=,1'then
if(scan="11")then
scan爛"00";
else
scan<=scan+,1';
endif;
endif;
endprocess;
withscanselect
hex<=mhlwhen"00",
mHwhen"or,
shlwhen
sllwhen"11",
0whenothers;
ledout<=notled;
scanout<=scan;
withhexselect
1ed<="1111001”when1,-1
"0100100"when2,一2
"0110000"when3,-3
"001100rwhen4,—4
"0010010"when5,一5
,z0000010"when6,-6
"1111000"when7,-7
"OOOOOOO'when8,—8
"OOlOOOO'when9,—9
^lOOOOOO^whenothers;-0
endone;
21、設計彩燈信號控制器。共有十個彩燈,要求循環(huán)順序點亮這十個彩燈,每次只有一個彩
燈點亮,其他彩燈不亮。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitylightis
port(clk:instdjogic;
letout:outstd_logic_vector(9downto0));
endlight;
architectureaoflightis
signalcnt:std_logic_vector(3downto0);
begin
process(clk)
begin
if(clk*eventandclk=T)then
ifcnt=n1001Hthen
cnt<=n0000n
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