差分信號線的分析和LAYOUT

DifferentialSignalingIntroductionReadingChapter612/4/2023AgendaDifferentialSignalingDefinitionVoltageParametersCommonmodeparametersDifferentialmodeparametersCurrentmodelogic(CML)bufferRelatetoparametersModeling&simulationTimingparametersClockrecoveryEmbeddedclockACcouplingCommonmoderesponseIssueswithsimulation8B10BencodingDCbalancedcodesDutyCycledistortionCycle12/4/2023SingleEndedSignalingAllelectricalsignalcircuitsrequirealooporreturnpath.Singleendedsignalsubjectseveralmeansofdistortionsandnoise.Groundorreferencemaymoveduetoswitchingcurrents(SSOnoise).Wetouchedonthisinthegroundconundrumclass.Asingleendedreceiveronlycaresaboutavoltagethatisreferencedtoitsownground.Electromagneticinterferencecanimposevoltageonasingleendedsignal.Signalpassingfromoneboardtoanotheraresubjecttothelocalgrounddisturbance.Wecancounteractmanyoftheseeffectbyaddingmoreground.Asfrequenciesincreasebeyond1GHz,80%ofthesignalwillbelost.12/4/2023ReviewofthresholdsensitivityThewaveisreferencedtoeitherVccorVss.ConsequentlytheeffectiveDCvalueofthewavewillbetiedtooneoftheserails.ThewaveisattenuatedaroundtheeffectiveDCcomponentofthewaveform,butthereferencedoesnotchangeaccordingly.Hencetheclocktriggerpointbetweenvariousclockloadpointsisverysensitivetodistortionandattenuation.TxVssVrefVssRx2VrefLonglineVssRx1VrefShortline12/4/2023DifferentialSignalingAnysignalcanbeconsideredaloopiscompletedbytwowires.Oneofthe“wires”insingleendedsignalingisthe“groundplane”DifferentialsignalingusestwoconductorsThetransmittertranslatesthesingleinputsignalintoapairofoutputsthataredriven180°outofphase.Thereceiver,adifferentialamplifier,recoversthesignalasthedifferenceinthevoltagesonthetwolines.AdvantagesofdifferentialsignalingcanbesummedupasfollowsDifferentialSignalingisnotsensitivetoSSOnoise.Adifferentialreceiveristolerantofitsgroundmovingaround.Ifeach“wire”ofpairisoncloseproximityofoneandother.electromagneticinterferenceimposesthesamevoltageonbothsignals.Thedifferencecancelsouttheeffect.SincetheACcurrentsinthe“wires”areequalbutoppositeandproximal,radiatedEMIisreduced.Signalspassingfromoneboardtoanotherarenotsubjecttothelocalgrounddisturbances.Asfrequenciesincreasebeyond1GHz,upto80%ofthesignalmaybelost,butdifferencestillcrosses0volts.Therearestilllossissuesfordifferentialsignalingbutonlycomeintoplayinhighlosssystem.Mostsingleendedsystemsassumeapproximately15%channelloss.12/4/2023DifferentialSignaling-ConsThecostisdoublingthesignalwires,butthismaynotbesobadascomparedtoaddinggroundstoimprovesingleendedsignaling.Routingconstraint:Pairsignalsneedtoberoutedtogether.Differentialsignalhavecertainsymmetryrequirementsthatmayposeroutingchallenges.12/4/2023DifferentialSignalParametersVoltageonline1=aVoltageonline2=bDifferentialvoltaged=a-bCommonmodevoltagec=(a+b)/2Oddmodesignal,o=(a-b)/2Evenmodesignal,e=(a+b)/2Signalonline1a=e+oSignalonline2b=e-oUsefulrelations;o=b/2;e=cLine1Line2Reference12/4/2023PropagationTermstoConsiderDifferentialmodepropagationCommonmodepropagationSingleendedmode(uncoupled)propagationThisiswhentheotherlineisnotdrivenbutterminatedtoabsorbedreflections.Transmissionlinematrixeswillreflectthesemodes.12/4/2023DifferentialMicrostripExampleSE:singleended=uncoupled12/4/2023DifferentialImpedanceCouplingbetweenlinesinapairalwaysdecreasesdifferentialimpedanceDifferentialimpedanceisalwayslessthat2timestheuncoupledimpedanceDifferentialimpedanceofuncoupledlinesis2timestheuncoupledimpedance.12/4/2023PropagationVelocitiesForTEMstructures,(striplines)Differentialmode,CommonMode,andsingleendedvelocitiesarethesameForNonTEMandQuasi-TEMstructures(microstrip)Differentialmode,CommonMode,andsingleendedvelocitiesandimpedancesarenotthesame.Commonmodecanbeconvertedtodifferentialmodeatareceiverandresultinadifferentialsignaldisturbance.12/4/2023ExampleofCommonModeLine1andline2havethesameDCoffset.ThisisDCcommonmode.ItcanbedefinedasanaverageDCfortimedurationofmanyUIcyclesvalueaswell.Line1andline2havethesameACoffsetThisisACcommonmodeACcommonmodealsoresultfromtimedifferences(skew)betweensignalonline1andline2.ThiscanresultinACcommonmodeanddifferentialsignalloss.Thefollowingslidewillbeusedtoclarifytheabove12/4/2023DifferentialSignalingBasicsForlongchannels,atGHzfrequencies,signaltendlooklikesinewaves.Theartificialoffsetcommontoline1and2hasanaverageof1andvariesaroundthataverageby+/-0.1inaperiodmanor.12/4/2023IndividualsignalsDevicesneedtohaveenoughcommonmodedynamicvoltagerangetoreceiveortransmitthewaveforms.Inthiscasethesignalsswingbetween-0.1and2.1.Thesinewaveamplitudeis1andpeaktopeakis2.Signalaandbiswhatwouldbeobservedwith2oscilloscopeprobes12/4/2023DifferentialModeSignalThedifferentialamplitudeis2andpeaktopeakis4whichis2timestheindividualsignalpeaktopeakamplitude.Noticethedistortionsaregone.12/4/2023CommonModeSignalTheDCcommonmodesignalis1TheACcommonmodesignalis.2vpeaktopeakSomemayspecificationsmaycallthis0.1vpeakfromtheDCaverageWewilladdthiscommonmodetothesignals“a”and“b”12/4/2023Add150psskewtosignalbWaveformsdonotlooksogood.Weevenhavewhatappearstobenon-monotonicbehavior.12/4/2023DifferentialsignallooksOKHoweverwelostdifferentialsignalamplitude.Itusedtobe4peaktopeakandnowis3.562.12/4/2023CommonmodemeasurementsaredifferentAverageisstill1.Peaktopeakis0.944butpeakis0.504ACcommonmodesignalscanbeconvertedtodifferential12/4/2023PWBstructuresthatintroduceSkewAnescapefromaBGAorconnectorpins

introducesskewThisisanexampleofskewcompensation12/4/2023BendsintroduceskewBacktobackbends

compensateforskewfromfrequenciesbelow2GHz.Backtobackbends

compensateforskewfromfrequenciesbelow2GHz.12/4/2023MoreTerms:BalancedandUnbalancedGoodAgilentTechnologiesarticleonbalanceandunbalancedsignalingUnbalancedsignalinginreferencetogroundBalancedsignalingisreferencedonlytotheotherportterminal.Ifeachchannelisidentical,thenthissuggestsavirtualACgroundbetweenthetwoterminals.ItisoftenusefultoallowthisACgroundtobeaDCvoltagetobiasingdevices.12/4/2023Ethernet10/100BASE-Texample50W50W50W50WTransformerFilterCommon-modechokeUnbalancedBalanced12/4/2023LowVoltageDifferentialSignaling:LVDS200MHz–500MHzRangePublishedbyIEEEin1995LacksrobustnessforGHzSignalingWellsuitedistributingsystemclocksGoodnoisemarginCommonmodeimpedancehaswiderangeprovidebufferdesignflexibilityDifferentialimpedanceisoptimizearound100WDifferentialreceiverswitchingthresholdsaretighterthanforsingleendedlogic.MostdevicerequireexternalterminationandbiasresistorsDoesnothavecapacitanceorpackagespec.ThisseverelylimitsGHzoperation12/4/2023CurrentModeLogicEmergingtechnologyNorealspecyetbutcaninferoperationfromspec’slikePCIExpress?,Infiniband?,USB,SATA,etc.TxandRxlinesareseparateTheTxdriversteerscurrentbetweenthedifferentialterminalsACcouplingbetweenTxandRxwithaseriescapacitorprovidescommonmodedesignflexibilityTerminationisinbuffers.Thismayrequirecompensationorabandgapreferencetoinsureatightresistancerange.12/4/2023ExampleofSimpleCMLDifferentialBehavioralCircuitVccVssI_sourcer_termn,C_termr_termp,C_termPositiveTerminalNegativeTerminalThisexponentdetermineswaveshapeThisswitchtimeoffsetBalancebetweenforFETswitch2ndlecture12/4/2023ExampleofSensitivities:I,balance,CVccI_sourceMoreprominent

forfasteredges12/4/2023ExampleofSensitivities:Slew,Skew,RVccI_source+/skewR/Fslew12/4/2023SerialDifferentialGHztransmissionwillhavemanyUI’sofdataintransitontheinterconnectatanypointsintime.Henceitbecomesusefultothinkofthisasserialdatatransmission.Oftenmultiplesinglechannelsaregangedinparalleltoachieveevenhigherdatathroughput.12/4/2023ACcouplingissuesSeriescapacitorscanbuildupchargedifferencebetweendifferentialterminalsforthefollowingreasons.UnequalnumbersoffzeroandonesDutycycle(UI)distortion.Thesolutionistouseadatacodethatis“DC”balanced.8B10B(8bit10bit)withdisparityisonesuchcodeTightUIcontrolisabasicrequirementforkeepingthesignaleyeopen12/4/2023EyeDiagramTheeyediagramisaconvenientwaytorepresentwhatareceiverwillseeaswellasspecifyingcharacteristicsofatransmitter.TheeyediagrammapsallUIintervalsontopofoneandother.Theopeningineyediagramismeasureofsignalquality.Thisisthesimplesttypeofeyediagram.TheareotherformwhichwewilldiscusslaterEyeDiagram12/4/2023CreatingeyediagramPlotperiodicvoltagetimeramps(sawtoothwaves)onxversesthevoltagewaveonY.CanbedonewithAvanwavesexpressioncalculatorandcanbesavedinaconfigurationfile.12/4/2023CreaterampwithexpressionbuilderStartofrelativeeyepositionTimeofeyestartUnitInterval12/4/2023CopyRamptoXAxisUsemiddlebuttontodragramptoCurrentX-Axis12/4/2023Voltageandperiodvolt-timeramp12/4/2023ClockingTheonethingomittedinthesuggestsinthepreviousslidesoneyediagramswasthe“chop”frequency.WeassumeditwasUI.Thisissimpleforsimulation.Timemarchesalongandallsignalsstartoutsynchronizedintime.ThisisnottrueforrealmeasurementsinceedgeswillsignificantlyjitterandmakeitdifficulttodeterminatewheretheexactUIispositioned.Presently,therearebasicallytwoformsofGHz+clockingEmbeddedclockingForwardedclocking12/4/2023EmbeddedclockingThiswhatisusedinFiberChannel,GigabitEthernet,PCIExpress,Infiniband,SATA,USB,etc.TheclockisextractedfromthedataThereisrequirementthatdatatransitionsareataminimumrate.8B/10Bguaranteesthis.Wediscussthisinmoredetaillater.Aphaseinterpolatorisnormallyusedtoextracttheclockfromthedata.Wediscussedthephaseinterpolatorintheclockingclass.ThephaseinterpolatoristiedtothePCIExpress-likejitterspec:MedianandJitteroutlier.12/4/2023JitterMedianandOutlierSpecEyeopeningisdefinedfromastableUI.JittermedianusedtodetermineastableUIItisusedasareferencetodetermineeyeopeningJitterOutlierisusedtoguaranteelimitsofoperationJitterMedianJitteroutlierEyediagramUI12/4/2023ForwardedClockingTheTxclockissourcedandreceiveddownstream.TheclockisaTxdatabuffersynchronizedwiththeTxdatabits.Asynchronizationortrainingsequenceonadatalineisusedtoadjustthereceiverclocksothatitisinphasesynchronizationwiththedata.Thecaveatisthattheactualdataclocklagstherealdatabyafewcycles.ThewholeideaisthatthejitterintroducedoverthesecycleswouldbesmallerthanthejitterassociatedwithtwothePLLsusedtoprovidebaseclocksforanembeddedclockdesign.12/4/2023AspectsofACcouplingWewillexploreissueswithACcouplingwithasimulationexample.FirstwewillcreateasimpleCMLdifferentialmodelNextwewilltieittoadifferentialtransmissionlineandaterminator.Assignment7istoreproducetheseeffectswithaHSPICEprogram.TheoutputAvanwaveswithapowerpointstorysummarywhatyouwillhandin.Thebasisforourworkwillbelastsemesterstestckt.spdeck12/4/2023BehavioralDataModel–Example12bitofrepeatingdata

010101001001…v(t)dataUI=500ps

Tr=Tf=100psRterm=50Cterm=0.25pfVswing=800mVI=Vswing/(50||50)/2Waveshape**Refertofirstcourse3rdlecture12/4/2023ACcoupledDifferentialCircuitACcouplingcapsarenormallylarger,butarescaleddowntoillustratecommonmodeeffects12/4/2023TopLevelHSPICECODEModifiedConvenience12/4/2023NoinitialconditionsonDCblockingcaps300nsofsimulationtime!Cblknpkg2_nbpkg2_n1nf$ic=400mvCblkppkg2_pbpkg2_p1nf$ic=400mv101010101010repeating12bitpatternDifferentialSingleendedReproducethisatpackage2(receiver)12/4/2023SetICtoVswing/2DifferentialSingleendedReproducethisatpackage2(receiver)12/4/2023NotcompletelyfixedInitialvoltageforD+andD+isnot0sothereisastepresponsewhenthewavereachesthereceiver.Wecanfixthisbymultiplyingboth“n”and“p”controlwavesfortheVCR(voltagecontrolledresistor)by0forthefirstcycle.ThisforcestheDCsolutionattheotherendofthelineto0voltsdifferential.12/4/2023InsurebothlegsstartatsamevoltageQualifyingvoltageQualifyingvoltage

pcontrolvoltageQualifyingvoltage

ncontrolvoltage12/4/2023Results–PrettygoodDifferentialSingleendedReproducethisatpackage2(receiver)Mayhavetoignore

first1-2cycles12/4/2023NowletschangebitpatternThepatterncreatesaDCchargetobebuiltupinthecapThesolutionistocreateacodethathasequalamountof1’sandzeros.Thisistherationalfor8bit10bit(8b10b)codingDifferentialSingleendedReproducethisatpackage2(receiver)12/4/2023CrossingOffsetThecrossingoffsetisthehorizontallinethatisintheverticalcenteroftheeyeanditshouldbeat0voltsforadifferentialsignal.TheamountofoffsetistheaverageDCvalue.Asimpleapproximationisoneminustheratioofone’stozerostimesthereceivedvswing/2.Thisdoesnotincludededgeshapeeffects12/4/2023Repeatpatternsof5onesand6zerosApprox.offsetReproducethisatpackage2(receiver)Hint:starteyediagramat200ns12/4/20238b/10bencodingandbackgroundCourtesyof

ScottGardiner,Intel12/4/20238b/10b-SimpleSchemeTheencodingiscomprehendedinasetoftableswhichconformtoasetofpredetermined“rules”HelpfulHint:Completetablesthatgivealltheliteral10bencodingsdoexist-andtheycomprehendalloftheencodingrules…8bitsareencodedinto10bits12/4/20238b/10b:OverviewThe10bitsarereferredtoasa“symbol”ora“code-group:”Theoriginal8bitsarebrokenintoa3bitblockanda5bitblock(eachofthesearecalledsub-blocks)

F1

111

10001The3bitsub-block(labeledHGF)isencodedinto4newbits(labeledfghj)&the5bitsub-block(EDCBA)isencodedinto6newbits(abcdei)HGFEDCBA

notationcommonlyrepresentstheun-encodedbits,andabcdeifghjrepresentstheencodedbits;notethattherelativeorderandpositionofthesub-blocksisswitcheduponencodingHGF

EDCBA

abcdei

fghjHence,anextrabit,

j

,isaddedtothenewlyencoded3bitblockandanextrabit,

i

,totheencoded4bitblockcreatinga4and5bitsub-blocks12/4/20238b/10b–CharacterConventionsBothDataCharactersandSpecialControlCharactersexist;(nomenclature:D.a.b&K.a.b)D/K=SignifiesDataorControla=5bitblocktobeencodedb=3bitblocktobeencodedSetofAvailableDataandControlCharactersData(D.a.b)D0.0-D31.0,D0.1-D031.1,D0.7–D31.7All256Possible8-bitDatacharacters(00throughFFHEX)Control(K.a.b)K28.0–K28.7,K23.7,K27.7,K29.7,K30.712/4/20238b/10b-DCbalancing&DisparityNevermorethan5consecutive1’sor0’sallowedinarow(consecutively)..i.e.themaximum“runrate”is5tomaintainaDCbalancedtransmission.Thisguaranteesthelowestfrequencytobe1/10ofthemaxfrequency.i.e.only1decadedatabandwidthrequired.With8b/10b,eitherpositive(RD+)ornegative(RD-)disparityencodingispossible12/4/20238b/10b-DisparityDisparityis“thedifferencebetweenthenumberofonesandzeros...positiveandnegativedisparityrefertoanexcessofonesorzerosrespectively”.Note:neutraldisparityissaidtooccurwhenRD+andRD-encodingareidentical-meaningtheywilleachhavethesamenumberofonesandzeros(therearesomeexceptions)Agivensub-blockorsymbolcanhaveanactualdisparitynumberofeitherazero(neutral),+2or–2,thoughtheRunningDisparityissaidonlytobePositive,NegativeorNeutral.12/4/20238b/10b–RunningDisparityTheRunningorCurrentDisparity(abinaryvalueof+or-)istrackedbytheTX/RXandiscomputedateverysub-blockboundaryandateachsymbolboundary.Thevaluefromonesub-blockorsymbolisusedwiththatofthenextsub-blockorsymboltogivea“running”or“current”status.12/4/20238b/10b–RunningDisparityAlgorithmForagivenencodingofabyte,thestartingdisparityiswhatexistedattheendoftheprevioussymbolTherunningdisparityisthencalculatedfirstforthe6bitsub-block,comprehendingthestartingdisparityvalue;The6bitsubblockdisparityvalue

isthenusedasthestartingdisparitywhentherunningdisparitycalculatedforthe4bitsub-blockTherunningdisparityfortheentire10bitsymbolisnowthesameastherunningdisparityfoundattheendofthe4bitsub-block(andtherunningdisparityatthebeginningofthenextsymbol/

6bitsub-blockisthesameasthatfoundattheendofthethissymbol)Again,agivensub-blockorsymbolcanhaveanactualdisparitynumberofeitherazero(neutral),+2or–2,thoughtheRunningDisparityisonlysaidtobePositive,NegativeorNeutral.12/4/20238b/10b-RunningDisparityCalculationAlgorithm:Assumptions:The8bto10bencodinghasalreadybeendone;AcurrentdisparityvalueisalreadyassumedProcess:Calculatethedisparityfortheleftmost6bitsfirst,keepinginmindthecurrentdisparityvaluebeforeenteringthealgorithm.Thencalculatethedisparityfortherightmost4bitskeepinginmindthedisparityvaluedeterminedafteranalyzingtheprevious6bits.Thedisparityforboththe6-bitandthe4-bitblocksshouldbecalculatedasfollows:12/4/20238b/10b-RunningDisparityCalculationMethodMethod:If#of1’s>0’s Disparity=Positive(1)Elseif#of0’s>1’s Disparity=Negative(0)Elseif6-bit=000111 ThenDisparity=Positive(1)Elseif6-bit=111000 ThenDisparity=Negative(0)Elseif4-bit=0011 ThenDisparity=Positive(1)Elseif4-bit=1100 ThenDisparity=Negative(0)ElseDisparity=Disparity(ifnoneoftheabove,thenthedisparityvaluedoesn’tchange)

Note:Assumingaencoding,more1’sacrosstheentire10bcodeyieldspositivedisparity,more0’syieldsnegativedisparity,andeven#’sof1’sand0’syieldsneutraldisparity(i.e.disparityisthesameasitwasbefore).12/4/20238b/10b-Disparity&EncodingExample:Transmitterkeepsrunningtrackofcurrentdisparity(itiseitherRD,RD+orneutral)NeutralmeansthedisparitytrackerkeepsthepreviousRD-orRD+valueARunningDisparityofRD+isalwaysfollowedbyanRD-encodingandviceversaIfRunningDisparityisRD+,thefollowingisencodedforthedatabyteF1:

HGFEDCBAabcdeifghj111

10001

100011

0111

(RD-encoding)IfRunningDisparityisRD-,thefollowingisencodedforthedatabyteF1:

HGFEDCBAabcdeifghj11110001

1000110001

(RD+encoding)12/4/20238b/10b-Disparity&EncodingExample:Notethatthenumberofonesandzerosinthecurrentlychosenencodingworkstobalanceouttheoffsetinthenumberofonesandzeroes(trackedbytheRunningDisparityvalue)fromthepreviousencodingI.E.:Don’tconfusethedefinitionofPositiveDisparitywiththeRD+encodingchoice!PositiveDisparitymeansthereisacurrentrunningtotalofmoreones

thanzeros!Thus,anRD+encodinggenerallyhasmorezerosthan

ones!Alsonotethatitispossiblethatthe4-bitsub-blockofaRD-orRD+symbolencodingcanyieldanegativeorpositivedisparity,respectivelythusforcingmorethanoneRD-encodingtobeusedconsecutively…12/4/2023Summary:ExampleconversionHEXDataByte(8b)tobeEncodedORBinaryDataByte(8b)tobeEncoded10bEncodedsymbol(RD-)10bEncodedsymbol(RD+)F1100011011110001100011111000112/4/2023PossiblePatterns…RepeatingComma[K28.5]Pattern(RD-followedbyRD+):0