2023《數(shù)字邏輯設(shè)計》期末考試-試題及參考解答

2024《數(shù)字邏輯設(shè)計》期末考試-試題及參考解答………密………封………線………以………內(nèi)………答………題………無………效……

電子科技高校2024-2024學(xué)年第2學(xué)期期末考試A卷

課程名稱：數(shù)字規(guī)律設(shè)計及應(yīng)用考試形式：閉卷考試日期：2024年07月13日

考試時長：120分鐘

課程成果構(gòu)成：平常20/30%，期中20/30%，爭論20/0%，期末40%

本試卷試題由IV部分構(gòu)成，共4頁。

I.Pleasefillthecorrectanswersinthebrackets“()”.(4’X10=40’)

1.Foran8-bitDAC(DigitalAnalogConverter),whentheinputis010000002,itsoutputvoltageis1.25V;If

theinputis101000002,theoutputvoltagewillbe(3.125或等效算式)V.

2.AstatetransitionequationisQ*=JQ’+K’Q.IfweuseDflip-floptopletetheequation，theinputofD

flip-flopshouldbeD=(JQ’+K’Q).

3.ForacounterwithNflip-flops,ithasatmost(2n)states.IfthecounterisJohnsoncounter,it

has(2n)validstates.

4.Aftermodification,anN-bitLFSR(LinearFeedbackShiftRegister)has(2N或2N-1)states.

5.Dlatchisalsocalledtransparentlatch,ithastwoinputsignalDandC,oneoutputsignalQ.The

relationshipbetweentheoutputQandtheinputDis(Q*=DC+QC'或C=1時Q*=D,C=0時Q*=Q).

6.Tobuilda64Kx8ROM,weneed(16)4Kx8ROM.

7.Onlywhenbothtwo-bitinputsA(A1,A0)andB(B1,B0)areequal,theoutputAEQBis1,sothelogic

expressionofAEQBis((A1⊙B1)·(A2⊙B2)或其他等效表達(dá)).

8.State/outputtableforasequentialcircuitisshownastable1.XisinputandZisoutput.Assumethatthe

initialstateisS0,iftheinputsequenceisX=10110110,theoutputsequenceshouldbe(100011108位或9位均算正確).

9.Transition/outputtableforasequentialcircuitisshowninTable2,XisinputandYisoutput,thesequential

circuitisamodulus(4)up/downcounter.

………密………封………線………以………內(nèi)………答………題………無………效……

II.Choosethecorrectanswerandfilltheitemnumberinthebrackets.(3’X5=15)

1.WithNflip-flops,(A)hastheoutputsthatcanbeusedas1-out-of-Ncodesdirectly.A.Ringcounter

B.Johnsoncounter

C.LFSR(LinearFeedbackShiftRegister)

D.N-bitbinarycounter

2.IfstateS1andS2areequivalentstates,itmeans(D選A或B或C只得1分)forallinputbinations.

A.theiroutputsarethesame

B.theirnextstatesarethesame

C.theirnextstatesaretheequivalentstates

D.bothAandBandC

3.ForaDflip-flop,ifthefrequencyofclockis10MHz,thefrequencyofitsoutputsignalQmaybe(B或C)MHz.A.10

B.5

C.2.5

D.20

4.Whenusingshiftregisterstoperiodicallygeneratesequence“0100101”,itrequiresatleast(A)flip-flops.

A.6

B.3

C.4

D.5

5.AccordingtoFigure1,themodulusofthecounteris(B)A.5B.6C.7D.9

Figure1

n+121

2.Listouttransition/outputtable.

3.AssumetheinitialstateQ2Q1=00,pletethetimingdiagramforQ1,Q2andZ.

參考答案：

1.激勵方程:D1=X，D2=X⊕Q1

轉(zhuǎn)移方程：Q1*=D1=X，Q2*=D2=X⊕Q1輸出方程：Z=X⊕Q2

2.轉(zhuǎn)移/輸出表

3.波形圖

IV.DesignaMealymachineforasequencedetectorwithaserialinputsequenceof1011or

a74x194,anANDandaXORgate,thesequencemaybeoverlap.TheoutputZ=1,whenthesequenceof1011or1101isdetected,andZ=0otherwise.Pleaseselectshiftleftmodeforthe74x194.(19’)1.Listoutthestatesmeaningandminimalstate/outputtable.2.Wri