通信與電子設計實驗硬件連接關系

33脈沖觸發(fā)開關(4位64M0/1控制開關(8位4個Xilinx Xilinx視頻擴展分AlteraCPLDNorFLASH外擴單片擴展子U50：CPLD型號：XC95144XL-10TQ144：familyXC95144XLDeviceXC95144XLSpeed-10Package U46：FPGA型號：XC2V2000：familyVirtex2,deviceXC2V2000。Speed-4。Package U1：ARM型號：三星S3C2410,最高工作時鐘200MHzU30：ALTERACPLD型號：EPM7032TC44-10U42：ALTERACPLD型號：EPM7032TC44-10U33：ALTERACPLD型號：EPM7032TC44-10 CPLD1234567899567234輸出數(shù)碼管（動態(tài)掃描模式:共陰極a8個數(shù)碼管的共用正極控bcdefg8個數(shù)碼管的共陰極控制0/1控制開關（ON接到地，OFF接到KEY1KEY3無無KEY2KEY4無無 FPGA控制所有CPLD12345678938個DIP開關的通斷狀態(tài)通過FPGA_DipSwitch_en和FPGA_DipSwitch_n[3..0]輸入到FPGA，其中FPGA_DipSwitch_en為串行數(shù)據傳遞使能信號，當其為高電平(或上升沿)時，F(xiàn)PGA_DipSwitch_n[3..0]數(shù)據有效。000~111的狀態(tài)，0表示ON，1表示OFF。4，32LEDFPGAFPGA_LED_dFPGA_LED_bits[4..0]完成。00000~1，F(xiàn)PGA_LED_d（高電平）還是滅（低電平FPGA_Seg7_HEX[3..0]FPGA_Seg7_en_n用來指示數(shù)據傳遞，即當其為低電平時，F(xiàn)PGA_Seg7_bits[2..0]三、FPGAXC2V2000FPGAS11開關控制四個全局時鐘引腳的時鐘連（OFF/ONOFFON時提供48MHz的時鐘。FPGA式000主串（與模式引腳一起認IO111配置期間是否上011主接高電平時,110從IO101時，相應的控制為高電平;ON時相應的控制為低電平。U55 V2000TDOV8000V2000_TDIU55V2000V8000U47U55V2000沒焊時 123456789DS38a8個bcdefgAD/AD板接信名123456789地地地地地地地ADJADJ 方向ED[0-31]16245U42CPLDDC_EMIFA_OE# U35 UARTU41UARTU41 23568’TCE1=’0’TCE2=’0’TCE3=’0’時為’0’,TCE1=’0’DC_AOE=’0’且 DSPU40SST39VF040- NorU42U41 U42U42AJ109BU34,U35 A[0..11]LEDLEDLED PCIPCI無啟動模式（默認PCIPROM無效（默認PCIROMBITEMIF8NoNoNoCPU時鐘NoCPU時鐘0040015021106131184、DSPCLKIN11101201600十、DSPARMHD00~HD15DSP端HPI控制引腳的譯碼是通過U33EPM7032CPLD實現(xiàn)的，如上圖所示。U33將來自ARM的片選信號nGCS3,nGCS5ADDR[0..4]（Laddr[0..4]162245緩沖器）DSPHPI相應的控制信號?？刂七壿?VHDL代碼)如下：HCNTRL0<=ADDR1whennGCS3='0'else whennGCS3='1'; whennGCS3='1'; whennGCS3='0'else whennGCS3='1'; whennGCS3='0'else whennGCS3='1'; <=(nWEandnOE)whennGCS3='0'else whennGCS3='1';HDS2 十一、ARMLCD顯示模塊用的是SHARPLQ035Q7DH01TFT觸摸屏模塊，其引腳定義見下表，其它內容請參考Cpld-Cpld-Cpld-Cpld-Cpld-Cpld-Cpld-Cpld-5、USB6、8、ARMLIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all; Vcom Samplingstart framesynLCD_LP linesyn ClocksignalofGate DataENDARCHITECTUREBehaviorOFLCD_CONSIGNAL SIGNALcounter_for_mod SIGNALcounter_for_point:std_logic_vector(8downto0); SIGNALs_lcd_cls SIGNALcounter_for_line: SIGNALline_den Interal_dclk<=notLCD_DCLK <=not CASEcounter_for_modWHEN =>WHENOTHERS=>counter_for_mod<=counter_for_mod+"001";ENDEND (VLINE='1')elsif(Interal_dclk'EVENTANDInteral_dclk='0')thenend (counter_for_point="000000110"andline_den='1')then

end

if(Interal_dclk'eventandInteral_dclk='1')thenif(counter_for_point="011111111")thens_lcd_rev<=notendif;endendif(VFRAM='1')thenelsif(s_lcd_cls'eventands_lcd_cls='0')endif;if(counter_for_line>="000000110"andcounter_for_line<="101000101")thenendif;endprocess;if(line_den='1')thenendif; <=nGCS0ANDnGCS1ANDnGCS2ANDnGCS3ANDnGCS4ANDnGCS5ANDnFWEANDtem_buffe