八位模型機(jī)課程設(shè)計(jì)報(bào)告

9．VHDL實(shí) 參考文 計(jì)算機(jī)組成原理課程設(shè)計(jì)的主要任務(wù)是讓學(xué)生通過動腦和動手解決計(jì)算機(jī)設(shè)計(jì)中編寫程序，在所設(shè)計(jì)的模型計(jì)算機(jī)上調(diào)試運(yùn)行。quartusII5.1、VHDL0=>1=>2=>3=>4=>5=>6=>7=>8=>9=>10=>11=>12=>13=>14=>9VHDLLIBRARYIEEE;USEUSEWORK.CPU_DEFS.ALL;ENTITYCPUPORT(::data_r_out:BUFFERSTD_LOGIC_VECTOR(19DOWNTO0);出 STD_LOGIC; STD_LOGIC_VECTOR(op_w-1DOWNTOadd_r_outUNSIGNED(4DOWNTO0);:::::acc_bus:OUT pc_bus:OUT mdr_bus:OUT alu_acc:OUT inc_pc:OUT cs:OUT r_nw:OUTalu_add:OUTSTD_LOGIC;alu_sub:OUTSTD_LOGIC;addr_bus:OUTENDARCHITECTURErtlOFCPUTYPEmicrocode_arrayISARRAY(0TO14)OFSTD_LOGIC_VECTOR(19CONSTANTcode :microcode_array:=( 0=>"00010100000000000001",1=>2=>3=>4=>5=>6=>7=>8=>9=>10=>11=>12=>13=>14=>VARIABLEmicrocode:microcode_array;VARIABLEadd_r :UNSIGNED(4DOWNTO0);VARIABLEdata_r :STD_LOGIC_VECTOR(19DOWNTO0);VARIABLEtemp :STD_LOGIC_VECTOR(4DOWNTO0);IFreset='0'add_r:=(OTHERS=>'0'); ELSIFRISING_EDGE(clock)THEN--microprogramdata_rcode(TO_INTEGER(add_r));IFdata_r(4DOWNTO0)="01111"THEN，OPtemp:="01"&op(2DOWNTO0);--01+對應(yīng)的機(jī)器指令add_r:=UNSIGNED(temp);ELSIFdata_r(4DOWNTO0)="10000"IFz_flag='1'THENENDIF; :=UNSIGNED(data_r(4DOWNTO0));ENDIF;--以上為下地址形成電路（控制器的核心部分ENDdata_r_out<=data_r;add_r_out<=add_r;load_pc<=data_r(19)and(notclock);load_acc<=data_r(17)and(notclock);load_ir<=data_r(15)and(notclock);load_mar<=data_r(14)and(notclock);load_mdr<=data_r(12)and(notclock);acc_bus<=data_r(18);pc_bus<=data_r(16);inc_pc<=data_r(10);cs<=data_r(8);r_nw<=data_r(7);alu_add<=data_r(6);alu_sub<=data_r(5);ENDEND--libraryuseentityACCisload_acc:instd_logic;--脈沖信號q:instd_logic_vector(7downto0);d:bufferstd_logic_vector(7downto0));--結(jié)果endentity;architectureoneofACCisif(reset='0')thenendprocess;--libraryuseENTITYALUISALU_ACC:INOP:INSTD_LOGIC_VECTOR(1DOWNTO0);D_BUS:INSTD_LOGIC_VECTOR(7downto0);ACC:INSTD_LOGIC_VECTOR(7DOWNTO0);Flags:BUFFERSTD_LOGIC;ALU:BUFFERSTD_LOGIC_VECTOR(7DOWNTOENDENTITYarchitectureONEofALUifALU_ACC='1'caseOPwhenwhen"01"=>ALU<=ACC+(not--when"00"=>ALU<=ACCandD_BUS;when"11"=>ALU<=D_BUS;endcase;ifALU="00000000"thenendif;endif;endLIBRARYUSEIEEE.STD_LOGIC_UNSIGNED.ALL;USEWORK.CPU_DEFS.ALL;ENTITYRAMISPORT(reset:INSTD_LOGIC;cs:INSTD_LOGIC;R_NW:INSTD_LOGIC; :INSTD_LOGIC_VECTOR(7DOWNTO0);MDR_IN:INSTD_LOGIC_VECTOR(7DOWNTO0); :BUFFERSTD_LOGIC_VECTOR(7DOWNTOENDARCHITECTUREONEOFRAM STD_LOGIC_VECTOR(word_w-1DOWNTO0); :mem_array; CONSTANTprog :mem_array:=(0=>op2slv(load)&STD_LOGIC_VECTOR(TO_UNSIGNED(4,word_w-op_w)),--movacc,[4]將4轉(zhuǎn)換成5位的二進(jìn)制數(shù)，將4號單元的值實(shí)現(xiàn)load指令1=>op2slv(add) &STD_LOGIC_VECTOR(TO_UNSIGNED(5,word_w-op_w)),--add2=>op2slv(store)&STD_LOGIC_VECTOR(TO_UNSIGNED(6,word_w-op_w)),--將acc6號單元3=> &4=>5=>OTHERS(OTHERS'0'));ifreset='0'thenmem<=prog;MDR_out<=elsifrising_edge(cs)thenifR_NW='0'THENmem(conv_integer(MAR))<=MDR_OUT<=endENDlibraryieee;useieee.std_logic_1164.all;ENTITYPCIS(reset:IN :IN inc_pc:IN :IN STD_LOGIC_VECTOR(7DOWNTO0); :BUFFER STD_LOGIC_VECTOR(7DOWNTO0)ENDPC;ARCHITECTUREoneOFPCIFreset='0'THENpc<="00000000";ELSIFrising_edge(load_pc)THENIFinc_pc='1'THENENDENDIF;ENDPROCESS;libraryuseieee.std_logic_1164.all;ENTITYMARIS(reset:IN :IN :IN STD_LOGIC_VECTOR(7DOWNTO0); :BUFFER STD_LOGIC_VECTOR(7DOWNTO0)ENDMAR;ARCHITECTUREoneOFMARIFreset='0'THENq<=ELSIFrising_edge(load_mar)THENENDIF;ENDPROCESS;--MDR代碼：libraryuseieee.std_logic_1164.all;ENTITYMDRIS(reset ::DOWNTO:DOWNTO : STD_LOGIC_VECTOR(7DOWNTOENDMDR;ARCHITECTUREoneOFMDRIFreset='0'THENq<=ELSIFrising_edge(load_mdr)THENIFr_nw='0'THENELSIFr_nw='1'ENDENDIF;ENDPROCESS;--IRlibraryuseieee.std_logic_1164.all;ENTITYIRIS(reset:IN :IN :IN STD_LOGIC_VECTOR(7DOWNTO0); : STD_LOGIC_VECTOR(7DOWNTO : STD_LOGIC_VECTOR(2DOWNTOENDIR;ARC