數(shù)字設(shè)計(jì) 第六章 組合邏輯設(shè)計(jì)實(shí)踐學(xué)習(xí)課件

Chapter6CombinationalLogicDesignPracticesMSIbuildingblocksaretheimportantelementofcombinationalcircuits.2/28/20251本章重點(diǎn)具備一定功能的通用組合邏輯電路的設(shè)計(jì)方法及實(shí)例掌握常用的MSI的使用方法及功能擴(kuò)展掌握譯碼器、MUX實(shí)現(xiàn)組合邏輯功能的方法能分析、設(shè)計(jì)由MSI構(gòu)建的電路2/28/20252chapter66.1DocumentationStandard1.SignalNamesandActiveLevelsMostsignals(signalname)haveactivelevel.

activehighactivelowNamingconvention

surffix“_L”attachingtosignalnamerepresentactivelowlevel.Like,EN_L、READY_L……Inlogicrelation,EN_L=EN’，READY_L=READY’。2/28/20253chapter62.ActivelevelsforpinsENEN_LDinstartDoutflgstart_LDinDoutflg_LInversionbubbleActivelowENENDinstartDoutflgstartDinDoutflgActivehign2/28/20254chapter6Exp2：①EN=1(activehigh),datacanbetransferred②EN=0(activelow),datacanbetransferredENCLKEN_LCLK2/28/20255chapter63.bubble-to-bubblelogicdesignMakethelogiccircuiteasiertounderstand.Exp：NotmatchABSELDATAABASELDATAmatch2/28/20256chapter66.3CombinationalPLDs1.Programmablelogicarrays(PLA)twolevel“AND—OR”device.Canbeprogrammedtorealizeanysum-of-productslogicexpression.Ann×m

PLAwithpproductterms:n—inputsm—outputsp—productterms2/28/20257chapter64×3with6producttermsANDarrayORarray2/28/20258chapter62/28/20259chapter62.ProgrammableArrayLogicDevicesFixedORarray，programmableANDarrayBidirectionalinput/outputpins，熔絲型PAL16L8，Outputenable2/28/202510chapter63.GenericArrayLogicDevices（GAL）aninnovationofthePAL;canbeerasedandreprogrammed;2/28/202511chapter66.4DecoderAnimportanttypeofcombinationalcircuit.inputcodeword

enableinputOutputcodeword

decodeer1-to-1mapping1-out-of-mcoden<mn-bitm-bit2/28/202512chapter61、bianrydecodersinputcode：n-bitoutputcode：2n-bit⑴2-4decoder（2-22）

I1I0Y3Y2Y1Y0truthtable：？Yi：？I1I0Y3Y2Y1Y0000001010010100100111000Yi=miY0=I1’·I0’ Y1=I1’·I0Y2=I1·I0’ Y3=I1·I02-4decoderOneinputcombinationchoosesanoutputport.2/28/202513chapter62-4decoderwithenableinputYi=EN·miENI1I0Y3Y2Y1Y00××00001000001101001011001001111000I1I0Y3Y2Y1Y0EN2-4decoder2/28/202514chapter6（2）74×139,dual2-4decoderInputcode：B（MSB）

A（LSB）Alsobecalledaddressinput.Outputcode：Y3_L~Y0_LEN2/28/202515chapter6（3）74××138,3-8decoderEnableinputEN=G1·G2A_L’·G2B_L’Inputcode：C（MSB）、B、AOutputcode：

Y0_L~Y7_LYi_L=（EN·mi）’Y0_LY1_LY2_LY3_LY4_LY5_LY6_LY7_LG1G2A_LG2B_LEN2/28/202516chapter6ENmsblsb2/28/202517chapter62、realizingcombinationalcircuitswithdecoderreview：canonicalsumDecoderoutput：Yi_L=(EN·mi)’whenEN=1，Yi_L=mi’=MiaddanNANDgatetothedecoder’soutput.Exp:(1)F=∑AB（0、3）F=A’·B’+A·BEnableasserted2/28/202518chapter6（2）ifa3-bitnumberXYZisoddnumber，thenODDoutput1，elseoutput0.realizethefunctionwithdecoderandgates.solution：F=？F=ΣXYZ（1，3，5，7）2/28/202519chapter6（3）F=∏XYZ（0、1、5）

解：2/28/202520chapter63.CascadingbinarydecodersHowtoconstructa4-16、5-32……decoder？

usemultiple2-4or3-8decoderstocascade.PS.：confirmthenumberofdecodersaccordingtotheinputandoutputbits.onlyonechipworksineachdecoding.2/28/202521chapter6Exp：a4-16decoderInputs:4-bitN3、N2、N1、N0。Outputs:16-bitDEC15_L~DEC0_LNeed23-8decoders.

UsetheMSBoftheinputsaschip-selectbit. 0000

0001 0111… 1000

1001… 1111N3N2N1N0N3N2N1N02/28/202522chapter6Chipselecting2/28/202523chapter6Exp：4-bitprime-numberdetector.Realizingitwith74×138andsomegates.N3N2N1N0F2/28/202524chapter64、7-segmentdecoderClassifyof7-segdisplayer：inmaterials:LED（發(fā)光二極管）

LCD（液晶）Inworkingmode:common-cathode(共陰極)common-anode(共陽(yáng)極)afbcegddpabcdedpfggndgnd2/28/202525chapter67-segmentdecodertransformtheinputBCDcodeto7-segmentdisplayingcode.devices：

7446A、74LS47（驅(qū)動(dòng)共陽(yáng)）

74LS48、74LS49（驅(qū)動(dòng)共陰）0000~1001areusefulinputcodes.1010~1111areunusedBCDcode.2/28/202526chapter674LS492/28/202527chapter65、BCDdecoder（二—十進(jìn)制譯碼器）Inputs:BCDY0Y9……BCDdecoderOutput:1-out-of10code74HC422/28/202528chapter65.5Encoder1、binaryencoder…………

inputs:1-out-of-2n

codeI0I1Im(m=2n-1)……

output:n-bitY0Y1Yn-1binaryencoder2/28/202529chapter68-3encoderinputoutputI7I6I5I4I3I2I1I0Y2Y1Y01000000011101000000110001000001010001000010000001000011000001000100000001000100000001000In/out:activehigh2/28/202530chapter6Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I72/28/202531chapter62、PriorityEncoderifmultipleinputsareasserted,howtodealwith?solution：assignprioritytoeachinputfromhightolow.letI7—highestpriorityanddecreasefromI6downtoI0A2,A1,A0—encodeoutputIDLE—whennoinputisasserted,IDLE=12/28/202532chapter6inputoutputI7I6I5I4I3I2I1I0A2A1A0IDLE1×××××××111001××××××1100001×××××10100001××××100000001×××0110000001××01000000001×00100000000100000000000000012/28/202533chapter62/28/202534chapter63、74××148PriorityEncoderEI_L：EnableInput.I7_L~I0_L：encodeinput，I7_Lhashighestpriority.A2_L~A0_L：encodeoutputGS_L：GS_L=0whenoneormoreoftherequestinputsareasserted.EO_L：enableoutput,EO_L=0whenalloftherequestinputsarenegativeandEI_L=0.高低優(yōu)先級(jí)2/28/202535chapter674××148真值表2/28/202536chapter64、cascadingpriorityencoderproblem：howtoconstruct16-4、32-5……priorityencoder？Connectingmultiple8-3endoder.note：

makesuretheneedednumberofchipsaccordingtotheinputs.needtoredesigntheoutputcircuitthatcouldproducethecorrectencodingoutput.2/28/202537chapter616-4priorityencoder:usetwo74××148U1、U2，

U1:inputE15_L~E8_L;U2:inputE7_L~E0_L;E15_Listhehighestpriority,output:A3~A0，activehigh;Whenoneormoreinputsisasserted，GS0=1；andA3~A0=0000。U1U22/28/202538chapter6思考：若需要編碼輸出、GS0為低電平有效，如何修改電路輸出結(jié)構(gòu)？P.413figure6-49showsthe32-5priorityencoder’sstrcture,.2/28/202539chapter66.6Three-stateDevices1、three-statebuffers2/28/202540chapter6EN_LAOUTENEN_LAAOUT_LOUT_LEnablemeans:thebufferoutputnormallogic0、1whenENisasserted；thebufferoutputHi-ZwhenENisnegated.2/28/202541chapter6Applicationdata返回時(shí)序

addressofdatasource2/28/202542chapter6IssuesinapplicationTPLZ、TPHZ：timethattakesfromnormallogicintoHi-Z;TPZL、TPZH

：timethattakesfromHi-Zintonormallogic;generally，TPLZ、TPHZ<TPZL、TPZH

Buttoconfirmthecorrectioninapplication,acontrollogicisadopted.2/28/202543chapter674××

138的相關(guān)引腳信號(hào)查看電路

截止時(shí)間

（停滯時(shí)間）2/28/202544chapter6課堂練習(xí)試設(shè)計(jì)一個(gè)電路，當(dāng)控制信號(hào)M=1時(shí)，電路為“判一致”電路，即當(dāng)三個(gè)輸入變量取值全部相同時(shí)輸入為1；當(dāng)控制信號(hào)M=0時(shí)，電路為“多數(shù)表決”電路，即輸出等于輸入變量中占多數(shù)的取值。請(qǐng)寫出最簡(jiǎn)表達(dá)式。（注：至少要寫出卡諾圖，三變量為X、Y、Z）2/28/202545chapter66.7MultiplexerABSELY=AorB2-to-1MUXY=SEL’·A+SEL·B2/28/202546chapter6又稱數(shù)據(jù)選擇器，簡(jiǎn)稱MUXOutput:enableselect

ndatasource

dataoutput

n≤2s

mj：SEL[j]minterm1、基本結(jié)構(gòu)：2/28/202547chapter6Letb=1,D0D1DjDn-1SELENY……2/28/202548chapter6Exp:4-to-1MUXABCDS1S001101234outputCS0S1output00A01B10C11D2/28/202549chapter62、MSIMUX（1）8-to-1MUX，74××151EN_LaddressY_LY2/28/202550chapter6返回2/28/202551chapter6G_L

S（2）4-bit,2inputMUX，74××1572/28/202552chapter6（3）2bit,4inputMUX，74××153inputoutput1G_L2G_LBA1Y2Y00001C02C000011C12C100101C22C200111C32C301001C0001011C1001101C2001111C30100002C0100102C1101002C2101102C311××001G_L2G_L2/28/202553chapter63、ExpandingMUXsExp1：use74××151torealizea16-to-1MUX,somegatescanbeusedifnecessary.Chipsneeded：

accordingtothe16inputs,274××151chips.output：

combinetwochip’soutputsintooneoutput.2/28/202554chapter6TheMSB(A3)ofinputactasthechip-selectbit.2/28/202555chapter6Exp2：用74××153實(shí)現(xiàn)4輸入，4位MUX，。設(shè)4路輸入分別是：1D[3..0]、2D[3..0]、3D[3..0]、4D[3..0]；

4位輸出是：Dout[3..0]

輸入選擇：S1、S0解：無(wú)需外加門，只需要合理安排輸入、輸出數(shù)據(jù)端口即可。2/28/202556chapter6Dout3S1S02/28/202557chapter64、用MUX實(shí)現(xiàn)組合邏輯函數(shù)的標(biāo)準(zhǔn)和

multipleinput,1bitMUX,theoutput：

whenENisasserted：

thecanonicalsumform.74×151的內(nèi)部電路2/28/202558chapter6MUX的數(shù)據(jù)輸入端與真值表的每行輸出對(duì)應(yīng)，MUX的地址選擇端作為最小項(xiàng)產(chǎn)生器，即

真值表：輸出值 輸入變量

MUX：數(shù)據(jù)輸入端 地址端例1：試設(shè)計(jì)一個(gè)數(shù)據(jù)檢測(cè)電路，當(dāng)輸入3位二進(jìn)制數(shù)能被3整除時(shí)，輸出F為1，否則為0。請(qǐng)用74××151實(shí)現(xiàn)該邏輯函數(shù)。

解：F=∑XYZ（？）電路？按最小項(xiàng)編號(hào)順序變量與選擇端對(duì)應(yīng)2/28/202559chapter6例1的電路XYZFU1~W6D04D13D22D31D415D514D613D712A11C9B10Y5~G7VCCGNDR12/28/202560chapter6例2：若例1中輸入數(shù)為4位二進(jìn)制數(shù)，如何實(shí)現(xiàn)？解1：用16輸入，1位的MUX來(lái)實(shí)現(xiàn)，選用74××150。F=∑WXYZ（0，3，6，9，12，15）解2：仍選用74××151，先對(duì)所求函數(shù)的卡諾圖做降維處理。預(yù)備知識(shí)：卡諾圖的降維

用一個(gè)n變量的卡諾圖來(lái)處理m變量的函數(shù)（n<m），這種卡諾圖被稱為降維（降次）的卡諾圖。它允許單元格中除了0、1、無(wú)關(guān)項(xiàng)外，還可包含單變量或邏輯表達(dá)式。2/28/202561chapter6卡諾圖的降維卡諾圖降次的過(guò)程：設(shè)m=n+1，在m-變量函數(shù)F(X1,X2,…,Xn,Xn+1)中選擇一個(gè)“入圖”的變量Xi，用剩下的n個(gè)變量構(gòu)造n-變量卡諾圖。原圖中變量Xi取值相反所覆蓋的相鄰的兩個(gè)單元格被合并。（這兩個(gè)單元格的其余變量是相同的；在真值表中對(duì)應(yīng)著兩行，只有Xi是不同的，其余變量均相同。）00011110FWXYZ000111WYZX10選擇入圖將被合并2/28/202562chapter6降維的基本步驟①先建新的真值表，表中的輸入變量是除Xi而外剩下的變量，新行號(hào)由他們的組合值（最小項(xiàng)）確定。②若在原(n+1)變量真值表中，被合并的兩行的入圖變量Xi與對(duì)應(yīng)的F取值相同，則新表中F=XiWXYZFFnew×××00Z×××11W、X、Y取值相同2/28/202563chapter6③若在原(n+1)變量真值表中，被合并的兩行的入圖變量Xi與對(duì)應(yīng)的F取值相反，則新表中F=Xi’④若在原(n+1)變量真值表中，被合并的兩行的入圖變量Xi所對(duì)應(yīng)的F=1，則新表中F=1⑤若在原(n+1)變量真值表中，被合并的兩行的入圖變量Xi所對(duì)應(yīng)的F=0，則新表中F=0⑥得新的n變量卡諾圖⑦用MUX實(shí)現(xiàn)2/28/202564chapter6輸入輸出WXYZF0000100010001000011101000010100110101110輸入輸出WXYZF1000010011101001011011001110101110011111新輸出FZ’Z0Z’0123新編號(hào)4567新編號(hào)新輸出FZ0Z’Z2/28/202565chapter6卡諾圖中降維原4變量卡諾圖 新3變量卡諾圖1000010100011110F00100101WXYZ000111WYZX100ZZ’ZZZ’0Z’WXFnewYWYX2/28/202566chapter6例2的電路圖U1~W6D04D13D22D31D415D514D613D712A11C9B10Y5~G7GNDIO1U2AZZ’WXYF2/28/202567chapter65.Multiplexers、DemultiplexersandBusesdemultiplexersDin……

2nbitparalleloutputdemultiplexers…1-bitD0D1Dm最多m=2nSELn-bitNoDeMUXchips,abinarydecoderwithenableinputcanbeusedasaDeMUX.2/28/202568chapter6MUX、DeMUX應(yīng)用于數(shù)據(jù)的選擇與分配MUX：combinemparallel-inputdatasourcesintoserialoutputdata.DeMUX：routethebusdatato1ofmdestinations.MUXDe

-MUX……SRCASRCBSRCCSRCZSRCSELBUSDSTSELDSTADSTBDSTCDSTZ2/28/202569chapter6（1）MUX：parallel—serialconversion

8-to-1

MUXD0D1D2D3D4D5D6D7S2S1S0t2/28/202570chapter62/28/202571chapter6（2）DeMUX:serial—parallelconversionUsea74××138asaDeMUX.2/28/202572chapter6DiagramofExp.S2S1S0111110101100011010001000010101012/28/202573chapter66.8Exclusive-ORgatesandParitycircuits1、XORandXNORgatesXYX⊕Y(X⊕Y)’XORXNOR0001011010101101（X⊙Y）XORXNOR記憶：異或門—相同為0，相異為1

異或非門—與異或相反2/28/202574chapter6PropertiesX⊕0=X

X⊕1=X’X⊕X=0

X⊕X’=1X⊕Y=Y⊕XX⊕Y⊕Z=(X⊕Y)⊕Z=X⊕(Y⊕Z)Equivalentsymbols

Anytwosignals(inputsoroutputs)ofanXORorXNORgatemaybecomplementedwithoutchangingtheresultinglogicfunction.2/28/202575chapter6FeatureofXORexpression(k-map)X⊕Y⊕Z=X’YZ’+XY’Z’+X’Y’Z+XYZFXYZ0

1

01101000011110XY01Z010100001111XYZ2/28/202576chapter62、paritycircuitsn個(gè)異或門級(jí)聯(lián)起來(lái)，可對(duì)n+1個(gè)數(shù)作奇校驗(yàn)（Odd-paritychecking）。輸入數(shù)中有奇數(shù)個(gè)1，則輸出ODD=1。

ODD=I1⊕I2⊕……⊕In

Daisy-chainconnection2/28/202577chapter6Complementtheoutputofodd-paritycircuit，itcanworksasanEven-paritywhichoutput1ifanevennumberofitsinputare1.Treestructure，hasfasteroperationspeed.2/28/202578chapter6奇偶校驗(yàn)的實(shí)現(xiàn)奇偶校驗(yàn)碼(補(bǔ)充)

由n位信息位+1位奇偶校驗(yàn)位構(gòu)成。偶校驗(yàn)編碼：n+1位編碼中包含偶數(shù)個(gè)1。奇校驗(yàn)編碼：n+1位編碼中包含奇數(shù)個(gè)1。例：某檢測(cè)電路采用1位奇校驗(yàn)碼方式，假設(shè)數(shù)據(jù)是三位，請(qǐng)給出奇偶校驗(yàn)位的產(chǎn)生電路。B200001111B100110011B001010101P10010110輸入輸出2/28/202579chapter63、74×2809-bitparitygenerator可在存儲(chǔ)和發(fā)送碼字時(shí)生成奇偶校驗(yàn)位，也可在恢復(fù)和接收碼字時(shí)檢查奇偶校驗(yàn)位。EVEN=A⊕B⊕C⊕D⊕E⊕F⊕(G⊕H⊕I)’ODD=A⊕B⊕C⊕D⊕E⊕F⊕G⊕H⊕I2/28/202580chapter61數(shù)據(jù)鎖存dataPIN存儲(chǔ)器WRRDRDWRPOUTERROR0101ODD=A⊕B⊕C⊕D⊕E⊕F⊕G⊕H⊕I=PIN=POUT22/28/202581chapter65.9比較器（Comparators）比較器：比較器—只比較兩個(gè)數(shù)是否相等數(shù)值比較器—將輸入數(shù)解釋為無(wú)符號(hào)數(shù)或符號(hào)數(shù)，并指出它們之間的算術(shù)關(guān)系（大于、等于、小于）。2/28/202582chapter61、比較器結(jié)構(gòu)（1）1-bit比較器（2）多位比較器

并行比較

串行比較DIFF=A0⊕B0EQ=（A0⊕B0）’2/28/202583chapter6并行比較器

4-bit比較器串行比較器：利用迭代電路2/28/202584chapter62.迭代電路（IterativeCircuit）迭代電路：由n個(gè)相同的模塊電路串聯(lián)而成，包含主輸入、輸出和級(jí)聯(lián)輸入、輸出。邊界輸出CICOPIPOC0C1PI0PO0CICOPIPOPI1PO1CICOPIPOPIn-1POn-1CnC2…Cn-1邊界輸入級(jí)聯(lián)輸入級(jí)聯(lián)輸出2/28/202585chapter6比較器模塊迭代比較電路EQIEQOXY1X0Y0EQIEQOXYX1Y1EQ1EQ2…EQIEQOXYXn-1Yn-1EQn速度慢，擴(kuò)展方便2/28/202586chapter63.數(shù)值比較器（1）1-bit數(shù)值比較器（Magnitudecomparators）ABF(A>B)F(A=B)F(A<B)00010010011010011010FA>B=AB’FA<B=A’BFA=B=A’B’+AB2/28/202587chapter6（2）多位數(shù)值比較器2-bit數(shù)值比較器，輸入數(shù)為A[1..0]、B[1..0]A1B1A0B0FA>BFA=BFA<B01××110××10000100011001010011111001110111110111111從高位到低位逐位比較2/28/202588chapter6

FA>B=(A1>B1)+(A1=B1)·(A0>B0)

=A1·B1’+(A’B’+AB)·(A1·B1’)FA=B=(A1=B1)·(A0=B0)FA<B=(A1<B1)+(A1=B1)·(A0<B0)A1B1A0B0FA>BFA=BFA<BA1<B1××1A1>B1××1A1=B1A0<B01A1=B1A0>B01A1=B1A0=B01偽邏輯2/28/202589chapter64.標(biāo)準(zhǔn)MSI比較器4-bit數(shù)值比較器74×85級(jí)聯(lián)輸入：ALBI、AEBI、AGBI，用于比較器的擴(kuò)展比較輸出（級(jí)聯(lián)輸出）：ALBO、AEBO、AGBOAGBO=(A>B)+(A=B)·AGBIAEBO=(A=B)·AEBIALBO=(A<B)+(A=B)·ALBI2/28/202590chapter6數(shù)值比較器的擴(kuò)展

串行方式擴(kuò)展FA>BFA=BFA<B2/28/202591chapter6并行方式擴(kuò)展F