慢速充電時鐘芯片DS1302中英文資料

1、慢速充電時鐘芯片ds1302一、特性1、實時時鐘，可對秒、分、時、日、周、月以及帶閏年補(bǔ)償?shù)哪赀M(jìn)行計數(shù),有效期2100年。2、用于高速數(shù)據(jù)暫存的318 ram3、最少引腳數(shù)的串行i/o4、2.0-5.5v滿度工作范圍5、2.5v時耗電小于300na6、用于時鐘或ram數(shù)據(jù)讀/寫的單字節(jié)或多字節(jié)（脈沖方式）數(shù)據(jù)傳送7、8引腳dip或可選的用于表面安裝的8引腳soic封裝8、簡單的3線接口9、ttl兼容（vcc=5v）10、可選的工業(yè)溫度范圍-40至+8511、與ds1202兼容二、引腳排列三、引腳說明x1，x2：32.768khz晶振引腳；gnd：接地；rst：復(fù)位；i/o：數(shù)據(jù)輸入/輸出；sc

2、lk：串行時鐘；vcc1，vcc2：電源引腳。四、說明ds1302慢速充電時鐘芯片包括實時時鐘/日歷和31字節(jié)的靜態(tài)ram。它經(jīng)過一個簡單的串行接口與微處理器通信。實時時鐘/日歷提供秒、分、時、日、周、月和年等信息。對于小于31天的月，月末的日期自動進(jìn)行調(diào)整，還包括了閏年校正的功能。時鐘的運(yùn)行可以采用24小時或帶am（上午）/pm（下午）的12小時格式。使用同步串行通信，簡化了ds1302與微處理器的通信。與時鐘/ram通信僅需三根線：（1）rst（復(fù)位）、（2）i/o（數(shù)據(jù)線）、和（3）sclk（串行時鐘）。數(shù)據(jù)可以以每次一個字節(jié)或多達(dá)31字節(jié)的多字節(jié)形式傳送至?xí)r鐘/ram或從其中送出。ds

3、1302設(shè)計成能在非常低的功耗下工作，消耗小于1微瓦的功率便能保存數(shù)據(jù)和時鐘信息。ds1302是ds1202的升級產(chǎn)品，除了ds1202基本的慢速充電功能外，ds1302具有的其它特點(diǎn)包括：用于主電源和備份電源的雙電源引腳，可編程的vcc1慢速充電器以及7個附加字節(jié)的高速暫存存儲器（scratchpad memory）。（1）、工作原理串行時鐘芯片的主要組成部分示于圖1：移位寄存器、控制邏輯、振蕩器、實時時鐘以及ram。（2）、信號說明vcc1：vcc1在單電源與電池供電的系統(tǒng)中提供低電源并提供低功率的電池備份。通過連接這個引腳對系統(tǒng)實時充電。vcc2：vcc2在雙電源系統(tǒng)中提供主電源，在這種

4、運(yùn)用方式中vcc1連接到備份電源，以便在沒有主電源的情況下能保存時間信息以及數(shù)據(jù)。ds1302由vcc1或vcc2兩者中較大者供電。當(dāng)vcc2大于vcc1+0.2v時，vcc2給ds1302供電。當(dāng)vcc2小于vcc1時，ds1302由vcc1供電。時鐘（串行時鐘輸入） -時鐘用于同步數(shù)據(jù)移動的串行接口。i/o（數(shù)據(jù)輸入/輸出）-對i/o引腳是雙向數(shù)據(jù)引腳的3線接口。復(fù)位（復(fù)位） -復(fù)位信號必須在高電平讀取或?qū)懭?。x1，x2：連接為一個標(biāo)準(zhǔn)的32.768 khz的石英晶體。所選用晶振規(guī)定的負(fù)載電容量應(yīng)當(dāng)為6pf。（3）、命令字節(jié)命令字節(jié)示于圖2。每一數(shù)據(jù)傳送由命令字節(jié)初始化。最高有效位msb（

5、位7）必須為邏輯1。如果它是零，禁止寫ds1302。位6為邏輯0指定時鐘/日歷數(shù)據(jù)；邏輯1指定ram數(shù)據(jù)。位1至5指定進(jìn)行輸入或輸出的特定寄存器。最低有效位lsb（位0）為邏輯0指定進(jìn)行寫操作（輸入）；邏輯1指定進(jìn)行讀操作（輸出）。命令字節(jié)總是從最低有效lsb（位0）開始輸入。（4）、復(fù)位和時鐘控制通過把rst輸入驅(qū)動至高電平來啟動所有的數(shù)據(jù)傳送。rst輸入有兩種功能。首先，rst接通控制邏輯，允許地址/命令序列送入移位寄存器。其次，rst提供了中止單字節(jié)或多字節(jié)數(shù)據(jù)傳送的手段。時鐘是下降沿后繼以上升沿的序列。數(shù)據(jù)輸入時，在時鐘的上升沿數(shù)據(jù)必須有效，而數(shù)據(jù)位在時鐘的下降沿輸出。如果rst輸入為

6、低電平，那么所有的數(shù)據(jù)傳送中止且i/o引腳變?yōu)楦咦杩範(fàn)顟B(tài)。數(shù)據(jù)傳送在圖3中說明。上電時，在vcc2.0伏之前rst必須為邏輯0。此外，當(dāng)把rst驅(qū)動至邏輯1的狀態(tài)時，sclk必須為邏輯0。圖3數(shù)據(jù)傳輸概要（5）數(shù)據(jù)輸入跟隨在輸入寫命令字節(jié)的8個sclk周期之后，在下8個sclk周期的上升沿輸入數(shù)據(jù)字節(jié)。如果有額外的sclk周期，它們將被忽略。數(shù)據(jù)從位0開始輸入。（6）數(shù)據(jù)輸出跟隨在輸入讀命令字節(jié)的8個sclk周期之后，在下8個sclk周期的下降沿輸出數(shù)據(jù)字節(jié)。注意，被傳送的第一個數(shù)據(jù)位發(fā)生在寫命令字節(jié)的最后一位之后的第一個下降沿。只要rst保持為高電平，如果有額外的sclk周期，它們將重新發(fā)送

7、數(shù)據(jù)字節(jié)。這一操作使之具有連續(xù)的多字節(jié)方式的讀能力。另外，在sclk的每一上升沿，i/o引腳為三態(tài)。數(shù)據(jù)從位0開始輸出。（7）、多字節(jié)方式通過對地址31（十進(jìn)制）尋址（地址/命令位1至5=邏輯1），可以把時鐘/日歷或ram寄存器規(guī)定為多字節(jié)（burst）方式。如前所述，位6規(guī)定時鐘或ram而位0規(guī)定讀或?qū)憽Ｔ跁r鐘/日歷寄存器中的地址9至31或ram寄存器中的地址31不能存儲數(shù)據(jù)。在多字節(jié)方式中讀或?qū)憦牡刂?的位0開始。與使用ds1202時一樣，當(dāng)以多字節(jié)方式寫時鐘寄存器時，必須按數(shù)據(jù)傳送的次序?qū)懽钕?個寄存器。但是，當(dāng)以多字節(jié)方式寫ram時，為了傳送數(shù)據(jù)不必寫所有31個字節(jié)。不管是否寫了全部3

8、1個字節(jié)，所寫的每一個字節(jié)都將傳送至ram。（8）、時鐘/日歷如圖4所示，時鐘/日歷包含在7個寫/讀寄存器內(nèi)。包含在時鐘/日歷寄存器內(nèi)的數(shù)據(jù)是二十進(jìn)制（bcd）碼。（9）、時鐘暫停秒寄存器的位7定義為時鐘暫停位。當(dāng)此位設(shè)置為邏輯1時，時鐘振蕩器停止，ds1302被置入低功率的備份方式，其電源消耗小于100毫微安（nanoamp）。當(dāng)把此位寫成邏輯0時，時鐘將啟動。（10）、am-pm/12-24方式小時寄存器的位7定義為12或24小時方式選擇位。當(dāng)它為高電平時，選擇12小時方式。在12小時方式下，位5是am/pm位，此位為邏輯高電平表示pm。在24小時方式下，位5是第2個10小時位（20-23

9、時）。（11）、寫保護(hù)寄存器寫保護(hù)寄存器的位7是寫保護(hù)位。開始7位（位0-6）置為零，在讀操作時總是讀出零。在對時鐘或ram進(jìn)行寫操作之前，位7必須為零。當(dāng)它為高電平時，寫保護(hù)位防止對任何其它寄存器進(jìn)行寫操作。（12）、慢速充電（trickle charge）寄存器這個寄存器控制ds1302的慢速充電特性。圖5的簡化電路表示慢速充電器的基本組成。慢速充電選擇（tcs）位（位4-7）控制慢速充電器的選擇。為了防止偶然的因素使之工作，只有1010模式才能使慢速充電器工作，所有其它的模式將禁止慢速充電器。ds1302上電時，慢速充電器被禁止。二極管選擇（ds）位（位2-3）選擇是一個二極管還是兩個二

10、極管連接在vcc2與vcc1之間。如果ds為01，那么選擇一個二極管；如果ds為10，則選擇兩個二極管。如果ds為00或11，那么充電器被禁止，與tcs無關(guān)。rs位（位0-1）選擇連接在vcc2與vcc1之間的電阻。電阻選擇（rs）位選擇的電阻如下：如果rs為00，充電器被禁止，與tcs無關(guān)。二極管和電阻的選擇由用戶根據(jù)電池或超容量電容充電所需的最大電流決定。最大充電電流可以如下列所說明的那樣進(jìn)行計算。假定5v系統(tǒng)電源加到vcc2而超容量電容接至vcc1。再假設(shè)慢速充電器工作時在vcc2和vcc1之間接有一個二極管和電阻r1。因而最大電流可計算如下：imax=（5.0v二極管壓降）/r1（5.

11、0v0.7v）/2k2.2ma顯而易見，當(dāng)超容量電容充電時，vcc2和vcc1之間的電壓減少，因而充電電流將會減小。（13）、時鐘/日歷多字節(jié)（burst）方式時鐘/日歷命令字節(jié)可規(guī)定多字節(jié)工作方式。在此方式下，最先8個時鐘/日歷寄存器可以從地址0的第0位開始連續(xù)地讀或?qū)懀ㄒ妶D4）。當(dāng)指定寫時鐘/日歷的多字節(jié)方式時，如果寫保護(hù)位設(shè)置為高電平，那么沒有數(shù)據(jù)會傳送到8個時鐘/日歷寄存器（包括控制寄存器）的任一個。在多字節(jié)方式下，慢速充電器是不可訪問的。（14）、ram靜態(tài)ram是ram地址空間中順序?qū)ぶ返?18字節(jié)。（15）、ram多字節(jié)方式ram命令字節(jié)可規(guī)定多字節(jié)工作方式。在此方式下，可以從地

12、址0的第0位開始順序讀或?qū)?1 ram寄存器（見圖4）。（16）、寄存器概要寄存器數(shù)據(jù)格式概要示于圖4。（17）、晶振選擇32.768khz的晶振（諸如daiwa公司的dt26s、seiko公司的ds-vt-200或其他類似產(chǎn)品）可通過引腳2和3（x1，x2）直接連接至ds1302。所選用晶振規(guī)定的負(fù)載電容量（cl）應(yīng)當(dāng)為6pf。晶振可從dallas半導(dǎo)體公司訂購。訂購器件號是ds9032。五、極限參數(shù)*任何引腳相對于地的電壓 0.5v至+7.0v運(yùn)用溫度 0至70貯存溫度 55至+125焊接溫度 260，10秒* 強(qiáng)度超出所列的極限參數(shù)可能導(dǎo)致器件的永久性損壞。這些僅僅是極限參數(shù)，并不意味著

13、在極限條件下或在任何其它超出推薦工作條件所示參數(shù)的情況下器件能有效地工作。延長在極限參數(shù)條件下的工作時間會影響器件的可靠性。六、推薦的直流運(yùn)用條件七、直流電特性八、電容（ta=25）九、交流電特性（除非另有說明，0至70；vcc=2.0v至5.5v）十、時序圖十一、注意：1. 所有電壓以地為參考點(diǎn)。2. 對于電容性負(fù)載,提供電流1mavcc=5v和0.4ma、vcc=2.5v、voh=vcc條件下規(guī)定邏輯1的電壓。3. 對于電容性負(fù)載，在吸收電流4ma、vcc=5v和1.5ma、vcc=2.5v、vol=地的條件下規(guī)定邏輯0的電壓。4. 在i/o開路、rst設(shè)置為邏輯0、時鐘暫停標(biāo)志=0（允許

14、振蕩器工作）條件下規(guī)定icc1t和icc2t。5. 在i/o引腳開路、rst設(shè)置為高電平、vcc=5v時sclk=2mhz；vcc=2.5v時sclk= 500khz以及時鐘暫停標(biāo)志=0（允許振蕩器工作）的條件下規(guī)定icc1a和icc2a。6. rst、sclk和i/o均接有40k下拉電阻至地。7. 在vih=2.0v或vil=0.8v以及最大為10ms上升和下降時間條件下測量。8. 在voh=2.4v或vol=0.4v條件下測量。9. 負(fù)載電容=50pf。10. 在rst、i/o和sclk開路條件下規(guī)定icc1s和icc2s。時鐘暫停標(biāo)志必須設(shè)置為邏輯1（禁止振蕩器工作）。11. 當(dāng)vcc2

15、vcc1+0.2v時，vcc=vcc2；當(dāng)vcc1vcc2時，vcc=vcc1。12. vcc2=0伏。13. vcc1=0伏。14. 典型值為25時的數(shù)值。ds1302 trickle charge timekeeping chip一、features1、real time clock counts seconds, minutes hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100.2、31 x 8 ram for scratchpad

16、 data storage.3、serial i/o for minimum pin count.4、2.05.5v full operation.5、uses less than 300 na at 2.0v.6、singlebyte or multiplebyte (burst mode) data transfer for read or write of clock or ram data.7、8pin dip or optional 8pin soics for surface mount.8、simple 3wire interface.9、ttlcompatible (vcc =

17、 5v).10、optional industrial temperature range 40c to +85c.11、ds1202 compatible.二、pin assignment三、pin descriptionx1, x2：32.768 khz crystal pins；gnd：ground；rst：reset；i/o：data input/output；sclk：serial clock；vcc1, vcc2：power supply pins四、description the ds1302 trickle charge timekeeping chip contains a

18、real time clock/calendar and 31 bytes of static ram. it communicates with a microprocessor via a simple serial interface. the real time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with less th

19、an 31 days, including corrections for leap year. the clock operates in either the 24hour or 12hour format with an am/pm indicator. interfacing the ds1302 with a microprocessor is simplified by using synchronous serial communication. only three wires are required to communicate with the clock/ram: (1

20、) rst(reset), (2) i/o (data line), and (3) sclk (serial clock). data can be transferred to and from the clock/ram 1 byte at a time or in a burst of up to 31 bytes. the ds1302 is designed to operate on very low power and retain data and clock information on less than 1 microwatt.the ds1302 is the suc

21、cessor to the ds1202. in addition to the basic timekeeping functions of the ds1202, the ds1302 has the additional features of dual power pins for primary and backup power supplies, programmable trickle charger for vcc1, and seven additional bytes of scratchpad memory.（1）、operationthe main elements o

22、f the serial timekeeper are shown in figure 1: shift register, control logic, oscillator,real time clock, and ram.ds1302 block diagram figure 1（2）、signal descriptions vcc1： vcc1 provides low power operation in single supply and battery operated systems as well as low power battery backup. in systems

23、 using the trickle charger, the rechargeable energy source is connected to this pin.vcc2 ：vcc2 is the primary power supply pin in a dual supply configuration. vcc1 is connected to a backup source to maintain the time and date in the absence of primary power.the ds1302 will operate from the larger of

24、 vcc1 or vcc2. when vcc2 is greater than vcc1 + 0.2v, vcc2 will power the ds1302. when vcc2 is less than vcc1, vcc1 will power the ds1302.sclk (serial clock input) sclk is used to synchronize data movement on the serial interface.i/o (data input/output) the i/o pin is the bi-directional data pin for

25、 the 3-wire interface.rst (reset) the reset signal must be asserted high during a read or a write.x1, x2 ： connections for a standard 32.768 khz quartz crystal. the internal oscillator is designed for operation with a crystal having a specified load capacitance of 6 pf. （3）、command bytethe command b

26、yte is shown in figure 2. each data transfer is initiated by a command byte. the msb (bit 7) must be a logic 1. if it is 0, writes to the ds1302 will be disabled. bit 6 specifies clock/calendar data if logic 0 or ram data if logic 1. bits 1 through 5 specify the designated registers to be input or o

27、utput, and the lsb (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. the command byte is always input starting with the lsb (bit 0).address/command byte figure 2（4）、reset and clock controlall data transfers are initiated by driving the rst input high. the

28、rst input serves two functions. first, rst turns on the control logic which allows access to the shift register for the address/command sequence. second, the rst signal provides a method of terminating either single byte or multiple byte data transfer. a clock cycle is a sequence of a falling edge f

29、ollowed by a rising edge. for data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. if the rst input is low all data transfer terminates and the i/o pin goes to a high impedance state. data transfer is illustrated in figure 3. at p

30、owerup, rst must be a logic 0 until vcc 2.0 volts. also sclk must be at a logic 0 when rst is driven to a logic 1 state.data transfer summary figure 3（5）、data inputfollowing the eight sclk cycles that input a write command byte, a data byte is input on the rising edge of the next eight sclk cycles.

31、additional sclk cycles are ignored should they inadvertently occur. data is input starting with bit 0.（6）、data outputfollowing the eight sclk cycles that input a read command byte, a data byte is output on the falling edge of the next eight sclk cycles. note that the first data bit to be transmitted

32、 occurs on the first falling edge after the last bit of the command byte is written. additional sclk cycles retransmit the data bytes should they inadvertently occur so long as rst remains high. this operation permits continuous burst mode read capability. also, the i/o pin is tristated upon each ri

33、sing edge of sclk. data is output starting with bit 0.（7）、burst modeburst mode may be specified for either the clock/calendar or the ram registers by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). as before, bit 6 specifies clock or ram and bit 0 specifies read or write

34、. there is no data storage capacity at locations 9 through 31 in the clock/calendar registers or location 31 in the ram registers. reads or writes in burst mode start with bit 0 of address 0. when writing to the clock registers in the burst mode, the first eight registers must be written in order fo

35、r the data to be transferred. however, when writing to ram in burst mode it is not necessary to write all 31 bytes for the data to transfer. each byte that is written to will be transferred to ram regardless of whether all 31 bytes are written or not.（8）、clock/calendarthe clock/calendar is contained

36、 in seven write/read registers as shown in figure 4. data contained in the clock/ calendar registers is in binary coded decimal format (bcd).register address/definition figure 4：（9）、clock halt flagbit 7 of the seconds register is defined as the clock halt flag. when this bit is set to logic 1, the c

37、lock oscillator is stopped and the ds1302 is placed into a lowpower standby mode with a current drain of less than 100 nanoamps. when this bit is written to logic 0, the clock will start. the initial power on state is not defined.（10）、am-pm/12-24 modebit 7 of the hours register is defined as the 12

38、or 24hour mode select bit. when high, the 12hour mode is selected. in the 12hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24hour mode, bit 5 is the second 10-hour bit (20 23 hours).（11）、write protect bitbit 7 of the control register is the write-protect bit. the first seven bits

39、 (bits 0 6) are forced to 0 and will always read a 0 when read. before any write operation to the clock or ram, bit 7 must be 0. when high, the write protect bit prevents a write operation to any other register. the initial power on state is not defined. therefore the wp bit should be cleared before

40、 attempting to write to the device.（12）、trickle charge registerthis register controls the trickle charge characteristics of the ds1302. the simplified schematic of figure 5 shows the basic components of the trickle charger. the trickle charge select (tcs) bits (bits 4 -7) control the selection of th

41、e trickle charger. in order to prevent accidental enabling, only a pattern of 1010 will enable the trickle charger. all other patterns will disable the trickle charger. the ds1302 powers up with the trickle charger disabled. the diode select (ds) bits (bits 2 3) select whether one diode or two diode

42、s are connected between vcc2 and vcc1. if ds is 01, one diode is selected or if ds is 10, two diodes are selected. if ds is 00 or 11, the trickle charger is disabled independently of tcs. the rs bits (bits 0 -1) select the resistor that is connected between vcc2 and vcc1. the resistor selected by th

43、e resistor select (rs) bits is as follows.if rs is 00, the trickle charger is disabled independently of tcs.diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated

44、 in the following example. assume that a system power supply of 5 volt is applied to vcc2 and a super cap is connected to vcc1. also assume that the trickle charger has been enabled with one diode and resistor r1 between vcc2 and vcc1. the maximum current imax would therefore be calculated as follow

45、s:imax = (5.0v diode drop) / r1 (5.0v 0.7v) / 2 k 2.2 maobviously, as the super cap charges, the voltage drop between vcc2 and vcc1 will decrease and thereforethe charge current will decrease.（13）、clock/calendar burst modethe clock/calendar command byte specifies burst mode operation. in this mode t

46、he first eight clock/calendar registers can be consecutively read or written (see figure 4) starting with bit 0 of address 0. if the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the eight clock/calendar registers (this inclu

47、des the control register). the trickle charger is not accessible in burst mode. at the beginning of a clock burst read, the current time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the

48、need to re-read the registers in case of an update of the main registers during a read.(14)、ramthe static ram is 31 x 8 bytes addressed consecutively in the ram address space.(15)、ram burst modethe ram command byte specifies burst mode operation. in this mode, the 31 ram registers can be consecutive

49、ly read or written (see figure 4) starting with bit 0 of address 0.(16)、register summarya register data format summary is shown in figure 4.(17)、crystal selectiona 32.768 khz crystal can be directly connected to the ds1302 via x1 and x2. the crystal selected for use should have a specified load capacitance (cl) of 6 pf. for more information on crystal selection and crystal layout consideration, please consult application note 58, “crystal considerations with dallas real time clocks.五、absolute maximum ratings*voltage on any pin relative to grou