(完整word版)VHDL語言實例.doc

1、VHDL語言實例例 1：設(shè)計一七段顯示譯碼器，用它來驅(qū)動七段發(fā)光管 LED顯示十六進(jìn)制數(shù)字 0 到 9 和字母 A 到 F。LED顯示數(shù)碼管為共陽極。LIBRARYieee;USE ieee.std_logic_1164.all;ENTITY HEX2LEDISPORT(HEX :IN std_logic_vector(3 DOWNTO0);LED : OUT std_logic_vector(6 TO0);圖例 1 七段顯示譯碼END 器實體 HEX2LED;ARCHITECTURE HEX2LED_arc OF HEX2LED ISBEGIN- HEX-TO-SEVEN-SEGMENT D

2、ECODER- SEGMENT ENCODING-0- 5 |1- - -6- 4 |2-3WITH HEX SELECTLED= 1111001 when 0001,0100100 when 0010,0110000 when 0011,0011001 when 0100,0010010 when 0101,0000010 when 0110,1111000 when 0111,0000000 when 1000,0010000 when 1001,0001000 when 1010,0000011 when 1011,1000110 when 1100,0100001 when 1101,

3、0000110 when 1110,0001110 when 1111,1000000 when others;END HEX2LED_arc;例 2：設(shè)計一個八選一數(shù)據(jù)選擇器1）s 是通道選擇信號 ,d0,d1,d2,d3,d4,d5,d6,d7數(shù)據(jù)輸入out1 是數(shù)據(jù)輸出ENTITY sels ISPORT(d0,d1,d2,d3,d4,d5,d6,d7:INBIT;s :INTEGERRANGE0TO7;out1 :OUT BIT);END sels;圖例 2（a)八選一數(shù)據(jù)選擇器實體ARCHITECTURE sels_arc OF sels ISBEGINWITH s SELECTou

4、t1 = d0 WHEN 0,d1 WHEN 1,d2 WHEN 2,d3 WHEN 3,d4 WHEN 4,d5 WHEN 5,d6 WHEN 6,d7 WHEN 7;END sels_arc;2)A,B,C 是通道選擇信號 ,I0,I1,I2,I3,I4,I5,I6,I7數(shù)據(jù)輸入Q 是數(shù)據(jù)輸出LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY mux8 ISPORT(I0,I1,I2,I3,I4,I5,I6,I7,A,B,C:INstd_logic;Q :OUT std_logic);END mux8;圖例2（b)八選一數(shù)據(jù)選擇器實體ARCHIT

5、ECTURE mux8_arc OF mux8 ISSIGNAL sel :INTEGER；BEGINQ = I0 AFTER 10 ns WHEN sel= 0 ELSEI1 AFTER 10 ns WHEN sel= 1 ELSEI2 AFTER 10 ns WHEN sel= 2 ELSEI3 AFTER 10 ns WHEN sel= 3 ELSEI4 AFTER 10 ns WHEN sel= 4 ELSEI5 AFTER 10 ns WHEN sel= 5 ELSEI6 AFTER 10 ns WHEN sel= 6 ELSEI7 AFTER 10 ns ;sel = 0 WHEN

6、 A= 0 AND B= 0 AND C= 0 ELSE1 WHEN A=1 AND B= 0 AND C=0 ELSE2 WHEN A=0 AND B= 1 AND C=0 ELSE3 WHEN A=1 AND B= 1 AND C=0 ELSE4 WHEN A=0 AND B= 0 AND C=1 ELSE5 WHEN A=1 AND B= 0 AND C=1 ELSE6 WHEN A=0 AND B= 0 AND C=1 ELSE7;END mux8_arc;例 3：設(shè)計一 D觸發(fā)器d 是輸入端， clk 是時鐘信號控制端， q 是觸發(fā)器的輸出端。其程序如下：LIBRARY ieee;U

7、SE ieee.std_logic_1164.all;ENTITY reg ISPORT(d,clk:IN BIT;q:OUTBIT);END reg;圖例 3 D 觸發(fā)器實體ARCHITECTURE reg_arc OF reg ISBEGINPROCESSBEGINWAIT UNTIL clk=1;q = d;END PROCESS;PROCESSEND reg_arc;例 4：設(shè)計一基本 RS觸發(fā)器r 、s 為觸發(fā)器的輸入信號， q、not_q 為觸發(fā)器的輸出信號。LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY RSFF ISPORT(r,

8、s:IN BIT;q,not_q:OUTBIT);END RSFF;圖例 4 基本 RS觸發(fā)器實體ARCHITECTURE RSFF_arc OF RSFF ISBEGINPROCESS(r,s)VARIABLE last_state:BIT:=0;BEGINASSERT NOT(r=1 AND s= 1)REPORT“Both r AND s equal to1”SEVERITY error;IF r=0 AND s= 0 THENlast_state:= last_state ;ELSIF r= 1 AND s= 0 THENlast_state:=0;ELSE -r= 0 AND s=

9、1last_state:=1;END IF;q = last_state AFTER 10 ns;not_q = NOT(last_state) AFTER 20 ns;END PROCESS;END RSFF_arc;當(dāng) r 和 s 同時等于 1 時，觸發(fā)器處于不定狀態(tài)。 程序設(shè)計中設(shè)置了斷言語句是為了判斷 r 和 s 都等于 1 時，輸出終端將顯示報告“ Both r ANDs equal to 1”，同時終止模擬過程， 并顯示錯誤的嚴(yán)重 error ，以便設(shè)計者調(diào)試和修正模塊程序。從 IF 到 ENDIF 是條件語句， 用到了可選項 ELSIF 和 ELSE來判別 RS觸發(fā)器的其它三種情

10、況。IF 語句后面是一賦值語句， 將 IF 語句中賦值的中間變量 lsat_state經(jīng) 10 ns 后送到 q 端。圖 8-12 是 RS觸發(fā)器的邏輯電路圖。例 5：設(shè)計一個帶有異步清零、同步置數(shù)、使能控制的四位二進(jìn)制計數(shù)器LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY COUNT2 ISPORT(A: IN INTEGERRANGE0TO3;CLK: INSTD_LOGIC;CLR: INSTD_LOGIC;EN: INSTD_LOGIC;LD: INSTD_LOGIC;圖例 5四位二進(jìn)制計數(shù)器實體Cout: OUTINTEGER RANGE

11、 0 TO 3);END COUNT2;ARCHITECTURE COUNT2_arc OF COUNT2 ISSIGNALSIG: INTEGER RANGE 0 TO 3;BEGINPROCESS (CLK, CLR)BEGINIF CLR = 0 THENSIG = 0;ELSIF (CLKEVENT AND CLK = 1) THENIF LD = 1 THENSIG = A;ELSEIF EN = 1 THENSIG = SIG + 1;ELSESIG = SIG;END IF;END IF;END IF;END PROCESS;Cout = SIG;END COUNT2_arc例

12、6：設(shè)計一個存儲容量為288的 RAM。CS為 RAM的片選信號， WR為 RAM的寫信號， RD為 RAM讀信號， ADR：八位地址信號， Din ：八位數(shù)據(jù)輸入線， Dout 為八位數(shù)據(jù)輸出線。library IEEE;use IEEE.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity RAM isport (WR: in STD_LOGIC;RD:in STD_LOGIC;ADR:in STD_LOGIC_VECTOR (7 downto 0);CS:in STD_LOGIC;Din:in STD_LOGIC_VECTOR

13、 (7 downto 0);Dout:圖例6RAM實體out STD_LOGIC_VECTOR (7 downto 0);end RAM;architecture RAM_arch of RAM issubtype word is std_logic_vector(7 downto 0);type memory is array (0 to 15)of word;signal adr_in:integer range 0 to 15;signal sram:memory;beginadr_in=conv_integer(ADR);process(wr)beginif(wrevent and w

14、r=1)thenif(cs=1and wr=1)thensram(adr_in)=din after 2 ns;end if;end if;end process;process(rd,cs)beginif(rd=0and cs=1)thendout=sram(adr_in)after 3 ns;elsedoutnext_state=yellow;red_light=0;green_light=1;yellow_lightred_light=1;green_light=0;yellow_light=0;if(sensor=1)thennext_state=green;elsenext_stat

15、ered_light=0;green_light=0;yellow_light=1;next_state=red;end case;end process;processbeginwait until clockevent and clock=1;present_state=next_state;end process;end abc;該狀態(tài)機(jī)由兩個進(jìn)程描述， 第一計算下一個狀態(tài)邏輯， 第二個鎖存下一個狀態(tài)到當(dāng)前狀態(tài)。例 8：用 VHDL設(shè)計一家用告警系統(tǒng)的控制邏輯，告警系統(tǒng)有來自傳感器的三個輸入信號 smoke、door 、water 和準(zhǔn)備傳輸?shù)礁婢O(shè)備的三個輸出觸發(fā)信號fire_alar

16、m、burg_alarm 、water_alarm 以及使能信號 en 和 alarm_en 。VHDL程序描述如下：LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY alarm ISPORT(smoke,door,water:IN std_logic;en,alarm_en:IN std_logic;fire_alarm,burg_alarm:OUTstd_logic;water_alarm:OUTstd_logic);END alarm;圖例8家用告警系統(tǒng)的控制邏輯電路圖ARCHITECTURE alarm_arc OF alarm ISBEG

17、INPROCESS(smoke,door,water,en,alarm_en)BEGINIF (smoke=1) AND (en=0) THENfire_alarm =1;ELSEfire_alarm =0;END IF;IF (door=1) AND (en=burg_alarm =1;0) AND (alarm_en=0)THENELSEburg_alarm = END IF;0;IF (water=1) AND (en=0) THENwater_alarm =1;ELSEwater_alarm =0;END IF;END PROCESS;END alarm_arc;程序中用了三個分開的 I