eda整點報時時鐘設(shè)計

1、eda 技術(shù)應(yīng)用課程設(shè)計報告題目名稱：多功能數(shù)字鐘專業(yè)班級：姓名 ：學(xué)號 ：小組成員：指導(dǎo)教師：設(shè)計時間：15-12-01 15-12-25一、設(shè)計目的1. 使得更加了解 eda的應(yīng)用2. 熟悉 vhdl的編程。3. 對于編程語句的編輯與糾錯有較大的提升4. 提升對于設(shè)計方面的能力二、設(shè)計要求1. 數(shù)字鐘具有“時”、“分”、“秒”顯示功能，其中時功能為24 小時制。2. 數(shù)字鐘具有校時和校分功能。3. 數(shù)字鐘具有整點報時功能。三、設(shè)計方案通過分別作出秒模塊、 分鐘模塊、小時模塊、整點報時模塊，導(dǎo)入動態(tài)掃描模塊，再由其輸出到數(shù)碼管輸出。四、模塊設(shè)計1. 秒程序模塊有3輸入3輸出 reset 為異

2、步清零當(dāng)沒有信號時清零秒模塊的計數(shù) setmin 為校分 當(dāng)有信號時想分模塊進一位 daout_a 與 daout_b 為輸出的信號分別為秒的高位與低位 enmin 負(fù)責(zé)向下一個模塊進位 clk 為時鐘信號2. 分鐘程序模塊 3輸入 3 輸出 reset 為異步清零當(dāng)沒有信號時清零分模塊的計數(shù) sethour 為校分 當(dāng)有信號時向時模塊進一位 daout_ma 分 daout_mb 為輸出的信號分別為分的高位與低位 enhour 負(fù)責(zé)向下一個模塊進位 clk 為時鐘信號3. 小時程序模塊有2輸入 2輸出 reset 為異步清零當(dāng)沒有信號時清零時模塊的計數(shù)clk 為時鐘信號 daout_ha d

3、aout_hb 為輸出的信號分別為時的高位與低位4. 動態(tài)掃描模塊 有八個輸入端，兩個輸出端 reset 為異步清零當(dāng)沒有信號時清零時模塊的計數(shù) daout 為高位5. 七段譯碼管模塊 有1輸入 8輸出 s 為用來接收秒分時模塊輸出的信號 ah 為轉(zhuǎn)化后的信號用來接數(shù)碼管6. 整點報時模塊有5輸入2輸出 clkspk 為時鐘信號 miao_h miao_l fen_h fen_h為從秒模塊時模塊接收的信號 speak 接蜂鳴器， lamp 接 led作為報時時的閃爍燈五、模塊程序1. 秒模塊設(shè)計（ 60 計時制）library ieee;use ieee.std_logic_1164.all;

4、use ieee.std_logic_unsigned.all;entity shijian isport(reset,clk,setmin:in std_logic;daout_a:out std_logic_vector(7 downto 4);輸出高位daout_adaout_b:out std_logic_vector(3 downto 0);輸出低位daou_benmin:out std_logic); enmin 是向分位進位信號end shijian;architecture behav of shijian issignal count:std_logic_vector(3 d

5、ownto 0); signal counter:std_logic_vector(3 downto 0);signal carry_out1:std_logic;signal carry_out2:std_logic;beginp1:process(reset,clk)begin 59 秒時的進位信號if reset='0'then 59 秒時的進位信號count<="0000"counter<="0000"若 reset為 0 時，則高、低位異步清零elsif(clk'event and clk='1

6、9;)then否則 clk 為上升沿時if(counter<5)thenif(count=9)thencount<="0000"counter<=counter+1;elsecount<=count+1;end if;carry_out1<='0'若高位counter<5, 低位 count=9 ，則低位清零，高位進一，否則低位進一， 59 秒時的進位信號carry_out1為 0。elseif(count=9)thencount<="0000"counter<="0000&quo

7、t;carry_out1<='1'若高位counter 為 5 時，低位 count=9 ，則高、低位清零，59 秒時的進位信號carry_out1進位為 1。elsecount<=count+1;carry_out1<='0'低位 count 加 1，59 秒時的進位信號carry_out1為 0end if;end if;end if;end process;daout_a(7 downto 4)<=counter;高位賦予daout_adaout_b(3 downto 0)<=count;低位賦予daout_benmin<

8、;=carry_out1 or setmin;程序 59 秒的進位信號或手動給 enmin 進位end behav;2. 分鐘模塊設(shè)計（ 60 制計時） library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fen is port(reset,clk,sethour:in std_logic;daout_ma:out std_logic_vector(7 downto 4);輸出高位信號daout_madaout_mb:out std_logic_vector(3 downto 0);

9、輸出低位信號daout_mbenhour:out std_logic); enhour 向時位進位信號end fen;architecture behav of fen issignal count:std_logic_vector(3 downto 0); signal counter:std_logic_vector(3 downto 0);signal carry_out1:std_logic 59 分的進位信號 carry_out1 signal carry_out2:std_logic; begin p1:process(reset,clk)beginif reset='0&

10、#39;then count<="0000"counter<="0000"若 reset 為 0 時，則高、低位異步清零elsif(clk'event and clk='1')then否則 clk 為上升沿時if(counter<5)thenif(count=9)thencount<="0000"counter<=counter+1;elsecount<=count+1;end if;carry_out1<='0'若高位 counter<5, 低位

11、 count=9 ，則低位清零，高位進 1，否則低位進 1，59 分時的進位信號 carry_out1 為 0 elseif(count=9)thencount<="0000"counter<="0000"carry_out1<='1'若高位counter 為 5 時，低位 count=9 ，則高、低位清零，59 分時的進位信號carry_out1進位為 1。elsecount<=count+1;carry_out1<='0'低位 count 加 1，59 分時的進位信號carry_out1為

12、 0。end if;end if;end if;end process;p2:process(reset,clk)beginif(clk'event and clk='0')then若 clk 為下降沿時if(counter=0)thenif(count=0)thencarry_out2<='0'若高位counter 為零，低位為零，則59 分時的進位信號carry_out2為 0end if;elsecarry_out2<='1' 否則進位為 1 end if;end if;end process;daout_ma(7 do

13、wnto 4)<=counter;高位賦予daout_madaout_mb(3 downto 0)<=count;低位賦予daout_mbenhour<=(carry_out1 and carry_out2)or sethour;程序兩個59 分的進位信號或手動給enmin 進位end behav;3. 小時模塊設(shè)計（ 24 小時制） library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity xiaoshi is port(reset,clk:in std_logic;d

14、aout_ha:out std_logic_vector(7 downto 4); 輸出高位 daout_hadaout_hb:out std_logic_vector(3 downto 0); 輸出地位 daout_hbend xiaoshi;architecture behav of xiaoshi issignal count:std_logic_vector(3 downto 0); signal counter:std_logic_vector(3 downto 0); beginp1:process(reset,clk) beginif reset='0'then

15、count<="0000"counter<="0000"若 reset 為 0 時，則高、低位異步清零if(counter<2)thenelsif(clk'event and clk='1')then否則 clk 上升沿來到時if(counter<2)thenif(count=9)thencount<="0000"counter<=counter+1;elsecount<=count+1;若高位counter<2, 低位 count=9 ，則低位清零，高位進 1，

16、否則低位進1。end if;elseif(count=3)thencount<="0000"counter<="0000"elsecount<=count+1;若高位counter=2, 低位count=3 ，則高、低位清零，否則低位進一。end if;end if;end if;end process;daout_ha(7 downto 4)<=counter;高位賦予daout_hadaout_hb(3 downto 0)<=count;地位賦予daout_hbend behav;4. 動態(tài)掃描模塊設(shè)計 library

17、ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity seltime isport(ckdsp:in std_logic; reset:in std_logic;shijian_s:in std_logic_vector(7 downto 4);秒模塊高位模塊輸入shijian_g:in std_logic_vector(3 downto 0);秒模塊低位模塊輸入fen_s:in std_logic_vector(7 downto 4);fen_g:in std_logic_vector(3 down

18、to 0); xiaoshi_s:in std_logic_vector(7 downto 4); xiaoshi_g:in std_logic_vector(3 downto 0); daout:out std_logic_vector(3 downto 0); sel:out std_logic_vector(2 downto 0);end seltime;architecture behav of seltime issignal sec:std_logic_vector(2 downto 0);beginprocess(reset,ckdsp)beginif(reset='0&

19、#39;)thensec<="000"elsif(ckdsp'event and ckdsp='1')thenif(sec="101")thensec<="000"elsesec<=sec+1;end if;end if;end process;process(sec,shijian_g,shijian_s,fen_g,fen_s,xiaoshi_g,xiaoshi_s)begincase sec iswhen"000"=>daout<=shijian_g(3

20、downto 0); when"001"=>daout<=shijian_s(7 downto 4); when"010"=>daout<=fen_g(3 downto 0); when"011"=>daout<=fen_s(7 downto 4); when"100"=>daout<=xiaoshi_g(3 downto 0); when"101"=>daout<=xiaoshi_s(7 downto 4); when others=

21、>daout<="xxxx" end case;end process;sel<=sec;end behav;5. 整點報時模式 library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity alert isport(clkspk:in std_logic;時鐘信號shijian_s:in std_logic_vector(7 downto 4);shijian_g:in std_logic_vector(3 downto 0);fen_s:in std_

22、logic_vector(7 downto 4);fen_g:in std_logic_vector(3 downto 0);speak:out std_logic;輸出 speaklamp:out std_logic_vector(8 downto 0);輸出 lampend alert;architecture behav of alert issignal divclkspk2:std_logic;beginp1:process(clkspk)beginif(clkspk'event and clkspk='1')then當(dāng) clkspk為上升沿時divclksp

23、k2<=not divclkspk2; divclkspk2 的非賦予 divclkspk2 end if;end process;p2:process(shijian_s,shijian_g,fen_s,fen_g) beginif(fen_g="1001"andfen_s="0101"andshijian_s="0101")then若時間是59 分 50 秒時case shijian_g is隔一秒響一次when"0001"=>lamp<="000000001"speak&

24、lt;=divclkspk2;when"0010"=>lamp<="000000010"speak<='0'when"0011"=>lamp<="000000100"speak<=divclkspk2;when"0100"=>lamp<="000001000"speak<='0'when"0101"=>lamp<="000010000"sp

25、eak<=divclkspk2;when"0110"=>lamp<="000100000"speak<='0'when"0111"=>lamp<="001000000"speak<=divclkspk2;when"1000"=>lamp<="010000000"speak<='0'when"1001"=>lamp<="100000000&quo

26、t;speak<=clkspk;當(dāng) 59 秒信號給 lamp，時鐘信號給speak，準(zhǔn)備整點報時when others=>lamp<="000000000"當(dāng)秒為其他值時無效end case;end if;end process;end behav;6.7 段譯碼顯示模塊設(shè)計library ieee;use ieee.std_logic_1164.all;entity deled isport(s:in std_logic_vector(3 downto 0);a,b,c,d,e,f,g,h:out std_logic);end deled;archite

27、cture behav of deled issignal data:std_logic_vector(3 downto 0);signal dout:std_logic_vector(7 downto 0);begindata<=s; s 賦值給 dataprocess(data)begincase data iswhen"0000"=>dout<="00111111"當(dāng) data 是 0000時將 00111111賦給 doutwhen"0001"=>dout<="00000110"

28、;when"0010"=>dout<="01011011"when"0011"=>dout<="01001111"when"0100"=>dout<="01100110"when"0101"=>dout<="01101101"when"0110"=>dout<="01111101"when"0111"=>dout

29、<="00000111"when"1000"=>dout<="01111111"when"1001"=>dout<="01101111"when"1010"=>dout<="01110111"when"1011"=>dout<="01111100"when"1100"=>dout<="00111001"when"1101"=>dout<="01011110"when"1110"=>dout<="01111001"when"1111"=>dout<="01110001"when others=>dout<="00000000"當(dāng) data 為其他值時，將 00000000賦給