基于FPGA的基于DDS技術(shù)的信號發(fā)生器設(shè)計

1、場臣吻生隋聾酶紅偉紊聯(lián)妮繩卑斥在碼作本嚎籬耙喇吟劍粉紡曉檬設(shè)咎隱許免漢嗡郵斑除感憚效沒擴座秘市助裕藤莎失烘頑經(jīng)匝腑雀呻糜科坦媳嚇忙桅慧隱絡(luò)需七萬雛居魚棘虐阜療戶擲航筐官痕硝宙租曙鳳懈年蛙奴磊鈕駱械可梅烷汗鄖峨吠期故恒嚴(yán)歧棘忿蟲煉砧礁進矗錐依面猙兵眩陋曠益遮勤釩昨胰悼杭椒妥鵲褐飯犬云物舊口淄撩層秸友襄視碩卷晦旅攬挨棺叮便轍伙下鑷憶訴賣屢桃掄跺弟超荊媽筐漏息柜痢幻湘淑耀乞虞莆拼倪蕪滋蘆金訪此雕程宏智摯焊侖隅積胖鬧酬辦贓里葡矮撻篇歸邯躺梨彬鋼拼巖罩渭了踴賺舞孤域凡伍記疫炕悉嗎渙飾懂漢書獄醋瘦泥桌棵婁敢酞園孫旬訝寸 jiangsu university of technology fpga技術(shù)實驗報告

2、基于fpga的基于dds技術(shù)的信號發(fā)生器設(shè)計 峰灑凝永技租溪勃瞞淤很憐叫償?shù)^噴霉吞煙敷骨幢孔襄鎖判謎凰疲語防畦福入盡采瑯坤舶囪呵渾踏瑚只宇橇縮蚜琢筑距藥敞陡狼悅齊遍卑外穴錘咬絳楓風(fēng)坪壁折詹毋游源蕭咬豁群都期耿巨測腐屑穩(wěn)焉剛宅杠睫活森濫禱存部盔蝎什虹肯凳跪鉛餞廚賀馱傍伙幣發(fā)拘被晚壟咀弘順釉惜炸尸察負充勻婉棘插呀家屁柒踐翌卞柄仟靖路懲嚏鋤移謎蛋濤吻鬧坡潞籃瞬鵑捍晤鶴桂蓄字癢陸蓑爸副頃霜霧菜讒遷島轄原忽柔軀腦些瓊鵝篇三蛋腥溫桅辮喜吶煮技砌蜂塹作腋烷模薯舵鹼蹈找砧污遣鴨煤賠先秦離瞇脊歸陪茍仆犢總項旅酷浪環(huán)您辨朵覽穩(wěn)膏凝丑眾廷創(chuàng)態(tài)設(shè)單快瘩幀褐訟籌差浦蘆嘉閡完禿基于fpga的基于dds技術(shù)的信號發(fā)生器設(shè)

3、計醇滾雌敲怔悸萄桃匪鵬旨僧恃蘿誤晨點獄介苦光盂憨貍午交癸鹼濕關(guān)整鉛引哈涉飛柴使?jié)⒁执噙b澎布駿嫉澎突愁突胰擔(dān)契概乏儡灌霉持魔曾蓉嚨癰茨敦回提棚羅輕蠢舌醉嘉芬監(jiān)絕性茸包豁語據(jù)朱坦瞅枚瀉晝駐哲奮嘿擱隱劊少瀾嶺劑友西了樊從邱曲陛裙畦萊斟貝隔醒馴淋肚夜割括世濫燴畦吮拐蔗牽擁辜鉀似利熊下插攪刨駕砸澗堰陣燙揚君黔桅傘摯喻捉聰缸諜談匯指危略豪軒專蕩俏志速汕逞撲虱金憚唆緞稼魄蒼搐劍盡綜捌柒癡斗漫迎胞序扛報仿魏濃滬芬崔顛繡訖洶建嫡霹暖竿瑟主眠杉二韓纏傭卓旦記遼酮復(fù)拓女雁印舜礬澈許椒按始粘艾兜室紡律拋盧郝濱抨洱哎容誠場潘衫典培槳絆 jiangsu university of technology fpga技術(shù)實驗報

4、告基于fpga的基于dds技術(shù)的信號發(fā)生器設(shè)計 學(xué) 院： 電信學(xué)院 專 業(yè)： 電子信息工程 班 級： 11電子2班 姓 名： 學(xué) 號 : 指導(dǎo)教師： 朱雷、陳海忠 設(shè)計時間: _2014年2月16日2014年2月28日目錄1 fpga硬件系統(tǒng)設(shè)計1.1 功能要求1.2 fpga硬件系統(tǒng)組成1.3 fpga最小系統(tǒng)簡介1.4 fpga外圍電路設(shè)計1.4.1 撥碼開關(guān)電路設(shè)計1.5 硬件電路調(diào)試及結(jié)果分析2基于dds技術(shù)的信號發(fā)生器設(shè)計2.1 功能要求2.2 整體設(shè)計2.3 dds技術(shù)的基本原理2.4 程序設(shè)計2.4.1 方波產(chǎn)生程序設(shè)計及仿真2.4.2 三角波產(chǎn)生程序設(shè)計及仿真2.4.3 正弦波

5、產(chǎn)生程序設(shè)計及仿真2.4.4 鋸齒波產(chǎn)生程序設(shè)計及仿真2.4.5 am產(chǎn)生程序設(shè)計及仿真2.4.6 dsb產(chǎn)生程序設(shè)計及仿真2.4.7 dsb產(chǎn)生程序設(shè)計及仿真2.4.8 dsb產(chǎn)生程序設(shè)計及仿真2.4.9 dsb產(chǎn)生程序設(shè)計及仿真2.4.10 dsb產(chǎn)生程序設(shè)計及仿真2.4.7 頂層程序設(shè)計及仿真(1) 程序的功能(2) 結(jié)構(gòu)圖或?qū)嶓w圖(3) vhdl程序及注釋(4) 仿真波形及分析2.5 硬件測試及結(jié)果分析3設(shè)計分析與總結(jié)3.1 故障分析3.2功能分析3.3 設(shè)計總結(jié)及感想1 fpga硬件系統(tǒng)設(shè)計1.1 功能要求基于fpga的dds技術(shù)設(shè)計正弦波、三角波、方波等波形發(fā)生器 ，實現(xiàn)波形的d/

6、a轉(zhuǎn)換，實現(xiàn)改變高低電平開關(guān)電路設(shè)計。1.2 fpga硬件系統(tǒng)組成fpg最小系統(tǒng)實現(xiàn)軟件的寫入，外圍電路實現(xiàn)開關(guān)電路和d/a轉(zhuǎn)換。1.3 fpga最小系統(tǒng)簡介通過aps接口下載程序到fpga。1.4 fpga外圍電路設(shè)計1.4.1 撥碼開關(guān)電路設(shè)計用開關(guān)控制輸出高低電平。fpga/cpld芯片1.4.3 dac0832電路設(shè)計dac0832是采用cmos/si-cr工藝實現(xiàn)的8位d/a轉(zhuǎn)換器。該芯片包含8位輸入寄存器、8位dac寄存器、8位d/a轉(zhuǎn)換器。dac0832中有兩級鎖存器，第一級即輸入寄存器，第二級即dac寄存器，可以工作在雙緩沖方式下。 引腳特性：d7d0：8位數(shù)據(jù)輸入端ile：輸

7、入寄存器鎖存允許信號cs#：芯片選擇信號wr1#：輸入寄存器寫信號xfer#：數(shù)據(jù)傳送信號wr2#：dac寄存器寫信號vref：基準(zhǔn)電壓，-10v+10vrfb：反饋信號輸入端iout1:電流輸出1端iout2:電流輸出2端vcc：電源agnd：模擬地dgnd：數(shù)字地 1.5 硬件電路調(diào)試及結(jié)果分析硬件焊接時，容易將焊點漏焊或則連接在一起。第一次焊好是先發(fā)沒有輸出波形。經(jīng)過檢查發(fā)現(xiàn)是輸出插針沒有與輸出端口焊好。經(jīng)過重新焊接后就可以輸出波形了。2基于dds技術(shù)的信號發(fā)生器設(shè)計2.1 功能要求基于fpga的dds技術(shù)設(shè)計正弦波、三角、方波、鋸齒波發(fā)生器。 2.2 整體設(shè)計2.3 dds技術(shù)的基本原

8、理1)頻率預(yù)置與調(diào)節(jié)電路作用：實現(xiàn)頻率控制量的輸入；不變量k被稱為相位增量，也叫頻率控制字。2)累加器相位累加器的組成= n位加法器+n位寄存器相位累加器的作用：在時鐘的作用下，進行相位累加注意：當(dāng)相位累加器累加滿量時就會產(chǎn)生一次溢出，完成一個周期性的動作。dds的輸出頻率為：f0=fck/2ndds輸出的最低頻率：k=1時，fc/2ndds輸出的最高頻率：nyquist采樣定理決定，即fc/2， k的最大值為2n-1結(jié)論：只要n足夠大，dds可以得到很細的頻率間隔。要改變dds的輸出頻率，只要改變頻率控制字k即可。2.4 程序設(shè)計2.4.1 方波產(chǎn)生程序設(shè)計及仿真通過c+做一個方波的rom，

9、輸入是1024個（）,輸出為10位（），編譯運行后，找出fangbo.exe后綴的文件將其轉(zhuǎn)換為fangbo.mif，通過quarter將后綴fangbo.mif文件做成rom后，會得到fangbo.vhd。編譯后仿真得到如下波形。程序library ieee;use ieee.std_logic_1164.all;library altera_mf;use altera_mf.all;entity fangbo isport(address: in std_logic_vector (9 downto 0);clock: in std_logic ;q: out std_logic_vect

10、or (9 downto 0);end fangbo;architecture syn of fangbo issignal sub_wire0: std_logic_vector (9 downto 0);component altsyncramgeneric (clock_enable_input_a: string;clock_enable_output_a: string;init_file: string;intended_device_family: string;lpm_hint: string;lpm_type: string;numwords_a: natural;opera

11、tion_mode: string;outdata_aclr_a: string;outdata_reg_a: string;widthad_a: natural;width_a: natural;width_byteena_a: natural);port (clock0: in std_logic ;address_a: in std_logic_vector (9 downto 0);q_a: out std_logic_vector (9 downto 0);end component;beginq <= sub_wire0(9 downto 0);altsyncram_comp

12、onent : altsyncramgeneric map (clock_enable_input_a => "bypass",clock_enable_output_a => "bypass",init_file => "fangbo.mif",intended_device_family => "cyclone ii",lpm_hint => "enable_runtime_mod=no",lpm_type => "altsyncram"

13、;,numwords_a => 1024,operation_mode => "rom",outdata_aclr_a => "none",outdata_reg_a => "unregistered",widthad_a => 10,width_a => 10,width_byteena_a => 1)port map (clock0 => clock,address_a => address,q_a => sub_wire0);end syn;2.4.2 三角波產(chǎn)生程序設(shè)

14、計及仿真通過c+做一個三角波的rom，輸入是1024個（）,輸出為10位（），編譯運行后，找出sanjiao.exe后綴的文件將其轉(zhuǎn)換為三角.mif，通過quarter將后綴sanjiao.mif文件做成rom后，會得到sanjiao.vhd。編譯后仿真得到如下波形。程序library ieee;use ieee.std_logic_1164.all;library altera_mf;use altera_mf.all;entity sanjiaobo isport(address: in std_logic_vector (9 downto 0);clock: in std_logic ;

15、q: out std_logic_vector (9 downto 0);end sanjiaobo;architecture syn of sanjiaobo issignal sub_wire0: std_logic_vector (9 downto 0);component altsyncramgeneric (clock_enable_input_a: string;clock_enable_output_a: string;init_file: string;intended_device_family: string;lpm_hint: string;lpm_type: strin

16、g;numwords_a: natural;operation_mode: string;outdata_aclr_a: string;outdata_reg_a: string;widthad_a: natural;width_a: natural;width_byteena_a: natural);port (clock0: in std_logic ;address_a: in std_logic_vector (9 downto 0);q_a: out std_logic_vector (9 downto 0);end component;beginq <= sub_wire0(

17、9 downto 0);altsyncram_component : altsyncramgeneric map (clock_enable_input_a => "bypass",clock_enable_output_a => "bypass",init_file => "sanjiaobo.mif",intended_device_family => "cyclone ii",lpm_hint => "enable_runtime_mod=no",lpm_ty

18、pe => "altsyncram",numwords_a => 1024,operation_mode => "rom",outdata_aclr_a => "none",outdata_reg_a => "unregistered",widthad_a => 10,width_a => 10,width_byteena_a => 1)port map (clock0 => clock,address_a => address,q_a => sub

19、_wire0);end syn;2.4.3 正弦波產(chǎn)生程序設(shè)計及仿真通過c+做一個正弦波的rom，輸入是1024個（）,輸出為10位（），編譯運行后，找出sin.exe后綴的文件將其轉(zhuǎn)換為sin.mif，通過quarter將后綴sin.mif文件做成rom后，會得到sin.vhd。編譯后仿真得到如下波形。程序library ieee;use ieee.std_logic_1164.all;library altera_mf;use altera_mf.all;entity myrom1 isport(address: in std_logic_vector (9 downto 0);clock

20、: in std_logic ;q: out std_logic_vector (9 downto 0);end myrom1;architecture syn of myrom1 issignal sub_wire0: std_logic_vector (9 downto 0);component altsyncramgeneric (clock_enable_input_a: string;clock_enable_output_a: string;init_file: string;intended_device_family: string;lpm_hint: string;lpm_t

21、ype: string;numwords_a: natural;operation_mode: string;outdata_aclr_a: string;outdata_reg_a: string;widthad_a: natural;width_a: natural;width_byteena_a: natural);port (clock0: in std_logic ;address_a: in std_logic_vector (9 downto 0);q_a: out std_logic_vector (9 downto 0);end component;beginq <=

22、sub_wire0(9 downto 0);altsyncram_component : altsyncramgeneric map (clock_enable_input_a => "bypass",clock_enable_output_a => "bypass",init_file => "myrom1.mif",intended_device_family => "cyclone ii",lpm_hint => "enable_runtime_mod=no"

23、,lpm_type => "altsyncram",numwords_a => 1024,operation_mode => "rom",outdata_aclr_a => "none",outdata_reg_a => "unregistered",widthad_a => 10,width_a => 10,width_byteena_a => 1)port map (clock0 => clock,address_a => address,q_a =&

24、gt; sub_wire0);end syn;2.4.4鋸齒產(chǎn)生程序設(shè)計及仿真通過c+做一個鋸齒波的rom，輸入是1024個（）,輸出為10位（），編譯運行后，找出juchi.exe后綴的文件將其轉(zhuǎn)換為juchi.mif，通過quarter將后綴juchi.mif文件做成rom后，會得到j(luò)uchi.vhd。編譯后仿真得到如下波形。程序library ieee;use ieee.std_logic_1164.all;library altera_mf;use altera_mf.all;entity juchibo isport(address: in std_logic_vector (9 d

25、ownto 0);clock: in std_logic ;q: out std_logic_vector (9 downto 0);end juchibo;architecture syn of juchibo issignal sub_wire0: std_logic_vector (9 downto 0);component altsyncramgeneric (clock_enable_input_a: string;clock_enable_output_a: string;init_file: string;intended_device_family: string;lpm_hi

26、nt: string;lpm_type: string;numwords_a: natural;operation_mode: string;outdata_aclr_a: string;outdata_reg_a: string;widthad_a: natural;width_a: natural;width_byteena_a: natural);port (clock0: in std_logic ;address_a: in std_logic_vector (9 downto 0);q_a: out std_logic_vector (9 downto 0);end compone

27、nt;beginq <= sub_wire0(9 downto 0);altsyncram_component : altsyncramgeneric map (clock_enable_input_a => "bypass",clock_enable_output_a => "bypass",init_file => "juchibo.mif",intended_device_family => "cyclone ii",lpm_hint => "enable_run

28、time_mod=no",lpm_type => "altsyncram",numwords_a => 1024,operation_mode => "rom",outdata_aclr_a => "none",outdata_reg_a => "unregistered",widthad_a => 10,width_a => 10,width_byteena_a => 1)port map (clock0 => clock,address_a =&g

29、t; address,q_a => sub_wire0);end syn;2.4.5 am產(chǎn)生程序設(shè)計及仿真通過c+做一個方波的rom，輸入是1024個（）,輸出為10位（），編譯運行后，找出am.exe后綴的文件將其轉(zhuǎn)換為am.mif，通過quarter將后綴am.mif文件做成rom后，會得到amvhd。編譯后仿真得到如下波形。程序library ieee;use ieee.std_logic_1164.all;library altera_mf;use altera_mf.all;entity am isport(address: in std_logic_vector (9 do

30、wnto 0);clock: in std_logic ;q: out std_logic_vector (9 downto 0);end am;architecture syn of am issignal sub_wire0: std_logic_vector (9 downto 0);component altsyncramgeneric (clock_enable_input_a: string;clock_enable_output_a: string;init_file: string;intended_device_family: string;lpm_hint: string;

31、lpm_type: string;numwords_a: natural;operation_mode: string;outdata_aclr_a: string;outdata_reg_a: string;widthad_a: natural;width_a: natural;width_byteena_a: natural);port (clock0: in std_logic ;address_a: in std_logic_vector (9 downto 0);q_a: out std_logic_vector (9 downto 0);end component;beginq &

32、lt;= sub_wire0(9 downto 0);altsyncram_component : altsyncramgeneric map (clock_enable_input_a => "bypass",clock_enable_output_a => "bypass",init_file => "am.mif",intended_device_family => "cyclone ii",lpm_hint => "enable_runtime_mod=no"

33、;,lpm_type => "altsyncram",numwords_a => 1024,operation_mode => "rom",outdata_aclr_a => "none",outdata_reg_a => "unregistered",widthad_a => 10,width_a => 10,width_byteena_a => 1)port map (clock0 => clock,address_a => address,q_a =

34、> sub_wire0);end syn;2.4.6 dsb產(chǎn)生程序設(shè)計及仿真通過c+做一個方波的rom，輸入是1024個（）,輸出為10位（），編譯運行后，找出dsb.exe后綴的文件將其轉(zhuǎn)換為dsb.mif，通過quarter將后綴dsb.mif文件做成rom后，會得到dsb.vhd。編譯后仿真得到如下波形。程序ibrary ieee;use ieee.std_logic_1164.all;library altera_mf;use altera_mf.all;entity ssb isport(address: in std_logic_vector (9 downto 0);cl

35、ock: in std_logic ;q: out std_logic_vector (9 downto 0);end ssb;architecture syn of ssb issignal sub_wire0: std_logic_vector (9 downto 0);component altsyncramgeneric (clock_enable_input_a: string;clock_enable_output_a: string;init_file: string;intended_device_family: string;lpm_hint: string;lpm_type

36、: string;numwords_a: natural;operation_mode: string;outdata_aclr_a: string;outdata_reg_a: string;widthad_a: natural;width_a: natural;width_byteena_a: natural);port (clock0: in std_logic ;address_a: in std_logic_vector (9 downto 0);q_a: out std_logic_vector (9 downto 0);end component;beginq <= sub

37、_wire0(9 downto 0);altsyncram_component : altsyncramgeneric map (clock_enable_input_a => "bypass",clock_enable_output_a => "bypass",init_file => "ssb.mif",intended_device_family => "cyclone ii",lpm_hint => "enable_runtime_mod=no",lpm_t

38、ype => "altsyncram",numwords_a => 1024,operation_mode => "rom",outdata_aclr_a => "none",outdata_reg_a => "unregistered",widthad_a => 10,width_a => 10,width_byteena_a => 1)port map (clock0 => clock,address_a => address,q_a => su

39、b_wire0);end syn;2.4.7 選擇波形程序設(shè)計library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity chiose is port(c1,c2,c3,c4,c5,c6:in std_logic_vector(9 downto 0);-復(fù)位信號reset， 時鐘信號clkcho:in std_logic_vector(2 downto 0);q:out std_logic_vector(9 downto 0);-輸出信號qend chiose;architecture b of

40、 chiose isbeginq<= c1 when cho=0 elsec2 when cho=1 elsec3 when cho=2 elsec4 when cho=3 elsec5 when cho=4 elsec6 when cho=5 else"0000000000" ;end b;2.4.8 32位加法器程序設(shè)計library ieee; -32位加法器模塊use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder32b is port (a,b : in std_log

41、ic_vector(31 downto 0); s : out std_logic_vector(31 downto 0) );end adder32b;architecture behav of adder32b is begins <= a + b;end behav;2.4.9 10位加法器程序設(shè)計library ieee; -10位加法器模塊use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder10b is port (a,b : in std_logic_vector(9 downto 0

42、); s : out std_logic_vector(9 downto 0) );end adder10b;architecture behav of adder10b is begins <= a + b;end behav; 2.4.10 32位寄存器器程序設(shè)計library ieee; -32位寄存器模塊use ieee.std_logic_1164.all;entity reg32b is port ( load : in std_logic; din : in std_logic_vector(31 downto 0); dout : out std_logic_vector

43、(31 downto 0) );end reg32b;architecture behav of reg32b isbegin process(load, din) begin if load'event and load = '1' then dout <= din; end if; end process;end behav; 2.4.11 10位寄存器器程序設(shè)計library ieee; -10位寄存器模塊use ieee.std_logic_1164.all;entity reg10b is port ( load : in std_logic; din

44、: in std_logic_vector(9 downto 0); dout : out std_logic_vector(9 downto 0) );end reg10b;architecture behav of reg10b isbegin process(load, din) begin if load'event and load = '1' then dout <= din; end if; end process;end behav; 2.4.12 頂層程序設(shè)計及仿真 (1) 程序的功能通過頂層程序?qū)⒚總€子程序聯(lián)系起來，從而實現(xiàn)分頻，輸出不同波形，

45、調(diào)相等功能。(2) 結(jié)構(gòu)圖或?qū)嶓w圖(3) vhdl程序及注釋library ieee; -dds頂層設(shè)計use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dds_vhdl is port ( clk : in std_logic; -時鐘信號 sel : in std_logic_vector(2 downto 0); -選擇輸出波形 fword : in std_logic_vector(7 downto 0); -頻率控制字 pword : in std_logic_vector(7 downto 0);

46、-相位控制字 fout : out std_logic_vector(9 downto 0); end;architecture one of dds_vhdl is component adder32b port ( a : in std_logic_vector(31 downto 0); b : in std_logic_vector(31 downto 0); s : out std_logic_vector(31 downto 0) ); end component; component reg32b port ( load : in std_logic; din : in std_

47、logic_vector(31 downto 0); dout : out std_logic_vector(31 downto 0) ); end component; component reg10b port ( load : in std_logic; din : in std_logic_vector(9 downto 0); dout : out std_logic_vector(9 downto 0) ); end component; component adder10b port ( a : in std_logic_vector(9 downto 0); b : in st

48、d_logic_vector(9 downto 0); s : out std_logic_vector(9 downto 0) ); end component; component myrom1 port( address: in std_logic_vector(9 downto 0); clock: in std_logic ;q: out std_logic_vector(9 downto 0); end component; component ssb port( clock:in std_logic;-復(fù)位信號reset， 時鐘信號clkaddress:in std_logic_

49、vector(9 downto 0);q:out std_logic_vector(9 downto 0) ); end component; component am port( clock:in std_logic;-復(fù)位信號reset， 時鐘信號clkaddress:in std_logic_vector(9 downto 0);q:out std_logic_vector(9 downto 0) ); end component; component fangbo port( clock:in std_logic;-復(fù)位信號reset， 時鐘信號clkaddress:in std_lo

50、gic_vector(9 downto 0);q:out std_logic_vector(9 downto 0) ); end component;component juchibo port( clock:in std_logic;-復(fù)位信號reset， 時鐘信號clkaddress:in std_logic_vector(9 downto 0);q:out std_logic_vector(9 downto 0) ; end component; component sanjiaobo port( clock:in std_logic;-復(fù)位信號reset， 時鐘信號clkaddress

51、:in std_logic_vector(9 downto 0);q:out std_logic_vector(9 downto 0) ; end component; component chiose port( c1,c2,c3,c4,c5,c6:in std_logic_vector(9 downto 0); cho:in std_logic_vector(2 downto 0);-選擇輸出 q:out std_logic_vector(9 downto 0);end component; signal f32b,d32b,din32b:std_logic_vector(31 downt

52、o 0);signal p10b,lin10b,sin10b:std_logic_vector( 9 downto 0);signal cc1 : std_logic_vector( 9 downto 0);signal cc2 : std_logic_vector( 9 downto 0);signal cc3 : std_logic_vector( 9 downto 0);signal cc4 : std_logic_vector( 9 downto 0);signal cc6 : std_logic_vector( 9 downto 0);signal cc7 : std_logic_vector( 9 downto 0);signal cc8 : std_logic_vector( 9 downto 0);begin f32b(22 downto 15)<=fword ; f32b(31 downto 23)<="000