鍵盤掃描及計算器VHDL仿真

1、-作者xxxx-日期xxxx鍵盤掃描及計算器VHDL仿真【精品文檔】簡易計算器設(shè)計 EDA實驗報告 一、 實驗內(nèi)容實驗要求：完成個位數(shù)的加減乘運算，輸入用矩陣鍵盤，輸出用數(shù)碼管顯示，每輸入一次數(shù)據(jù)要顯示在數(shù)碼管上。矩陣鍵盤共16個按鍵，用其中10個做個位數(shù)的輸入，用3個分別做加減乘運算，用其中1個做等于操作，各位數(shù)的運算結(jié)果最多兩位，用動態(tài)掃描數(shù)碼管顯示運算結(jié)果。二、 小組成員三、 實現(xiàn)方法系統(tǒng)組成及連接原理如圖所示，主要由由七個功能模塊組成：分頻模塊（為鍵盤掃描模塊和防抖模塊提供時鐘）、鍵盤掃描驅(qū)動模塊（依次置零）、鍵盤按鍵值編碼模塊、鍵盤編碼值防抖模塊、運算模塊，數(shù)碼管顯示驅(qū)動模塊、動態(tài)掃

2、描驅(qū)動模塊。分頻鍵值編碼防抖鍵盤矩陣行驅(qū)動時鐘數(shù)碼管顯示運算數(shù)碼管動態(tài)顯示1.分頻模塊由于FPGA實驗板的原始時鐘頻率高達(dá)MHz，所以不能直接接入設(shè)計模塊中使用，就需要用到分頻模塊。將分頻到4KHz和10Hz來使用，一個用于行驅(qū)動掃描時鐘，一個用于防抖模塊。所以，采用寫一個可變分頻元件來調(diào)用。元件視圖：主要代碼如下（完整代碼見附錄，下同）：architecture RTL of freq_division iscomponent fredivn isgeneric(n:positive); Port ( clkin:in STD_LOGIC; clkout:out STD_LOGIC);end

3、 component;beginU1:fredivngeneric map(n=>3)port map(clkin=>clk,clkout=>clkout_kb);end RTL;仿真結(jié)果如下圖：達(dá)到預(yù)期的目的2.行驅(qū)動模塊（依次對行置零）：鍵盤掃描的原理就是檢測行列信號然后判斷出具體是按下了哪一個按鍵。所以，對行依次置零，當(dāng)置零頻率較快時，按下某一個按鍵后，一定能得到某一列的信號輸出為零，如下圖：當(dāng)行信號為1110時，若按下了0鍵，就會得到1110的列信號，立馬就快可以譯碼出按鍵值，若按下4鍵、8鍵、C鍵則都不會有輸出。主要代碼如下：process(clkin)begini

4、f clr='1' thencount<="00" elsif rising_edge(clkin) thenif count="11" thencount<="00"elsecount<=count+1;end if;end if;end process;process(count)beginif count="01" thenkeydrv<="1110"elsif count="10" thenkeydrv<="11

5、01"elsif count="11" then keydrv<="1011" elsif count="00" thenkeydrv<="0111"end if;end process;仿真結(jié)果如下圖：達(dá)到預(yù)期的目的3.鍵值編碼模塊依據(jù)行驅(qū)動模塊，當(dāng)按下某一個按鍵后，立馬可以根據(jù)行列和并位信號得到唯一的鍵盤編碼值，用5位矢量來保存結(jié)果，當(dāng)沒有按鍵按下時，編碼值一直保持著11111不變，并在后端的模塊中不對其做任何處理。以下列出部分編碼表（完整編碼表見附錄）：十進(jìn)制數(shù)行&列HEX七段碼

6、HEX011101110EE11111107E411011110DE011001133511011101DD10110115B主要代碼如下：process(clk)beginif clr='0' thenif rising_edge(clk) thenif temp1="11101110" thenkeyvalue1<="00000" -0elsif temp1="11101101" thenkeyvalue1<="00001" -1elsif temp1="11101011&

7、quot; thenkeyvalue1<="00010" -2elsif temp1="11100111" thenkeyvalue1<="00011" -3elsif temp1="11011110" thenkeyvalue1<="00100" -4elsif temp1="11011101" thenkeyvalue1<="00101" -5elsif temp1="11011011" thenkeyval

8、ue1<="00110" -6elsif temp1="11010111" thenkeyvalue1<="00111" -7elsif temp1="10111110" thenkeyvalue1<="01000" -8elsif temp1="10111101" thenkeyvalue1<="01001" -9elsif temp1="10111011" thenkeyvalue1<="01

9、010" -10elsif temp1="10110111" thenkeyvalue1<="01011" -11elsif temp1="01111110" thenkeyvalue1<="01100" -12elsif temp1="01111101" thenkeyvalue1<="01101" -13elsif temp1="01111011" thenkeyvalue1<="01110" -1

10、4elsif temp1="01110111" thenkeyvalue1<="01111" -15end if;end if;end if;end process;波形仿真如下圖：4.防抖模塊鍵盤按鍵物理模型如下：通常的按鍵所用開關(guān)為機械彈性開關(guān)，當(dāng)機械觸點斷開、閉合時，由于機械觸點的彈性作用，一個按鍵開關(guān)在閉合時不會馬上穩(wěn)定地接通，在斷開時也不會一下子斷開。因而在閉合及斷開的瞬間均伴隨有一連串的抖動，為了不產(chǎn)生這種現(xiàn)象而作的措施就是按鍵消抖。抖動時間的長短由按鍵的機械特性決定，一般為5ms10ms。一般來說，軟件消抖的方法是不斷檢測按鍵值，直到

11、按鍵值穩(wěn)定。實現(xiàn)方法：假設(shè)未按鍵時輸入1，按鍵后輸入為0，抖動時不定?？梢宰鲆韵聶z測：檢測到按鍵輸入為0之后，延時5ms10ms，再次檢測，如果按鍵還為0，那么就認(rèn)為有按鍵輸入。延時的5ms10ms恰好避開了抖動期。本模塊是采用多次采樣來達(dá)到防抖的，只有在給定的采樣次數(shù)內(nèi)，都保證采樣結(jié)果一致時才會輸出按鍵編碼值。主要代碼如下：case count iswhen "0000"=> test1<=temp;when "0001"=> test2<=temp;when "0010"=> test3<=te

12、mp;when "0011"=> test4<=temp;when "0100"=> test5<=temp;when "0101"=> test6<=temp;when "0110"=> test7<=temp;when "0111"=> test8<=temp;when "1000"=> test9<=temp;when "1001"=> test10<=temp;wh

13、en "1010"=> test11<=temp;when "1011"=> test12<=temp;when "1100"=> test13<=temp;when "1101"=> test14<=temp;when "1110"=> test15<=temp;when "1111"=> test16<=temp;when others=>null;end case;if test1=test5

14、 and test2=test6 and test3=test7 and test4=test8 and test5=test9 and test6=test10 and test7=test11 and test8=test12 and test9=test13 and test10=test14 and test11=test15 and test12=test16 and test1 /= "UUUUUUUU" then仿真波形如下：從圖中可以看出最終temp1從臨時信號temp得到最終輸出，達(dá)到防抖：5.運算模塊當(dāng)前段的模塊經(jīng)過防抖處理以后得到穩(wěn)定的按鍵信號，比如1

15、+2=3,轉(zhuǎn)化為編碼值就是11101101 10111011 01111101 11100111 => ED BB EB 7D E7(具體編碼表見附錄)主要代碼如下：if ysfh=0 then result<=first+second; elsif ysfh=1 then result<=first-second; elsif ysfh=2 then result<=first*second; end if; n<=n+'1'elsif n="100" then n<="000"end if;end

16、if; end process; process (n) begin if n="001"then keyvaluein<=conv_std_logic_vector(first,8); elsif n="011"then keyvaluein<=conv_std_logic_vector(second,8); elsif n="100"then keyvaluein<=conv_std_logic_vector(result,8); end if; end process;仿真波形如下：以1+3=4 和 5x6=3

17、0為例：編碼：01 + 03 =04 05 X 06 =1E6.數(shù)碼管顯示模塊以及動態(tài)掃描模塊由于次兩個模塊是密切相關(guān)的，所以統(tǒng)一到一起驗證。經(jīng)過運算得到最終的顯示結(jié)果后，要在七段數(shù)碼管中顯示，就必須有每一個數(shù)的七段碼，同時，由于前面的運算模塊的結(jié)果最大可以達(dá)到81，也就是需要8位二進(jìn)制，兩位十進(jìn)制來表示，所以就必須通過顯示模塊來分離出十位和個位。分離出十位和個位以后，就必須要利用動態(tài)掃描使兩個數(shù)都能顯示出來。因為8個七段數(shù)碼管的abcdefg位是連在一起的，只有利用分時間隔來顯示，一次使能一個數(shù)碼管，顯示一位數(shù)，當(dāng)頻率較高時，就可以得到兩位數(shù)的顯示效果。數(shù)碼管顯示模塊主要代碼如下：if nu

18、m=0 thenten:=0;one:=10;elsif num<10 and num>0thenten:=0;one:=num;elsif num<20 and num>9 thenten:=1;one:=num-10;elsif num<30 and num>19 thenten:=2;one:=num-20;elsif num<40 and num>29 thenten:=3;one:=num-30;elsif num<50 and num>39 thenten:=4;one:=num-40;elsif num<60 an

19、d num>49 thenten:=5;one:=num-50;elsif num<70 and num>59 thenten:=6;one:=num-60;elsif num<80 and num>69 thenten:=7;one:=num-70;elsif num<90 and num>79 thenten:=8;one:=num-80;elsif num<100 and num>89 thenten:=9;one:=num-90;end if;t<=conv_std_logic_vector(ten,4);o<=conv

20、_std_logic_vector(one,4);動態(tài)掃描模塊主要代碼如下：if count="00" thenshowout<=show1;en<="00000010"elsif count="01" thenshowout<=show2;en<="00000001"end if;仿真波形如下：數(shù)碼顯示模塊Show1是十位數(shù)，show2是個位數(shù)，分別為7E(七段碼十六進(jìn)制)和30,即01。掃描顯示模塊數(shù)碼管使能信號en依次在01和02中變化，翻譯成八段碼就是00000001和0000001

21、0四、 模塊調(diào)用將上述模塊按照層次調(diào)用，就可以得到最頂層的文件，完成計算器的所有要求功能。調(diào)用圖如下：掃描顯示數(shù)碼管顯示運算模塊后端處理防抖模塊鍵盤編碼行驅(qū)動頂層文件時鐘模塊：分頻鍵盤最終的仿真波形如下：01 => showout 0110000 3002 => showout 1101101 6D03 => showout 1111001 79由以上波形可以看出：01 + 02 = 03的計算完成了。五、 總結(jié)本次EDA設(shè)計實踐，完成了從VHDL代碼編寫到硬件實現(xiàn)的整個流程，掌握了一些FPGA的相關(guān)概念以及ISE軟件和Active-HDL軟件的使用方法。最重要的就是組員之間

22、的合作，因為VHDL程序是模塊化編寫的，所以不同模塊是由不同人來完成編譯的，要達(dá)到各個模塊之間能夠良好的銜接通信，就必須有一個很好的溝通交流，把大家的思路集中起來，一起討論、編寫、調(diào)試程序?！靖戒浺弧客暾绦颍悍诸l：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fredivn is generic(n:integer:=3); Port ( clkin:in STD_LOGIC; clkout:out STD_LOGIC);

23、end fredivn;architecture Behavioral of fredivn issignal clk1:std_logic:='0'signal counter:integer range 0 to n; beginprocess(clkin) begin if rising_edge(clkin)then if counter=(n-1)/2 then clk1<=not clk1; counter<=0; else counter<=counter+1; end if; end if; end process; clkout<=cl

24、k1; end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity keyscan is Port ( clr:in std_logic; clkin : in STD_LOGIC; keydrv :out STD_LOGIC_VECTOR(3 downto 0);end keyscan;architecture behavioral of keyscan issignal count : std_logic

25、_vector(1 downto 0); beginprocess(clkin)beginif clr='1' then count<="00"elsif rising_edge(clkin) thenif count="11" thencount<="00" elsecount<=count+1;end if;end if;end process;process(count)beginif count="01" thenkeydrv<="1110"els

26、if count="10" thenkeydrv<="1101"elsif count="11" thenkeydrv<="1011" elsif count="00" thenkeydrv<="0111"end if;end process;end behavioral;鍵值編碼：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_

27、UNSIGNED.ALL;entity keydecoder is Port ( clkin,clk,clr: in std_logic;keyin : in STD_LOGIC_VECTOR (3 downto 0); keycode : out STD_LOGIC_VECTOR (4 downto 0) );end keydecoder;architecture Rtl of keydecoder issignal temp:STD_LOGIC_VECTOR (7 downto 0); signal keydrv1:STD_LOGIC_VECTOR (3 downto 0);signal

28、keyvalue1:STD_LOGIC_VECTOR (4 downto 0);signal temp1:STD_LOGIC_VECTOR (7 downto 0);component keyscanPort ( clkin ,clr: in STD_LOGIC; keydrv : out STD_LOGIC_VECTOR(3 downto 0);end component; component fandou1Port ( clkin ,clr: in STD_LOGIC;temp:in std_logic_vector(7 downto 0);temp1: out STD_LOGIC_VEC

29、TOR(7 downto 0); end component;beginu1: keyscan port map(clkin=>clkin,keydrv=>keydrv1,clr=>clr); temp<=keydrv1&keyin; u2:fandou1 port map(clkin=>clkin,temp=>temp,temp1=>temp1,clr=>clr);process(clk)beginif clr='0' thenif rising_edge(clk) thenif temp1="11101110

30、" thenkeyvalue1<="00000"elsif temp1="11101101" thenkeyvalue1<="00001"elsif temp1="11101011" thenkeyvalue1<="00010"elsif temp1="11100111" thenkeyvalue1<="00011"elsif temp1="11011110" then keyvalue1<=&q

31、uot;00100" elsif temp1="11011101" thenkeyvalue1<="00101"elsif temp1="11011011" thenkeyvalue1<="00110"elsif temp1="11010111" thenkeyvalue1<="00111"elsif temp1="10111110" then keyvalue1<="01000"elsif temp1

32、="10111101" thenkeyvalue1<="01001"elsif temp1="10111011" thenkeyvalue1<="01010"elsif temp1="10110111" thenkeyvalue1<="01011"elsif temp1="01111110" thenkeyvalue1<="01100"elsif temp1="01111101" thenke

33、yvalue1<="01101"elsif temp1="01111011" then keyvalue1<="01110"elsif temp1="01110111" thenkeyvalue1<="01111"end if;end if;end if;end process;keycode<=keyvalue1;end rtl;防抖：library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_ARITH.AL

34、L;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;entity fangdou is port(keycode:in std_logic_vector(4 downto 0);keycode1:out std_logic_vector(4 downto 0);start:out std_logic;clk_f,clr:in std_logic);end fangdou;architecture fangdou of fangdou issignal count1:std_logic_vector(2 downto 0);sig

35、nal key1:std_logic_vector(4 downto 0);signal key2:std_logic_vector(4 downto 0);signal key3:std_logic_vector(4 downto 0);signal key4:std_logic_vector(4 downto 0);signal key5:std_logic_vector(4 downto 0);signal key6:std_logic_vector(4 downto 0);signal key7:std_logic_vector(4 downto 0);signal key8:std_

36、logic_vector(4 downto 0);signal start_1:std_logic;begin process(clk_f)beginif clr='1' thenkey1<="00000"key2<="00001"key3<="00010"key4<="00011"key5<="00100"key6<="00101"key7<="00110"key8<="00111

37、"count1<="000"start_1<='1'elseif rising_edge(clk_f) then if count1="111" thencount1<="000" else count1<=count1+'1'end if;end if;end if;case count1 iswhen "000"=>key1<=keycode;when "001"=>key2<=keycode;when

38、 "010"=>key3<=keycode;when "011"=>key4<=keycode;when "100"=>key5<=keycode;when "101"=>key6<=keycode;when "110"=>key7<=keycode;when "111"=>key8<=keycode;when others =>null;end case;if key1=key2 and key2

39、=key3 and key3=key4 and key4=key5 and key5=key6 and key6=key7 and key7=key8 and key1/="UUUUU"thenkeycode1<=key1;start_1<='0' after 5ns;end if;end process;start<=start_1;end fangdou;運算：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_

40、UNSIGNED.ALL;use ieee.numeric_std.all;entity yunsuan isport(start: in std_logic;keycode1:in std_logic_vector(4 downto 0);keyvaluein:out std_logic_vector(7 downto 0);end yunsuan;architecture Behavioral of yunsuan issignal first,second,result,ysfh: integer range 0 to 99;signal n:std_logic_vector(2 dow

41、nto 0);begin process(start,keycode1)beginif start='1' thenn<="000"else if n="000" thenif keycode1="00001"then first<=1;elsif keycode1="00010"then first<=2;elsif keycode1="00011"then first<=3;elsif keycode1="00100"then fi

42、rst<=4;elsif keycode1="00101"then first<=5;elsif keycode1="00110"then first<=6;elsif keycode1="00111"then first<=7;elsif keycode1="01000"then first<=8;elsif keycode1="01001"then first<=9;elsif keycode1="00000" then first&l

43、t;=0;end if;n<=n+'1'elsif n="001" then if keycode1="01010"then ysfh<=0; elsif keycode1="01011"then ysfh<=1; elsif keycode1="01100"then ysfh<=2;end if; n<=n+'1'elsif n="010" thenif keycode1="00001"then second&l

44、t;=1;elsif keycode1="00010"then second<=2;elsif keycode1="00011"then second<=3;elsif keycode1="00100"then second<=4;elsif keycode1="00101"then second<=5;elsif keycode1="00110"then second<=6;elsif keycode1="00111"then second&l

45、t;=7;elsif keycode1="01000"then second<=8;elsif keycode1="01001"then second<=9;elsif keycode1="00000"then second<=0;end if;n<=n+'1'elsif n="011" and keycode1="01101" then if ysfh=0 then result<=first+second;elsif ysfh=1 then re

46、sult<=first-second;elsif ysfh=2 then result<=first*second; end if; n<=n+'1'elsif n="100" thenn<="000"end if;end if;end process;process (n)beginif n="001"then keyvaluein<=conv_std_logic_vector(first,8);elsif n="011"then keyvaluein<=con

47、v_std_logic_vector(second,8); elsif n="100"then keyvaluein<=conv_std_logic_vector(result,8);end if; end process;end Behavioral;數(shù)碼管顯示：library IEEE;use IEEE.STD_LOGIC_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity shumaguanxianshi isport(keyvaluein:in std_log

48、ic_vector(7 downto 0);clk:in std_logic;show1,show2:out std_logic_vector(6 downto 0);end shumaguanxianshi ;architecture shumaguanxianshi of shumaguanxianshi issignal t:std_logic_vector(3 downto 0); signal o:std_logic_vector(3 downto 0);beginprocess(clk)variable num:integer range 0 to 99;variable ten,

49、one: integer range 0 to 15;beginif rising_edge(clk) thennum:=conv_integer(keyvaluein);if num=0 thenten:=0;one:=10;elsif num<10 and num>0then ten:=0;one:=num;elsif num<20 and num>9 then ten:=1;one:=num-10;elsif num<30 and num>19then ten:=2;one:=num-20;elsif num<40 and num>29th

50、en ten:=3;one:=num-30;elsif num<50 and num>39then ten:=4;one:=num-40;elsif num<60 and num>49 then ten:=5;one:=num-50;elsif num<70 and num>59then ten:=6;one:=num-60;elsif num<80 and num>69 then ten:=7;one:=num-70;elsif num<90 and num>79then ten:=8;one:=num-80;elsif num&l

51、t;100 and num>89 then ten:=9;one:=num-90;end if;t<=conv_std_logic_vector(ten,4); o<=conv_std_logic_vector(one,4);case t iswhen "0000"=>show1<="0000000"when "0001"=>show1<="0110000"when "0010"=>show1<="1101101"when

52、 "0011"=>show1<="1111001"when "0100"=>show1<="0110011"when "0101"=>show1<="1011011"when "0110"=>show1<="0011111"when "0111"=>show1<="1110000"when "1000"=>sho

53、w1<="1111111"when "1001"=>show1<="1110011"when others=>show1<="0000000"end case;case o iswhen "0000"=>show2<="1111110"when "0001"=>show2<="0110000"when "0010"=>show2<="1101

54、101"when "0011"=>show2<="1111001"when "0100"=>show2<="0110011"when "0101"=>show2<="1011011"when "0110"=>show2<="0011111"when "0111"=>show2<="1110000"when "1000&

55、quot;=>show2<="1111111"when "1001"=>show2<="1110011"when others=>show2<="0000000"end case;end if;end process;end shumaguanxianshi ;動態(tài)顯示：library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;entity s

56、haomiaoxianshi isport(clk,clr:in std_logic;show1:in std_logic_vector(6 downto 0);show2:in std_logic_vector(6 downto 0);showout:out std_logic_vector(6 downto 0);en:out std_logic_vector(7 downto 0);end shaomiaoxianshi;architecture shaomiaoxianshi of shaomiaoxianshi issignal count:std_logic_vector(1 do

57、wnto 0);beginprocess(clk)beginif clr='1' then count<="00"elseif clk'event and clk='1' then if count="01"thencount<="00"else count<=count+'1'end if;end if;if count="00" thenshowout<=show1;en<="00000010"elsif

58、count="01" thenshowout<=show2;en<="00000001"end if;end if;end process;end shaomiaoxianshi;鍵盤：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity keyboard isPort ( clr: in std_logic; clk : in STD_LOGIC; keyin : in STD_

59、LOGIC_VECTOR (3 downto 0);keydrv1:out std_logic_vector(3 downto 0);keyvalue :out STD_LOGIC_VECTOR(4 downto 0);start:out std_logic);end keyboard;architecture RTL of keyboard is component keyscanPort ( clkin ,clr: in STD_LOGIC; keydrv : out STD_LOGIC_VECTOR(3 downto 0);end component; component keydeco

60、derPort ( clkin,clk,clr:in std_logic;keyin : in STD_LOGIC_VECTOR (3 downto 0);keycode : out STD_LOGIC_VECTOR (4 downto 0);end component; component fangdou port(keycode:in std_logic_vector(4 downto 0);keycode1:out std_logic_vector(4 downto 0);start:out std_logic;clk_f,clr:in std_logic);end component;

61、component fredivngeneric(n:integer:=3); Port ( clkin:in STD_LOGIC; clkout:out STD_LOGIC);end component;signal key2:std_logic_vector(4 downto 0);signal clk_temp1:std_logic;signal key1:std_logic_vector(4 downto 0); signal clk_temp2:std_logic; signal start1:std_logic;beginU1:keyscanport map(clkin=>clk_temp1,keydrv=>keydrv1,clr=>clr);U2:keydecoderport map(clkin=>clk_temp1,keyi