電氣電子專業(yè)_外文翻譯_外文文獻(xiàn)_英文文獻(xiàn)_用SPMC75的PDC定時器做BLDC電機(jī)的速度檢測

1、BLDC Motor Speed Estimation Using PDC Timer Module 1 Speed Calculation of BLDC1.1 Summary of BLDCSince current BLDC has substituted the electrical commutator for the mechanical one, it eliminates the disadvantages of noise, spark, electromagnetic disturbance, short lifetime, etc. Now BLDC is provide

2、d with advantages of simple structure, dependable operation and easy maintenance as AC motor does, as well as advantages of high efficient, no excitation cost and functional speed regulation as traditional DC motor does. So it is widely used in various fields of industrial control now.1.2 PDC Module

3、 IntroductionSPMC75F2413A provides two channels of 16 bit PDC (Phase Detection Control, PDC timers used for capture function and PWM operation. It also supports position detection features for Brushless-DC motor application. The PDC timers are very suitable for both mechanical speed calculation, wit

4、h ACI and BLDC motor included, and phase commutation for changing current conduction according to position information. Figure 1-1 shows the block diagram of entire PDC timers, channel 0 and channel 1. For details of PDC timers specification, please refer to Table 1-1. 12 Figure 1-1 PDC Timers Block

5、 Diagram1.3 PDC OperationThis note mainly depicts PDC application in motor speed measurement. For detailed PDC introduction, please refer to “SPMC75F2413A Programming Guide” authored by Sunplus.PDC module has four types of registers to perform speed measurement: Timer control register P_TMRx_Ctrl (x

6、 = 0, 1, position detection control register P_POSx_DectCtrl (x = 0, 1, input output control register P_TMRx_IOCtrl (x = 0, 1, and timer interrupt enable register P_TMRx_INT (x = 0, 1. Where, P_TMRx_Ctrl and P_POSx_DectCtrl are introduced in detail.1.31Input Output Control Register 3 Bit 15:14SPCK:

7、Capture input sample clock select. These bits select the capture input sample clock. Capture input will be sampled with sample clock. Pulses shorter than four sample clocks will be considered invalid, and will be ignored.00 = FCK/101 = FCK/210 = FCK/411 = FCK/8Bit 13:10MODE: Modes select. These bits

8、 are used to select the timer operation modes. 0000 = Normal operation (continuous counter up counting0100 = Phase counting mode 10101 = Phase counting mode 20110 = Phase counting mode 30111 = Phase counting mode 41x0x = Edge-aligned PWM mode (continuous counter up counting, PWM output 1x1x = Center

9、-aligned PWM mode (continuous counter up/down counting, PWM outputBit 9:8CLEGS: Counter clear edge select. These bits select the counter clearing edge when the clearing source is in input capture mode.00 = do not clear01 = rising edge10 = falling edge11 = both edgeBit 7:5CCLS: Counter clear source s

10、elect. These bits select the TCNT counter clearing source.4000 = TCNT clearing disabled001 = TCNT cleared by P_TMRx_TGRA (x = 0, 1 capture input010 = TCNT cleared by P_TMRx_TGRB (x = 0, 1 capture input011 = TCNT cleared by P_TMRx_TGRC (x = 0, 1 capture input100 = TCNT cleared by every P_POSx_DectDat

11、a (x = 0, 1 change 6 times101 = TCNT cleared by every P_POSx_DectData (x = 0, 1 change 3 times110 = TCNT cleared by P_POSx_DectData (x = 0, 1 position detection data change 111 = TCNT cleared by P_TMRx_TPR (x = 0, 1 compare matchBit 4:3CKEGS: Clock edge select, These bits select the input clock edge

12、. When the input clock is counted using both edges, the input clock period is halved. When FCK/1 is selected as counter clock, counter will count at rising edge if count at both edges is selected.00 = Count at rising edge01 = Count at falling edge1X = Count at both edgesBit 2:0TMRPS: Timer pre-scala

13、r select. These bits select the TCNT counter clock source. It can be selected independently for each channel.000 = Counts on FCK /1001 = Counts on FCK /4010 = Counts on FCK /16011 = Counts on FCK /64100 = Counts on FCK /256101 = Counts on FCK /1024110 = Counts on TCLKA pin input111 = Counts on TCLKB

14、 pin inputControl register configurationP_TMRx_Ctrl(x = 0, 1 is used for the selection of input capture during speed measurement. Rather than being a general input signal, the input capture is a period between two position detection changes triggered by PDC interrupt. This period must be counted wit

15、h a certain frequency supported by a clock source. Thus, the counters on this function must be configured.MODE: Select a timer operation mode in seven modes. However, only the normal5operation (continuous counter up counting mode can be selected in this application, because the other six modes are a

16、ll related to phase counting mode or PWM mode.CCLS: Select a TCNT counter clearing source from eight settings. In this application, one among the three can be set: 100, 101 or 110, which respectively indicates that TCNT is cleared for once every 6/3/1 times P_the POSx_DectData (x = 0, 1 changes. Als

17、o, they can be described as: TCNT is cleared for once every 360/180/60 electrical degree rotation of BLDC. This setting is critical for converting electrical revolution to mechanical revolution and measuring the BLDC speed.CKEGS: Select the input clock edge, which can be rising, falling or both edge

18、s. When the input clock is counted using both edges, the input clock period is halved. Note to count this factor on during the BLDC speed calculation.TMRPS: Select the TCNT counter clock source from eight settings. This setting determines the precision and the range during BLDC speed measurement. Se

19、e the example code below:P_TMR0_Ctrl, B.MODE = 0; / Normal Counting mode P_TMR0_Ctrl, B.CCLS = 6; / TCNT cleared by P_POSx_DectData (x = 0, 1 / Each time position detection data changeP_TMR0_Ctrl, B.CKEGS = 0; / Counting at rising edge P_TMR0_Ctrl, B.TMRPS = 3; / Select FCK/64 clock source 1.3.2 Pos

20、ition Detection Control Register Bit 15:14SPLCK: Sampling clock select. Select FCK/4, FCK/8, FCK/32, or FCK/128 for position sampling clock00 = FCK/401 = FCK/8610 = FCK/3211 = FCK/128Bit 13:12SPLMOD: Sampling mode select. Select one of three modes: sampling when PWM signal is active (PWM is on, samp

21、ling regularly, or sampling when lower side (UN, VN, WN phases are conducting current.00 = Sample when UPWM/VPWM/WPWM bit is set in P_TMRx_OutputCtrl (x = 3, 4 register and generate the PWM waveform01 = Sample regularly10 = Sample when lower phases is in active state and conducting current11 = Reser

22、vedBit 11:8SPLCNT: Sampling count select. These bits select the sampling count for the valid external position detection signals. The position signals must be sampled continuously match as many times as the sampling count set, for the position signals to be considered valid. The valid settings are f

23、rom 1 to 15 times. Note that count 0 and 1 are assumed to be one time.Bit : 7PDEN: Position detection enable. This bit enables/disables the position detection function for position input pins TIOAC. When enabled, the input signals of these pins will be sampled and the results will be latched to PDR

24、2:0 bits in POS_DectData register. When disabled, PDR 2:0 will remain its status.0 = Disable1 = EnableBit 6:0SPDLY: Sampling delay. These bits set a delay time clock in which at SPLCK clock source. It is used to stop sampling in order to prevent erroneous detection due to noise that occurs immediate

25、ly after PWM output turns on.Position detection control registerWhen the position detection changing event occurs, the P_TMRx_TCNT (x = 0, 1 value can be transferred to TGRA. If the position detection interrupt enable bit PDCIE is set to 1 in the corresponding P_TMRx_INT (x = 0, 1 register, the PDC

26、interrupt routine will be called to process the data.SPLCK: Select sampling clock from FCK/4, FCK/8, FCK/32, or FCK/128 for position sampling clock, which determines the detection precision of position change.78Proper setting of SPLCK, SPLCNT and SPDLY will help to prevent erroneous detection and fi

27、lter the disturbance.SPLMOD: Select one of these three modes: sampling when PWM signal is active (PWM is on, sampling regularly, or sampling when lower side (UN, VN, WN phases are conducting current.SPLCNT: Sampling count select. The valid settings are from 1 to 15 times. Note that count 0 and 1 are

28、 both assumed to be one time.PDEN: This bit enables/disables the position detection function for position input pins TIOAC.SPDLY: Sampling delay with the range of 0 to 127. The setting example is shown as blew.P_POS0_DectCtrl, B.SPLCK = 2; / Count on FCK/32 P_POS0_DectCtrl, B.SPLMOD = 1; / Sample re

29、gularly P_POS0_DectCtrl, B.SPLCNT = 10; / Sample 10 times P_POS0_DectCtrl, B.PDEN = 1; / Enable position detection P_POS0_DectCtrl, B.SPDLY = 100; / Sample Delay 1.4 Speed CalculationIn order to obtain the exact parameters, the data must be filtered after captured. There are many filter algorithms,

30、such as low-pass filter, moving average filter, median filter, average filter, limiting filtering, first-order filter, moving average filtering, etc. In general, the data can be considered valid after processed by these filters. Then the speed can be calculated by substituting these parameters data

31、in the formula.Assume Fcap is PDC capture clock frequency; p is the pole-pair of BLDC rotor;TCNT is cleared every m P_POSx_DectData (x = 0, 1 changes, that is, TCNT is cleared atevery *3m rad rotation (m=1, 3, 6, and the position data is NcapSince:d dt =(Formula 1- 1and d =*3m ,N cap dt Fcap =Since

32、electrical degree = p x mechanical rotation then the mechanical angularvelocity is p=(Formula 1- 2with the unit of rad/min. Take n as the indicator.So:26030n n=rad/min (Formula 1- 3n summarize:60*10*3*2*Fcap m Fcap mnNcap p Ncap p=rpm (Formula 1- 4From the formula above, we can obverse that n is rel

33、ated to Fcap, m, Ncap and p (that is a constant when BLDC is selected .Suppose there is a BLDC with 2 pole-pair, 4000rpm rated speed. We will show you how to set the parameters of Fcap and m.When m= 1, TCNT is cleared every time P_POSx_DectData (x = 0, 1 changes, , that is, TCNT is cleared for once

34、every 60 electrical degree rotation of BLDC.With a certain clock frequency, the motor rotation speed can be calculated by the Formula 1- 4 at the highest speed when Ncap is 1 and the lowest speed when Ncap is 0xffff. When m= 3, TCNT is cleared for once every 3 times P_POSx_DectData (x = 0, 1 changes

35、, that is, TCNT is cleared every 180 electrical degree rotation of BLDC.From the Formula 1- 4, we can see that the measurable motor speed when m= 3 is three times higher than that when m= 1, provided that other parameters are the same.When m= 6, TCNT is cleared every 6 times P_POSx_DectData (x = 0,

36、1 changes, that is, TCNT is cleared every 360 electrical degree rotation of BLDC.From the Formula 1- 4, we can see that the measurable motor speed when m= 6 is six times higher than that when m= 1, provides that other parameters are the same.Above all, it is better to set m= 1 to ensure the veracity

37、 of positions. Since the highest speed can be applied, it is important to select the lowest speed. Assume the lowest measure speed is 200 rpm, we can set Fcap as FCK/16, FCK/64, FCK/256 or FCK/1024. FCK/16 is recommended to be selected for higher veracity.1.5 Noise Immunity9Through programming the b

38、it value of SPLCNT (sampling count select and SPDLY (sampling delay in P_POSx_DectCtrl(x = 0, 1, users could avoid the erroneous detection due to noise that occurs immediately after PWM output turns on. It can ensure the correctness of speed measurement and phase commutation in BLDC .The valid setti

39、ngs are from 1 to 15 times. Note that count 0 and 1 are both assumed to be one time. These bits select the sampling count for the valid external position detection signals. The position signals must be sampled continuously match as many times as the sampling count set, for the position signals to be

40、 considered valid. Then the sharp pulse can be filtered by this method. SPLCK selects the sampling clock. Figure 1-2 shows the sampling counting and Figure 1-3 shows the noise immunity pulse. Figure 1-2 Sampling Counting Figure 1-3 Noise Immunity PulseSee Figure 1-2 , the SPLCNT setting is 10. When

41、sampling the position signal with the frequency that SPLCK selected, a high-to-low transition occurs in hall3 at 0 to1 counting. Then sample the hall signal for ten executive times. If they are all of the same10value, the hall signal can be considered valid.When SPLCNT setting is 10, a high-to-low t

42、ransition occurs in hall3 at the first counting, while a low-to-high transition occurs at the fourth counting. Then reset the counter, sample hall3 for ten executive times. If they are all of the same value, the position signals can be considered as 011b still. By this way, a sharp pulse occurring i

43、n the signals can be filtered, which prevents the position signals from being disturbed. So the position signal will not be sampled if it varies quicker than the setting of SPLCK/SPLCNT does (note that count 0 and 1 are assumed to be one time.2 Software Design2.1 Software DescriptionThis application

44、 note is designed for motor speed measurement when driving BLDC, which is performed by PDC position detection change interrupt. 2.3 DMC InterfaceSpeed1_Now: Current speed by calculationUser_R0: PDC Data captured by PDC interrupt2.4 SubroutinesSpmc75_System_Init ( Prototype void Spmc75_System_Init(vo

45、idDescription Initialize PDC Timers and DMCInput Arguments NoneOutput Arguments None11Library Files Spmc75_ SPDET _V100Note PDC timer0 is initialized hereExample Spmc75_System_Init(;Spmc75_PDCETSPD_ISR ( Prototype void Spmc75_PDCETSPD_ISR(void Description Data capture, filter and calculationInput Ar

46、guments NoneOutput Arguments NoneLibrary Files Spmc75_SPDET_V100Note PDC ISRExample Spmc75_PDCETSPD_ISR(;3 Design Tips3.1 Demo Listing/*= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = */ / Example/*= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

47、= = = = = */ #include "Spmc75_regs.h"#include "Spmc_typedef.h"#include "unspmacro.h"#include "Spmc75_SPDET.h"main(Spmc75_System_Init(; /System initializationwhile(1MC75_DMC_UART_Service(; /DMC service/= = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

48、 = = = = = = = = = = = = / Description: IRQ1 interrupt source is XXX, used to XXX/ Notes: Speed measurement through PDC12/= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = void IRQ1(void_attribute_(ISR;void IRQ1(voidSpmc75_PDCETSPD_ISR(; / PDC capture interrupt for

49、the motor speed calculation./= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = / Description: IRQ6 interrupt source is XXX, used to XXX/ Notes: DMC receiving ISR/= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = void IRQ6(void _attr

50、ibute_ (ISR;void IRQ6(voidif(P_UART_Status, B.RXIF MC75_DMC_RcvStream(;Sub-function for speed measurement#define TMRPSFCK (24.0E+6/64 /Counter clock source#define PAIRPOLE 2 /BLDC pole pairs#define PDCCLEAR 1 /CNT clear source#define SPDLIMIT 5000 /Define the highest motor speed to avoid the disturb

51、ance due to sharp pulse#define RADIX (UInt32(TMRPSFCK*60*PDCCLEAR /(6*PAIRPOLE#define MAXRPM (UInt16(RADIX/SPDLIMITstatic UInt16 a FilterCAPBSIZE; /Moving average filter datastatic UInt16 *ptr = a Filter; /Pointer to arrayvoid Spmc75_PDCETSPD_ISR(void13static UInt32 summation= 0;UInt16 original, uiS

52、peed;P_TMR0_Status, B.PDCIF = 1; / Clear interrupt flagoriginal = P_TMR0_TGRA, W; /Read PDC captured data/Limit the highest speedif(original > P_TMR0_TCNT, W && original > MAXRPM/Accumulate the captured data and perform moving filtersummation -= *ptr;*ptr = original;summation += *ptr;/

53、Loop the arrayif(+ptr > (a Filter+CAPBSIZE-1 ptr = a Filter;/ Average the accumulation data original = (UInt16(summation >> SHIFTDIV;uiSpeed = (UInt32RADIX/original;/Speed calculationSPMC_DMC_Save_Aux(0, original;/Transmit captured data to DMC SPMC_DMC_Save_SpdNow(1, uiSpeed;/Send data to D

54、MC3.2 Main Process DescriptionThe main program performs system initialization and DMC data detection. While the DMC data detection can also be performed in a timer interrupt with a certain frequency. Figure 3-1 shows the coding flow. Figure 3-1 Main Process3.3 ISR DescriptionIn PDC interrupt, system

55、 reads and filters the data, then calculates the motor speed. The coding flow is shown as Figure 3-2 .Figure 3-2 ISR Process3.4Testing HardwareThis example is designed for the purpose of study and reference, so we simply need to input a position signal to test the system. The hardware connection is

56、shown as Figure 3-3 . 15 Figure 3-3 Test Hardware ConnectionWhere, the position signal can be generated by MCU or special timing logic circuit instead of necessarily being the real signal from BLDC (see Figure 3-4 and Figure 3-5 . The frequency of position detection change can be adjusted by the pot

57、entiometer or ADC in MCU system Figure 3-4 Hall SignalFigure 3-4 shows the three position signals timing with the sequence of 010b, 011b, 001b, 101b, 100b, 110b. Figure 3-5 Hall signal16Figure 3-5 shows Hall3, Hall2, Hall1 timing with the sequence of 110b, 100b, 101b, 001b, 011b, 010b. It is the same to test in real BLDC. The two timings present the different motor directions: move forward or move backward.The Hall.spj file in Appendix shows the code for simulating hall signal with SPMC75F2413A. We can use ADC0 voltage to simulate the speed variation, where IOD15,