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1、IT8705FSimple Low Pin Count Input / Output (Simple LPC I/O)Preliminary Specification V0.3Copyright ã 1999 ITE, Inc.This is Preliminary document release. All specifications are subject to change without notice.The material contained in this document supersedes all previous documentation issued f

2、or the related products included herein. Please contact ITE, Inc. for the latest document(s).All sales are subject to ITE s Standard Terms and Conditions, a copy of which is included in the back of this document.ITE, IT8705F is a trademark of ITE, Inc. Intel is a trademark claimed by Intel Corp.Micr

3、osoft is claimed as a trademark by Microsoft Corporation. PCI is claimed as a trademark by the PCI Special Interest Group. IrDA is claimed as a trademark by the Infrared Data Association. All other trademarks are claimed by their respective owners.All specifications are subject to change without not

4、ice.Additional copies of this manual or other ITE literature may be obtained from:ITE (USA) Inc.Marketing Department 1235 Midas Way,Sunnyvale, CA 94086Phone: Fax:(408) 530-8860(408) 530-8861ITE (USA) Inc.Eastern U.S.A. Sales Office 896 Summit St., #105 Round Rock, TX 78664 U.S.A.Phone: Fax:(512) 388

5、-7880(512) 388-3108ITE, Inc.Marketing Department7F, No. 435, Jui Kuang Rd.,Phone: Fax:(02) 2657-9896(02) 2657-8561, 2657-8576Taipei 114, R.O.C.If you have any marketing or sales questions, please contact:Lawrence Liu, at ITE Fax: 886-2-26578561David Lin, at ITE U.S.A: lawrence.liu.tw, Tel: 886-2-265

6、79896 X6071,: david.lin, Tel: (408) 980-8168 X238,Fax: (408) 980-9232Don Gardenhire, at ITE Eastern USA Office: Tel: (512) 388-7880, Fax: (512) 388-3108: don.gardenhire,To find out more about ITE, visit our World Wide Web at: iteusa comOritesupport.tw for more product information/services.Revision H

7、istoryRevision HistoryNote: Words in bold typeface in the revisions below indicate the changes.1IT8705F V0.3SectionRevisionPage No.1· The feature of Smart Carder was added.· The feature of “ 48 General Purpose I/O Pins” was revised.12· At the end of the second paragraph, the descripti

8、on “It also features a PC/SC and ISO 7816 compliant Smart Carder.” was added.33· Block Diagram was revised.54· Section 4 Pin Configuration was revised.7· Pin 2 was revised to “ RTS2#/JP6” .· Pin 11 was revised to “ FD4/IRQIN0/GP14”.· Pin 12 was revised to “ FD5/IRQIN1/GP15”.

9、· Pin 13 was revised to “ FD/IRQIN2/GP16” .· Pin 14 was revised to “ FD/IRQIN3/GP17” .· Pin 16 was revised to “ FA0/VID_I0/GP20”.· Pin 17 was revised to “ FA1/VID_I1/GP21”.· Pin 18 was revised to “ FA2/VID_I2/GP22”.· Pin 19 was revised to “ FA3/VID_I3/GP23”.· Pin 2

10、0 was revised to “ FA4/VID_I4/GP24”.· Pin 21 was revised to “ FA5/VID_O1/GP25”.· Pin 22 was revised to “ FA6/VID_O2/GP26”.· Pin 23 was revised to “ FA7/VID_O3/GP27”.· Pin 24 was revised to “ FA8/VID_O4/GP30”.· Pin 25 was revised to “ FA9/VID_O5/GP31”.· Pin 47 was revise

11、d to “ FCS#/SCIO/GP53” .· Pin 59 was revised to “ MTRB#/SCRST”.· Pin 61 was revised to “ DRVB#/SCCLK” .· Pin 80 was revised to “ FAN_CTL3/GP62/SCPFET#”.· Pin 81 was revised to “ PME#/GP63/SCPRES#”.8-95· The pin descriptions of the revised pins described above were revised.11

12、-19· Add the note “The GPIO registers of these pins are powered by VCC, not VCCH.” to the end of Table 5-4 and Table 5-5.12-13· The pin descriptions of pins 69, 70, 71, 72 were revised.176· Section 6 List of GPIO Pins was revised.21-23IT8705FRevision History (cont d)2IT8705F V0.3Secti

13、onRevisionPage No.6· Add the note “The GPIO registers of these pins are powered by VCC, not VCCH.” to the end of Table 6-6.237· Table 7-1. Power On StrapOptions was revised.258· In Table 8-1, the register for index 22h was revised to “ Configuration Select and Chip Version”.28· I

14、n Table 8-4, two more Serial Port Configuration registers weded: Serial Port 2 Special Configuration Register 3, and Serial Port 2 Special Configuration Register 4.29· In Table 8-7, two more GPIO Configuration registers weded: IRQ Routing Input 0 and 1 Interrupt Level Select Register, and IRQ R

15、outing Input 2 and 3 Interrupt Level Select Register.31· Several new registers weded from Index F6h through FFh at the end of Table 8-7 GPIO Configuration Registers.32· Section 8.3.5 Configuration Select and Chip Version Register was revised.· In section 8.3.6 Software Suspend, the bi

16、ts 7-6 was revised to “SCRPRES# Select”.· In section 8.3.7 Clock Selection and Flash ROM I/F Control Register, the description of bit 5 was revised to Flash ROM Interface Address Segment 2 (FFEF0000h-FFEFFFFh, FFEE0000h-FFEEFFFFh) Enable.35· The bit 2-0 description for section 8.6.6 Serial

17、 Port 2 Special Register 2 was revised. It added the “ 100: Smart Carder (SCR).44· The descriptions for Serial Port 2 Special Configuration Register 3 and Serial Port 2 Special Configuration Register 4 weded in section 8.6.7 and 8.6.8 respectively.45· The bit 0 of section 8.8.9 PME Control

18、 Register 1 was revised to “” .49· Added 2 new registers in section 8.9.8, and 8.9.9: IRQ Routing Input 0 and 1 Interrupt Level Select Register, and IRQ Routing Input 2 and 3 Interrupt Level Select Register.51· Added the descriptions of several new registers from section 8.9.20 through 8.9

19、.29.54-56· The descriptions of bits 7-6, 5-4, 3 of Section 8.12.5 MIDI Port Special Configuration Register were revised.589· In Table 9-2. Environment Controller Registers, the Serial Bus Interface Address Register was revised to “”.67Revision HistoryRevision History (cont d)3IT8705F V0.3S

20、ectionRevisionPage No.9· In Table 9-2. Environment Controller Registers, the registers from Index 52h to 54h were revised to “” registers.· In Table 9-2. Environment Controller Registers, 4 new EC registers were added from index 5Ch through 5Fh: 1) Special Control and Beep Event Enable Reg

21、ister, 2) Beep Frequency Divisor of Fan Event Register, 3) Beep Frequency Divisor of Voltage Event Register, and 4) Beep Frequency Divisor of Temperature Event Register.68· The bit 6 description in section 9.5.3.2.11 Fan Tachometer Divisor Register was revised.70· The R/W of section 9.5.3.

22、2.13 Fan Tachometer 1-3 Limit Registers (Index=10h-12H) was revised to “ R/W”.· Bit 7 description of section 9.5.3.2.14 Fan Controller Main Control Register was revised.· Bits 7 & 6-4 descriptions of section 9.5.3.2.15 FAN_CTL Control Register were revised.71· Section 9.5.3.2.26 S

23、erial Bus Interface Address Register (Index=48h) was revised to “” register.· Section 9.5.3.2.28 bit no. 7 was revised to bit no. 7-6.73· The registers from Index 54h-52h was changed to “” registers in section 9.5.3.29.74· In section 9.5.4.3 Voltage and Temperature Input, the formula

24、for Negative Voltage was revised to “Vs = (1+Rin/Rf) x Vin - (Rin/Rf) x VREF” .78· The descriptions of the 4 new EC registers described above were given from section 9.5.3.2.32 through 9.5.3.2.35.74-75· In section 9.7.2, the “ DLAB=0” should be changed to “ DLAB=1” in title (4) Divisor Lat

25、ches (DLL, DLM).1114IT8705F V0.3ContentsCONTENTSFeatures1General Description3Block Diagram5Pin Configuration7IT8705F Pin Descriptions11List of GPIO Pins211.2.3.4.5.6.7.8.Power On StrapOptions25Configuration278.18.2Configuring Sequence Description27Description of the Configuration Registers288.2.1Log

26、ical Device Base Address348.3Global Configuration Registers (LDN: All)358.3.18.3.28.3.38.3.48.3.58.3.68.3.78.3.88.3.9Configure Control (Index=02h)35Logical Device Number (LDN, Index=07h)35Chip ID Byte 1 (Index=20h, Default=87h)35Chip ID Byte 2 (Index=21h, Default=05h)35Configuration Select and Chip

27、Version (Index=22h, Default=02h)35Software Suspend (Index=23h, Default=00h)35Clock Selection and Flash ROM I/F Control Register (Index=24h, Default=sssss000b)36GPIO Set 1 Multi-Function Pin Selection Register (Index=25h, Default=00h)36GPIO Set 2 Multi-Function Pin Selection Register (Index=26h, Defa

28、ult=00h)37GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h)37GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=FFh)38GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=E0h)39GPIO Set 6 Multi-Function Pin Selection Register (Index=2Ah, Defa

29、ult=FFh)40Test Mode Register 1 (Index=2Eh, Default=00h)40Test Mode Register 2 (Index=2Fh, Default=00h)408.3.108.3.118.3.128.3.138.3.148.3.158.4FDC Configuration Registers (LDN=00h)418.4.18.4.28.4.38.4.48.4.58.4.68.4.7FDC Activate (Index=30h, Default=00h)41FDC Base Address MSB Register (Index=60h, De

30、fault=03h)41FDC Base Address LSB Register (Index=61h, Default=F0h)41FDC Interrupt Level Select (Index=70h, Default=06h)41FDC DMA Channel Select (Index=74h, Default=02h)41FDC Special Configuration Register 1 (Index=F0h, Default=00h)42FDC Special Configuration Register 2 (Index=F1h, Default=00h)428.5S

31、erial Port 1 Configuration Registers (LDN=01h)428.5.18.5.28.5.38.5.48.5.5Serial Port 1 Activate (Index=30h, Default=00h)42Serial Port 1 Base Address MSB Register (Index=60h, Default=03h)42Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h)43Serial Port 1 Interrupt Level Select (Index=70

32、h, Default=04h)43Serial Port 1 Special Configuration Register (Index=F0h, Default=00h)438.6Serial Port 2 Configuration Registers (LDN=02h)438.6.18.6.28.6.38.6.48.6.58.6.68.6.7Serial Port 2 Activate (Index=30h, Default=00h)43Serial Port 2 Base Address MSB Register (Index=60h, Default=02h)43Serial Por

33、t 2 Base Address LSB Register (Index=61h, Default=F8h)44Serial Port 2 Interrupt Level Select (Index=70h, Default=03h)44Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h)44Serial Port 2 Special Configuration Register 2 (Index=F1h, Default=50h)44Serial Port 2 Special Configuration

34、 Register 3 (Index=F2h, Default=00h)45iIT8705F V0.3IT8705F8.6.8Serial Port 2 Special Configuration Register 4 (Index=F3h, Default=7Fh)458.7Parallel Port Configuration Registers (LDN=03h)458.7.18.7.28.7.38.7.48.7.58.7.68.7.78.7.88.7.9Parallel Port Activate (Index=30h, Default=00h)45Parallel Port Prim

35、ary Base Address MSB Register (Index=60h, Default=03h)45Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h)46Parallel Port Secondary Base Address MSB Register (Index=62h, Default=07h)46Parallel Port Secondary Base Address LSB Register (Index=63h, Default=78h)46POST Data Port Bas

36、e Address MSB Register (Index=64h, Default=00h)46POST Data Port Base Address LSB Register (Index=65h, Default=80h)46Parallel Port Interrupt Level Select (Index =70h, Default=07h)46Parallel Port DMA Channel Select (Index=74h, Default=03h)47Parallel Port Special Configuration Register (Index=F0h, Defa

37、ult=03h)478.7.108.8Environment Controller Configuration Registers (LDN=04h)478.8.18.8.28.8.38.8.48.8.58.8.68.8.78.8.88.8.9Environment Controller Activate Register (Index=30h, Default=00h)47Environment Controller Primary Base Address MSB Register (Index=60h, Default=02h)47Environment Controller Prima

38、ry Base Address LSB Register (Index=61h, Default=90h)47PME Direct Access Base Address MSB Register (Index=62h, Default=02h)48PME Direct Access Base Address LSB Register (Index=63h, Default=30h)48Environment Controller Interrupt Level Select (Index=70h, Default=09h)48PME Event Enable Register (Index=

39、F0h, Default=00h)48PME Status Register (Index=F1h, Default=00h)49PME Control Register 1 (PCR 1) (Index=F2h, Default=00h)49Environment Controller Special Configuration Register (Index=F3h, Default=00h)49PME Control Register 2 (PCR2) (Index=F4h, Default=00h)49PME Special Code Index Register (Index=F5h

40、)49PME Special Code Data Register (Index=F6h)508.8.108.8.118.8.128.8.138.9GPIO Configuration Registers (LDN=05h)508.9.18.9.28.9.38.9.48.9.58.9.68.9.78.9.88.9.9Simple I/O Base Address MSB Register (Index=60h, Default=00h)50Simple I/O Base Address LSB Register (Index=61h, Default=00h)50Panel Button De

41、-bounce Base Address MSB Register (Index=62h, Default=00h)50Panel Button De-bounce Base Address LSB Register (Index=63h, Default=00h)50SMI# Normal Run Access Base Address MSB Register (Index=64h, Default=00h)50SMI# Normal Run Access Base Address LSB Register (Index=65h, Default=00h)50Panel Button De

42、-bounce Interrupt Level Select Register (Index=70h, Default=00h)51IRQ Routing Input 0 and 1 Interrupt Level Select Register (Index=71h, Default=00h)51IRQ Routing Input 2 and 3 Interrupt Level Select Register (Index=72h, Default=00h)51GPIO Pin Set 1, 2, 3, 4, 5 and 6 Polarity Registers (Index=B0h, B1

43、h, B2h, B3h, B4h and B5h, Default=00h)51GPIO Pin Set 1, 2, 3, 4, 5 and 6 Pin Internal Pull-up Enable Registers (Index=B8h, B9h, BAh, BBh, BCh and BDh, Default=00h)52Simple I/O Set 1, 2, 3, 4, 5 and 6 Enable Registers (Index=C0h, C1h, C2h, C3h,C4h and C5h, Default=00h)52Simple I/O Set 1, 2, 3, 4, 5 a

44、nd 6 Output Enable Registers (Index=C8h,C9h,CAh,CBh,CCh and CDh, Default=00h)52Panel Button De-bounce Control Register (Index=D0h, Default=00h)52Panel Button De-bounce Set 1, 2, 3, 4, 5 and 6 Enable Registers (Index=D1h, D2h, D3h, D4h, D5h and D6h, Default=00h)53SMI# Control Register (Index=F0h, Def

45、ault=00h)53SMI# Status Register (Index=F2h, Default=00h)538.9.108.9.118.9.128.9.138.9.148.9.158.9.168.9.178.9.188.9.198.9.208.9.21SMI# Pin MapRegister (Index=F5h, Default=00h)54Hardware Monitor Alert Beep Pin MapRegister (Index=F6h, Default=00h)54GP LED Blinking 1 Pin MapRegister (Index=F7h, Default

46、=00h)54GP LED Blinking 1 Control Register (Index=F8h, Default=00h)54iiIT8705F V0.3Contents8.9.228.9.238.9.248.9.258.9.268.9.278.9.28GP LED Blinking 2 Pin MapRegister (Index=F9h, Default=00h)54GP LED Blinking 2 Control Register (Index=FAh, Default=00h)55Watch Dog Timer Control Register (Index=FBh, De

47、fault=00h)55Watch Dog Timer Time-out Output Pin MapRegister (Index=FCh, Default=00h)55Watch Dog Timer Time-out Value Register (Index=FDh, Default=00h)55VID Input Register (Index=FEh, Default= - )56VID Output Register (Index=FFh, Default=00h)568.10Game Port Configuration Registers (LDN=06h)568.10.1 G

48、ame Port Activate (Index=30h, Default=00h)568.10.2 Game Port Base Address MSB Register (Index=60h, Default=02h)568.10.3 Game Port Base Address LSB Register (Index=61h, Default=01h)56Consumer IR Configuration Registers (LDN=07h)568.11.1 Consumer IR Activate (Index=30h, Default=00h)568.11.2 Consumer I

49、R Base Address MSB Register (Index=60h, Default=03h)578.11.3 Consumer IR Base Address LSB Register (Index=61h, Default=10h)578.11.4 Consumer IR Interrupt Level Select (Index=70h, Default=0Bh)578.11.5 Consumer IR Special Configuration Register (Index=F0h, Default=00h)57MIDI Port Configuration Registe

50、rs (LDN=08h)578.118.128.12.18.12.28.12.38.12.48.12.5MIDI Port Activate (Index=30h, Default=00h)57MIDI Port Base Address MSB Register (Index=60h, Default=03h)57MIDI Port Base Address LSB Register (Index=61h, Default=00h)58MIDI Port Interrupt Level Select (Index=70h, Default=0Ah)58MIDI Port Special Co

51、nfiguration Register (Index=F0h, Default=00h)589.Functional Description619.1LPC Interface619.1.19.1.2LPC Tranions61LDRQ# Encoding619.2Serialized IRQ619.2.19.2.29.2.39.2.4Continuous Mode61Quiet Mode62Waveform Samples of SERIRQ Sequence62SERIRQ Sampling Slot639.39.49.5General Purpose I/O63Power Manage

52、ment Event (PME#)64Environment Controller (Enhanced Hardware Monitor and Fan Controller)659.5.19.5.29.5.3Overview65Interfaces65Registers669.5.3.19.5.3.2Address Port (Base+05h, Default=00h):66Register Description699.5.3.2.19.5.3.2.29.5.3.2.39.5.3.2.49.5.3.2.59.5.3.2.69.5.3.2.79.5.3.2.89.5.3.2.9Config

53、uration Register (Index=00h, Default=18h)69Interrupt Status Register 1 (Index=01h, Default=00h)69Interrupt Status Register 2 (Index=02h, Default=00h)69Interrupt Status Register 3 (Index=03h, Default=00h)69SMI# Mask Register 1 (Index=04h, Default=00h)69SMI# Mask Register 2 (Index=05h, Default=00h)70S

54、MI# Mask Register 3 (Index=06h, Default=00h)70Interrupt Mask Register 1 (Index=07h, Default=00h)70Interrupt Mask Register 2 (Index=08h, Default=00h)70Interrupt Mask Register 3 (Index=09h, Default=00h)70Fan Tachometer Divisor Register (Index=0Bh, Default=09h)709.5.3.2.109.5.3.2.119.5.3.2.129.5.3.2.13

55、Fan Tachometer 1-3ing Registers (Index=0Dh-0Fh)71Fan Tachometer 1-3 Limit Registers (Index=10h-12h)71iiiIT8705F V0.3IT8705F9.5.3.2.149.5.3.2.159.5.3.2.169.5.3.2.179.5.3.2.189.5.3.2.199.5.3.2.209.5.3.2.219.5.3.2.22Fan Controller Main Control Register (Index=13h, Default=00h)71FAN CTL Control Register

56、 (Index=14h, Default=00h)71FAN_CTL1 FAN_CTL2 FAN_CTL3Control Register (Index=15h, Default=00h)72Control Register (Index=16h, Default=00h)72Control Register (Index=17h, Default=00h)72VIN7-VIN0 Voltage VBAT Voltageing Registers (Index=27h-20h)72ing Register (Index=28h)72TMPIN3-1 Temperatureing Registers (Index=2Bh-29h)73VIN7-0 High Limit Registers (Index=3Eh, 3Ch, 3Ah, 38h, 36h, 34h,32h and 30h)73VIN7-0 Low Li