IC-Semiconductor Design and Manufacturing Overview

1、IC-Semiconductor Design and Manufacturing Overview Typical Integrated Circuit (IC) Design Flow (Hewlett Packard)Integrated Circuit SimulationThirty years ago, the tools that made the engineering knowledge practical included the drawing board and the slide rule. Nowadays, the tool chest includes comp

2、uters and engineering software-Out of a great variety of different computer programs, the electronic circuit simulator SPICE (on which MultiSim is based) is probably the most important for electrical engineers.-The SPICE program, originated and developed at University of California at Berkeley, is t

3、ruly a wonderful present to the electrical engineering community worldwide from one of the best American public universities. It allows us to simulate both individual devices and electronic circuits, performing a large number of different analyses needed for tasks such as verification of circuit des

4、igns and prediction of circuit performance. It is so flexible and usually so reliable that many engineers use it as a software oscilloscope. However, the results of a SPICE simulation are only as good as the device models and the device parameters used in the simulation. Device technologies change s

5、o fast and device characteristics are so different that just using default parameters is almost never justified. If wrong device parameters or models are used in a SPICE simulation, all this computer power will be wastedtrue to the old adage: Garbage in, garbage out. Less than a decade ago, a typica

6、l circuit simulator would run only on mainframe computers. However, the rapid progress in microcomputers has enabled the development of SPICE versions that can run on inexpensive machines, making advanced circuit simulators readily available practically to every electrical engineer and electrical en

7、gineering student. Hence, we are now in the privileged situation that we can teach a course on the basics of semiconductor device physics and device modeling using the same computer aided design (CAD) tool that electrical engineering students will almost certainly use as practicing engineers. This f

8、ortunate circumstance allows students to try actual circuit design, bringing semiconductor device physics and modeling (which are often taught as a fairly theoretical subject) down to a very practical level.Semiconductor Manufacturing Processes Design Wafer Preparation Front-end Processes Photolitho

9、graphy Etch Cleaning Thin Films Ion Implantation Planarization Test and AssemblyThin FilmsPhoto-lithographyCleaningFront-EndProcessesEtchIonImplantationPlanarizationTest &AssemblyDesignWaferPreparationDesignThin FilmsPhoto-lithographyCleaningFront-EndProcessesEtchIonImplantationPlanarizationTest

10、 &AssemblyDesignWaferPreparation Establish Design Rules Circuit Element Design Interconnect Routing Device Simulation Pattern PreparationPattern PreparationReticleChrome PatternQuartz SubstratePellicleWafer PreparationThin FilmsPhoto-lithographyCleaningFront-EndProcessesEtchIonImplantationPlanar

11、izationTest &AssemblyDesignWaferPreparation Polysilicon Refining Crystal Pulling Wafer Slicing & Polishing Epitaxial Silicon DepositionPolysilicon RefiningChemical Reactions Silicon Refining: SiO2 + 2 C Si + 2 CO Silicon Purification: Si + 3 HCl HSiCl3 + H2 Silicon Deposition: HSiCl3 + H2 Si

12、 + 3 HClReactants H2 Silicon Intermediates H2SiCl2 HSiCl3Crystal PullingQuartz TubeRotating ChuckSeed CrystalGrowing Crystal (boule)RF or ResistanceHeating CoilsMolten Silicon(Melt)CrucibleMaterials Polysilicon Nodules * Ar * H2* High proportion of the total product useProcess Conditions Flow Rate:

13、20 to 50 liters/min Time: 18 to 24 hours Temperature: 1,300 degrees C Pressure: 20 Torr3/15/98PRAX01C.PPT Rev. 1.0Wafer Slicing & PolishingThe silicon ingot is sliced into individual wafers, polished, and cleaned.silicon waferp+ silicon substrateEpitaxial Silicon DepositionGasInputLampModuleQuar

14、tzLampsWafersSusceptorExhaust* High proportion of the total product useChemical Reactions Silicon Deposition: HSiCl3 + H2 Si + 3 HClProcess Conditions Flow Rates: 5 to 50 liters/min Temperature: 900 to 1,100 degrees C. Pressure: 100 Torr to Atmosphericsilicon waferp- silicon epi layerp+ silicon subs

15、trateDopants AsH3 B2H6 PH3Etchant HClCarriers Ar H2 * N2Silicon Sources SiH4 H2SiCl2 HSiCl3 * SiCl4 *Thin FilmsPhoto-lithographyCleaningFront-EndProcessesEtchIonImplantationPlanarizationTest &AssemblyDesignWaferPreparation Thermal Oxidation Silicon Nitride Deposition- Low Pressure Chemical Vapor

16、 Deposition (LPCVD) Polysilicon Deposition- Low Pressure Chemical Vapor Deposition (LPCVD) AnnealingFront-End ProcessesFront-End Processes* High proportion of the total product usePolysilicon H2 N2 SiH4 * AsH3 B2H6 PH3Exhaust ViaVacuum Pumpsand Scrubber3 ZoneTemperatureControlGas InletVertical LPCVD

17、 FurnaceQuartz TubeChemical Reactions Thermal Oxidation: Si + O2 SiO2 Nitride Deposition: 3 SiH4 + 4 NH3 Si3N4 + 12 H2 Polysilicon Deposition: SiH4 Si + 2 H2Process Conditions (Silicon Nitride LPCVD) Flow Rates: 10 - 300 sccm Temperature: 600 degrees C. Pressure: 100 mTorrsilicon dioxide (oxide)p- s

18、ilicon epi layerp+ silicon substrateNitride NH3 * H2SiCl2 * N2 SiH4 * SiCl4Oxidation Ar N2 H2O Cl2 H2 HCl * O2 * Dichloroethene *Annealing Ar He H2 N2PhotolithographyThin FilmsPhoto-lithographyCleaningFront-EndProcessesEtchIonImplantationPlanarizationTest &AssemblyDesignWaferPreparation Photores

19、ist Coating Processes Exposure ProcessesPhotoresist Coating Processesp- epip+ substratefield oxidephotoresistPhotoresists Negative Photoresist * Positive Photoresist *Other Ancillary Materials (Liquids) Edge Bead Removers * Anti-Reflective Coatings * Adhesion Promoters/Primers (HMDS) * Rinsers/Thinn

20、ers/Corrosion Inhibitors * Contrast Enhancement Materials *Developers TMAH * Specialty Developers *Inert Gases Ar N2Exposure Processesp- epip+ substratefield oxidephotoresistExpose Kr + F2 (gas) *Inert Gases N2Ion ImplantationThin FilmsPhoto-lithographyCleaningFront-EndProcessesEtchIonImplantationPl

21、anarizationTest &AssemblyDesignWaferPreparation Well Implants Channel Implants Source/Drain ImplantsIon Implantation180 kVResolvingApertureIon SourceEquipment GroundAcceleration Tube90 Analyzing MagnetTerminal Ground20 kVFocusNeutral beam and beam path gatedBeam trap andgate plateWafer in waferp

22、rocess chamberX - axisscannerY - axisscannerNeutral beam trap and beam gateGases Ar AsH3 B11F3 * He N2 PH3 SiH4 SiF4 GeH4Solids Ga In SbLiquids Al(CH3)3* High proportion of the total product usejunction depthp- epip+ substratefield oxidephotoresist maskn-wellp-channel transistorphosphorus (-) ionsPr

23、ocess Conditions Flow Rate: 5 sccm Pressure: 10-5 Torr Accelerating Voltage: 5 to 200 keVEtchThin FilmsPhoto-lithographyCleaningFront-EndProcessesEtchIonImplantationPlanarizationTest &AssemblyDesignWaferPreparation Conductor Etch- Poly Etch and Silicon Trench Etch- Metal Etch Dielectric EtchCond

24、uctor Etch* High proportion of the total product useEtchChambersCluster ToolConfigurationTransferChamberLoadlockWafersRIE ChamberTransferChamberGas InletExhaustRF PowerWaferp+ substratep-welln-channel transistorn-wellp-channel transistorsource-drain areasgate linewidthgate oxidePolysilicon Etches HB

25、r * C2F6 SF6 * NF3 * O2Aluminum Etches BCl3 * Cl2Diluents Ar He N2Chemical Reactions Silicon Etch: Si + 4 HBr SiBr4 + 2 H2 Aluminum Etch: Al + 2 Cl2 AlCl4Process Conditions Flow Rates: 100 to 300 sccm Pressure: 10 to 500 mTorr RF Power: 50 to 100 WattsDielectric Etch* High proportion of the total pr

26、oduct useEtchChambersCluster ToolConfigurationTransferChamberLoadlockWafersRIE ChamberTransferChamberGas InletExhaustRF PowerWaferContact locations n-wellp-channel transistorp-welln-channel transistorp+ substrateChemical Reactions Oxide Etch: SiO2 + C2F6 SiF4 + CO2 + CF4 + 2 COProcess Conditions Flo

27、w Rates: 10 to 300 sccm Pressure: 5 to 10 mTorr RF Power: 100 to 200 WattsPlasma Dielectric Etches CHF3 * CF4 C2F6 C3F8 CO *Diluents Ar He N2 CO2 O2 SF6 SiF4CleaningThin FilmsPhoto-lithographyCleaningFront-EndProcessesEtchIonImplantationPlanarizationTest &AssemblyDesignWaferPreparation Critical

28、Cleaning Photoresist Strips Pre-Deposition CleansCritical Cleaning1 12 23 34 45 51 Organics2 Oxides3 Particles4 Metals5 DryH2SO4 +HF +NH4OH +HCl +H2O or IPA +H2O2H2OH2O2 + H2OH2O2 + H2ON2H2O Rinse H2O Rinse H2O Rinse H2O RinseContact locations n-wellp-channel transistorp-welln-channel transistorp+ s

29、ubstrateRCA Clean SC1 Clean (H2O + NH4OH + H2O2) * * SC2 Clean (H2O + HCl + H2O2) *Piranha Strip * H2SO4 + H2O2 *Nitride Strip H3PO4 *Oxide Strip HF + H2O *Solvent Cleans NMP Proprietary Amines (liquid)Dry Cleans HF O2 Plasma Alcohol + O3Dry Strip N2O O2 CF4 + O2 O3Process Conditions Temperature: Pi

30、ranha Strip is 180 degrees C.Thin FilmsThin FilmsPhoto-lithographyCleaningFront-EndProcessesEtchIonImplantationPlanarizationTest &AssemblyDesignWaferPreparation Chemical Vapor Deposition (CVD) Dielectric CVD Tungsten Physical Vapor Deposition (PVD) Chamber CleaningChemical Vapor Deposition (CVD)

31、 Dielectric* High proportion of the total product useCVD Dielectric O2 O3 TEOS * TMP *TEOSSourceLPCVDChamberTransferChamberGas InletExhaustRF PowerWaferMeteringPumpInert MixingGasProcess GasVaporizerDirectLiquidInjectionn-wellp-channel transistorp-welln-channel transistorp+ substrateMetal 1insulator

32、 layer 2Chemical Reactions Si(OC2H5)4 + 9 O3 SiO2 + 5 CO + 3 CO2 + 10 H2OProcess Conditions (ILD) Flow Rate: 100 to 300 sccm Pressure: 50 Torr to Atmospheric Chemical Vapor Deposition (CVD) Tungsten* High proportion of the total product useCVD Dielectric WF6 * Ar H2 N2OutputCassetteInputCassetteWafe

33、rHanderWafersWater-cooledShowerheadsMultistation SequentialDeposition ChamberResistivelyHeated Pedestaln-wellp-channel transistorp-welln-channel transistorp+ substratetitaniumtungstenChemical Reactions WF6 + 3 H2 W + 6 HFProcess Conditions Flow Rate: 100 to 300 sccm Pressure: 100 mTorr Temperature:

34、400 degrees C.Physical Vapor Deposition (PVD)Barrier Metals SiH4 Ar N2 N2 Ti PVD Targets *PhysicalVaporDepositionChambersCluster ToolConfigurationTransferChamberLoadlockWafersPVD ChamberTransferChamberCryo PumpWaferNSN+e -BacksideHe CoolingArgon &NitrogenReactiveGasesDC PowerSupply (+)* High pro

35、portion of the total product usen-wellp-channel transistorp-welln-channel transistorp+ substrateProcess Conditions Pressure: 5 mTorr Temperature: 200 degrees C. RF Power:Chamber Cleaning* High proportion of the total product useChamber Cleaning C2F6 * NF3 ClF3Water-cooledShowerheadsMultistation Sequ

36、entialDeposition ChamberResistivelyHeated PedestalChemical Reactions Oxide Etch: SiO2 + C2F6 SiF4 + CO2 + CF4 + 2 COProcess Conditions Flow Rates: 10 to 300 sccm Pressure: 10 to 100 mTorr RF Power: 100 to 200 WattsAluminumSurface CoatingProcess Material ResidueChamber Wall Cross-SectionPlanarizationThin FilmsPhoto-lithographyCleaningFront-EndProcessesEtchIonImplantationPlanarizationTest &AssemblyDesignWaferPreparation Oxide Planarization Metal PlanarizationChemical Mechanical Planarization (CMP)* High proportion of the total product use.PlatenPolishin