【SoCVista】IC設(shè)計完全流程

1、Fully Custom IC Design FlowComposerHSPICELakerCalibreCalibreCalibreHSPICEICLab Layout1ICLabIC Fabrication Process OverviewWafer : 200 300 mm in diameter and about 0.35 1.25 mm thick Process steps : 20 30MasksOxidationLayoutDiffusionEtchProcessedChipsWafersChemicalwaferChemicalsIonvaporimplantationde

2、positionFabricationICLab Layout2ICLabIC Photolithographic ProcessApply material to wafer to be patterned Etch and apply specific processingMaterialstepWaferEtch awayunwantedmaterialSpin on positive photoresistPhotoresistMaterialWash off photoresistPattern photoresist with UV lightthrough glass maskP

3、atternedmaterialUV lightGlass maskChrome patternSolublephotoresistICLab Layout3ICLabCMOS P-Substrate Process FlowCross section viewSubstrateWellp substrateNMOS process stepsActive region, poly gate, p+/n+ implant, metal contact/linePMOS process stepsN well, active region, poly gate, p+/n+ implant, m

4、etal contact/lineICLab Layout4ICLabProcess Flow v.s. LayoutN well NWELL layer (NW)p substrateActive regionDIFF layer (OD)Well Contactp substrateICLab Layout5ICLabProcess Flow v.s. LayoutPoly gate (self-aligned gate)POLY1 layer (PO)p substratep substrateICLab Layout6ICLabProcess Flow v.s. LayoutP+/N+

5、 implant PIMP layer (PP)pppp substratenNIMP layer (NP)p substratep substratePolycide: silicide on polySalicide: self-aligned silicide on drain/sourceICLab Layout7ICLabProcess Flow v.s. LayoutMetal contacts/lines CONT layer (CO)Contact widowsp substrateMetal: Al or CuMETAL1 layer (M1)DGSWellP substra

6、teICLab Layout8ICLabProcess Flow v.s. LayoutMetal vias/lines VIA12 layer (VIA1)Via widowsP substrateMETAL2 layer (M2)P substrateICLab Layout9ICLabDesign Rule Check (DRC)Tolerate nonideal effects and guarantee device successful fabricationMask alignment errorEx: alignment of N well and active region

7、masksp substratep substratep substratep substrateICLab Layout10ICLabDesign Rule Check (DRC)Exposure and etching variationEx: different contact windowsdifferent contact resistanceContact widowsP substrate Two types of design rulesPoly overlapMinimumContactPoly-contactwidthoverlapspacingResolutionAlig

8、nmentICLab Layout11ICLabDesign Rule Check (DRC)Minimum channel width Minimize S/D diffusion width (xd)CO.W.1 + 2 × CO.E.1CO.W.1 + CO.E.1 + CO.C.1xdxdICLab Layout12ICLabLayout v.s. Schematic (LVS)Guarantee the fabricated circuits is the same as the simulated oneCheck device parametersModel nameC

9、hannel widthChannel lengthVDDVIVOGNDICLab Layout13ICLabParasitic Extraction (PEX)Evaluate interconnection RCeffectsVIVOVIVOGNDOnly C effectOnly R effectICLabICLab LayoutSubstrate and WellCMOS static logicNoise insensitiveUse substrate/well contact to providebody bias voltageSubstrate/well contact ne

10、eded but notimportant Analog circuits Noise sensitiveUse substrate/well contact to absorbnoise and provide body bias voltageGuard ringWell contactGuard ring(Avoid anycurrent flowsthrough it)Substrate contactICLab Layout15ICLabSubstrate and WellCMOS static logic Analog circuitsNoise insensitive Noise

11、 sensitiveShare N well for adjacent devicesSeparate N well for adjacent devicesReduce areaReduce coupling effectICLab Layout16ICLabInterconnectionCMOS static logicOnly consider RC delayUse minimum metal width Analog circuits Metal width is decided byCurrent densityoEx: 1 mA/µm for M1Parasitic r

12、esistanceoEx: M1 < 0.13 /squareParasitic capacitanceoEx: M1-Sub (0.4 µm width) 0.073 fF/µm| RC constantICLab Layout17ICLabInterconnectionCMOS static logic Analog circuitsContact/Via resistance is minor effect Contact/Via resistance may degradein RC delaycircuit performanceOne contact/vi

13、a can be used.At least two contact/viaCurrent densityEx: 0.6 mA/via for VIA12Contact widowsP substrateODCOM1ICLab Layout18ICLabCapacitanceCapacitance typesArea - Area area (W×L), 1/distance (1/d2) Fringe - Area length (L), 1/distance (1/d2) Fringe - Fringe length (L), 1/distance (1/d1)ICLab Lay

14、out19ICLabDouble-Poly CapacitorsPoly1-Poly2 capacitorEX: Ca = 864 aF/µm2Cf = 0.89 aF/µmPOLY2 layer (PO2)P substrateCtotal=Ca×W×L+Cf×(2W+2L)ICLab Layout20ICLabResistanceSheet resistance (ohm/square)Ex: RSH= 50 ohm/square50 ohm50 ohm50 ohm50 ohmLICLab Layout21RtotalL=×RSH

15、WICLabDiffusion ResistanceN+ diffusion resistorEX: RSH = 80±6.24 ohm/square Large parasitic capacitanceRPDUMMY layerP substrateICLab Layout22ICLabDiffusion ResistanceP+ diffusion resistorEX: RSH 150±16.8 ohm/square Large parasitic capacitanceP substrateICLab Layout23ICLabPoly ResistancePol

16、y2 resistorEX: RSH 50±9.24 ohm/square Small parasitic capacitanceP substrateICLab Layout24ICLabExercisePlease layout the following devices and pass the DRC verificationA PMOS device without guard ringPlease choose the channel width and channel length wisely.The total layout area should be as small as possible.The drain, gate, source, and body nodes should be at least contacted toMETAL1 layer.A NMOS device with guard ringChannel width = 10 µm, channel length = 0.5 µmLayout area should be no greater than 7 µm