發(fā)射電路時(shí)鐘電源

1、1發(fā)射電路設(shè)計(jì)、時(shí)鐘、電源發(fā)射電路設(shè)計(jì)、時(shí)鐘、電源2內(nèi)容nDigital-To-Analog ConverternBand-Pass FiltersnFrequency Up-ConverternRF Attenuator and GatenTune Mode3Digital-To-Analog ConverternU8 (DAC5687) is an ultra-fast dual-channel 16-bit DAC converting digital signal to RF signal. Two input channels get real-time digital signal

2、s from FPGA involving 4-phase selection, amplitude modulation, phase modulation, and frequency jumping.nThe digital input updating rate is 80 MHz. Inside the DAC, the digital signal is processed in 160 MHz. The process includes interpolation, frequency shift, digital filter, quadrature modulator cor

3、rection, gain adjustment, and unbalanced amplitude correction. All parameters are configurable by software through its serial channel.nThe DAC output updating rate is 160 MHz. The central IF frequency from two DACs outputs is 20 MHz. Two channels are working quadraturely.45Band-Pass FiltersnTwo RF t

4、ransformers T1 and T2 convert the current outputs to voltage. The two channel signals are filtered by two 3-pole symmetric band-pass filters to remove the harmonics and noise. The input and output impedance is 50 to match the DAC output and the frequency modulator input.67Frequency Up-ConverternU9 (

5、AD8345) is a quadrature frequency modulator. The operating frequency is from 140 MHz to 1000 MHz. It mixes the external frequency fLO with IF frequency fIF (20MHz) and generates the final transmitter frequency fTX. fTX = fLO - fIF.nThe quadrature modulator has single sideband output. The other sideb

6、and (fLO + fIF) is eliminated by choosing correct input phases. The external frequency source (PTS, for example) has to be set to fLO = fTX + fIF = fTX + 20 MHz.89nThe input level to the modulator is important to guarantee the minimum harmonics in its output. Therefore the external frequency source

7、should keep its output level within a range of +7dB (+/-2dB). T3 increases the common mode rejection, and D1 and D2 are for the input limiter.nU3 is a broadband RF amplifier with 12dB gain. C413, C414, C415, L51, L56, and L59 are constructed as a filter to further removing the harmonics.1011RF Atten

8、uator and GatenU4 and U5 (DAT-31R5-PN) are two stages of RF attenuator. Each stage has a range of attenuation from 0dB to 31.5dB with 0.5dB step. The total attenuation range is from 0dB to 63dB with 1dB step.nU10 and U11 (M3SWA-2-50) are two stages of RF gate. Each gate has isolation larger than 53d

9、B (DC -1000 MHz). The first stage of the gate (U10) also functions as a switch providing RF signals for probe tuning. U17 (HSWA2-30) is another RF gate switching tuning signals between two channels.nAn LED (D6) is the indicator for the RF gate on. It has an internal delay for obvious display if the

10、pulse is shorter than 50 ms.121314Tune ModenJ3 is the output for tuning. When the tune mode is selected (Console Mode Setting register), U17 output will pick one of the inputs, transmitter channel 1 or channel 2, as the tuning frequency. The channel is selected by the same register. nIn tune mode, t

11、he switchs U10 and U28 are close but U11 and U29 are open to block the RF output.nThe RF tuning level could be set by software. In tune mode, the LED indicator D8 will be blinking.1516System Clock-Clock SourcenAn ultra-high stabilization OCXO (Oven-Controlled-Crystal-Oscillator, U94) is used for the

12、 system clock source. The clock frequency is 80 MHz. It is fanout to different targets by U93 (NB3N551), an ultra-low skew clock buffer. U87 is a dual clock driver to convert the single-end signal to LVDS and drive the clock to FPGA and high speed ADC (AD6645). The clock traces on PCB is designed as

13、 a transmission line to match the impedance on PCB and both ends. Another destination of the U93 outputs is to ADC buffer (U40, 74ALVC16374).電路圖見(jiàn)電路圖見(jiàn)Wisdom-II_schematics P71718System Clock- Clock Reference OutputnTo synchronize external devices, PTS for example, a 10 MHz frequency source is provided

14、 as the reference. The 10 MHz frequency is derived from the system clock 80MHz. It has the same stability as the system clock. U81 and U88 (74LCX74) make three stages of the frequency divider. U91 (ERA-1SM) is an RF amplifier to provide 15 dBm (about 3.5Vpp) level output on J12 (rear panel).19Power SupplynTotally 12 different voltages are required in the console. They are