學習情境四乒乓球游戲機

1、EDA技術技術Electronic Design Automation 1 學習情境四：乒乓球游戲機學習情境四：乒乓球游戲機EDA技術技術Electronic Design Automation 2 主要內(nèi)容主要內(nèi)容項目任務項目任務項目目標項目目標實施步驟實施步驟相關知識相關知識評價與總結(jié)評價與總結(jié)綿陽職業(yè)技術學院綿陽職業(yè)技術學院 信息工程系信息工程系A. A. 項目任務項目任務EDA技術技術Electronic Design Automation 4 用用FPGAFPGA器件和器件和VHDLVHDL語言設計一個乒乓球游戲機，實現(xiàn)以下功能：語言設計一個乒乓球游戲機，實現(xiàn)以下功能：利用兩個按鍵作

2、為球拍，八只發(fā)光二極管的亮滅代表乒乓球運動的利用兩個按鍵作為球拍，八只發(fā)光二極管的亮滅代表乒乓球運動的軌跡。當一個按鍵按下時，乒乓球從一邊運動到另一邊（即發(fā)光二軌跡。當一個按鍵按下時，乒乓球從一邊運動到另一邊（即發(fā)光二極管從一邊依次閃爍到另一邊），當球到另一邊底線時按下另一個極管從一邊依次閃爍到另一邊），當球到另一邊底線時按下另一個按鍵，乒乓球反方向運動，遲按或早按按鍵都將判為失分，失分時按鍵，乒乓球反方向運動，遲按或早按按鍵都將判為失分，失分時由蜂鳴器報警，雙方的比分各由兩只數(shù)碼管顯示，另用一只數(shù)碼管由蜂鳴器報警，雙方的比分各由兩只數(shù)碼管顯示，另用一只數(shù)碼管閃爍表示比賽進行中，由一個撥碼開關

3、控制比賽的重新開始（比分閃爍表示比賽進行中，由一個撥碼開關控制比賽的重新開始（比分清零）清零）EDA技術技術Electronic Design Automation 5 B B 項目目標項目目標EDA技術技術Electronic Design Automation 6 C C 實施步驟實施步驟1系統(tǒng)功能分析系統(tǒng)功能分析根據(jù)任務要求，采用模塊化設計方法，乒乓球游戲機系根據(jù)任務要求，采用模塊化設計方法，乒乓球游戲機系統(tǒng)主要由以下幾個部分構(gòu)成：統(tǒng)主要由以下幾個部分構(gòu)成：speakerOUTPUTled7.0OUTPUTbainbbinclrclksouclkballout7.0countah3.0c

4、ountal3.0countbh3.0countbl3.0lampspeakertabletennisinstS3.0ABCDEFGHDELEDinst2clkS31.0daout3.0sel2.0seltimeinst1clkcoutcounter4800inst3clkcoutcounter1000hzinst5clkcoutcounter4hzinst6NOTinst12S7.4S3.0S19.16S8S23.20S31.0sel2.0OUTPUTEDA技術技術Electronic Design Automation 7 其中其中counter4800counter4800、counte

5、r4hzcounter4hz、counter1000hzcounter1000hz為分頻模為分頻模塊，主要功能是根據(jù)系統(tǒng)輸入主頻，進行分頻，以滿塊，主要功能是根據(jù)系統(tǒng)輸入主頻，進行分頻，以滿足主控模塊、聲音報警模塊和計分譯碼顯示模塊的需足主控模塊、聲音報警模塊和計分譯碼顯示模塊的需要。要。TabletennisTabletennis為主控模塊，根據(jù)兩個球拍（按鍵）為主控模塊，根據(jù)兩個球拍（按鍵）的動作情況，完成雙方的計分和報警控制，同時控制的動作情況，完成雙方的計分和報警控制，同時控制發(fā)光二極管的亮滅以表示乒乓球運動的軌跡，其余部發(fā)光二極管的亮滅以表示乒乓球運動的軌跡，其余部分為報警模塊和計分

6、譯碼顯示模塊，報警模塊根據(jù)主分為報警模塊和計分譯碼顯示模塊，報警模塊根據(jù)主控模塊的輸出驅(qū)動蜂鳴器報警，計分譯碼顯示模塊根控模塊的輸出驅(qū)動蜂鳴器報警，計分譯碼顯示模塊根據(jù)主控模塊的計分結(jié)果實現(xiàn)七段數(shù)碼管的譯碼和動態(tài)據(jù)主控模塊的計分結(jié)果實現(xiàn)七段數(shù)碼管的譯碼和動態(tài)顯示。顯示。EDA技術技術Electronic Design Automation 8 2 2分頻模塊分頻模塊設計設計1 1）counter480counter4800 0library ieee;use ieee.std_logic_1164.all;entity counter4800 isport( clk : in std_logi

7、c; cout : out std_logic);end counter4800;architecture behav of counter4800 isbeginprocess(clk)variable i: integer range 0 to 4800;beginif i=4800 theni:=0;cout=1;elsif clkevent and clk=1 theni:=i+1;if i=2400 thencout=0;end if;end if;end process;end behav;EDA技術技術Electronic Design Automation 9 2 2）coun

8、ter4hzcounter4hz library ieee;use ieee.std_logic_1164.all;entity counter4hz isport( clk : in std_logic; cout : out std_logic);end counter4hz;architecture behav of counter4hz isbeginprocess(clk)variable i: integer range 0 to 3000000;beginif i=3000000 theni:=0;cout=1;elsif clkevent and clk=1 theni:=i+

9、1;if i=1500000 thencout=0;end if;end if;end process;end behav; EDA技術技術Electronic Design Automation 10 3 3）counter1000hzcounter1000hz library ieee;use ieee.std_logic_1164.all;entity counter1000hz isport( clk : in std_logic; cout : out std_logic);end counter1000hz;architecture behav of counter1000hz i

10、sbeginprocess(clk)variable i: integer range 0 to 12000;beginif i=12000 theni:=0;cout=1;elsif clkevent and clk=1 theni:=i+1;if i=6000 thencout=0;end if;end if;end process;end behav;EDA技術技術Electronic Design Automation 11 3 3主控模塊設計主控模塊設計主控模塊采用層次化主控模塊采用層次化設計方法，底層由設計方法，底層由soundsound、ballctrlballctrl、ball

11、ball、boardboard、cou10cou10、cou4cou4、mwaymway等七個子模塊構(gòu)等七個子模塊構(gòu)成成 library ieee;use ieee.std_logic_1164.all;entity tabletennis isport(bain,bbin,clr,clk,souclk:in std_logic; ballout:out std_logic_vector(7 downto 0); countah,countal,countbh,countbl : out std_logic_vector(3 downto 0); lamp,speaker : out std_

12、logic);end;architecture ful of tabletennis iscomponent soundport (clk,sig,en :in std_logic; sout : out std_logic);end component;component ballctrlport (clr,bain,bbin,serclka,serclkb,clk :in std_logic; bdout,serve,serclk,ballclr,ballen : out std_logic);end component;component ballport (clk,clr,way,en

13、 :in std_logic; ballout : out std_logic_vector(7 downto 0);end component;EDA技術技術Electronic Design Automation 12 component boardcomponent boardport (port (ball,net,bclk,serveball,net,bclk,serve :in :in std_logicstd_logic; ; couclk,serclkcouclk,serclk : out : out std_logicstd_logic); );end component;e

14、nd component;component cou10component cou10port (port (clk,clr:inclk,clr:in std_logicstd_logic; ; coutcout : out : out std_logicstd_logic; ; qoutqout : out std_logic_vector(3 : out std_logic_vector(3 downtodownto 0); 0);end component;end component;component cou4port (clk,clr:in std_logic; cout : out

15、 std_logic; qout : out std_logic_vector(3 downto 0);end component;component mwayport (servea,serveb:in std_logic; way : out std_logic);end component;EDA技術技術Electronic Design Automation 13 ?signal net,couclkah,couclkal,couclkbh,couclkbl,cah,cbh : std_logic;signal serve,serclka,serclkb,serclk,ballclr,

16、bdout,way,ballen : std_logic;signal bbll : std_logic_vector(7 downto 0);beginnet=bbll(4); ballout=bbll; lamp=clk;uah : cou4 port map (couclkah,clr,cah,countah);ual : cou10 port map (couclkal,clr,couclkah,countal);ubh : cou4 port map (couclkbh,clr,cbh,countbh);ubl : cou10 port map (couclkbl,clr,coucl

17、kbh,countbl);ubda : board port map (bbll(0),net,bain,serve,couclkal,serclka);ubdb : board port map (bbll(7),net,bbin,serve,couclkbl,serclkb);ucpu : ballctrl port map (clr,bain,bbin,serclka,serclkb,clk,bdout,serve,serclk,ballclr,ballen);uway : mway port map (serclka,serclkb,way);uball : ball port map

18、 (clk,ballclr,way,ballen,bbll);usound : sound port map (souclk,ballen,bdout,speaker);end;EDA技術技術Electronic Design Automation 14 library ieee;use ieee.std_logic_1164.all;entity sound isport (clk,sig,en :in std_logic; sout : out std_logic);end sound;architecture ful of sound isbegin sout=clk and (not

19、sig) and en;end;EDA技術技術Electronic Design Automation 15 library ieee;use ieee.std_logic_1164.all;entity ballctrl isport (clr,bain,bbin,serclka,serclkb,clk :in std_logic; bdout,serve,serclk,ballclr,ballen : out std_logic);end ballctrl;architecture ful of ballctrl issignal bd : std_logic;signal ser : s

20、td_logic;beginbd=bain or bbin;ser=serclka or serclkb;serclk=ser;bdout=bd;process(clr,clk,bd)beginif (clr=1) then serve=1; ballclr=1;else if(bd=1) then ballclr=1; if (ser=1) then ballen=1; serve=0; else ballen=0; serve=1; end if; else ballclr=0; end if ;end if ;end process;end;EDA技術技術Electronic Desig

21、n Automation 16 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ball isport (clk,clr,way,en :in std_logic; ballout : out std_logic_vector(7 downto 0);end ball;architecture ful of ball issignal lamp : std_logic_vector(9 downto 0);beginprocess(clk,clr,en)beginif (clr=1)

22、 thenlamp=1000000001; elsif en=0 then elsif (clkevent and clk=1) then if (way=1) then lamp(9 downto 1)=lamp(8 downto 0); lamp(0)=0; else lamp(8 downto 0)=lamp(9 downto 1); lamp(9)=0; end if;end if;ballout=lamp(8 downto 1);end process;end;EDA技術技術Electronic Design Automation 17 library ieee;use ieee.s

23、td_logic_1164.all;entity board isport (ball,net,bclk,serve :in std_logic; couclk,serclk : out std_logic);end board;architecture ful of board isbeginprocess(bclk,net)beginif (net=1)then serclk=0; couclk=0;elsif(bclkevent and bclk=1)then if (serve=1)then serclk=1; else if (ball=1)then serclk=1; else s

24、erclk=0; couclk=1; end if ; end if;end if;end process;end;EDA技術技術Electronic Design Automation 18 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cou10 isport (clk,clr:in std_logic; cout : out std_logic; qout : out std_logic_vector(3 downto 0);end cou10;architecture fu

25、l of cou10 issignal qqout: std_logic_vector(3 downto 0);begin process(clr,clk)beginif (clr=1) then qqout=0000;cout1000)then qqout=0000; cout=1; else qqout=qqout+1; cout=0; end if;end if;qout=qqout;end process;end;EDA技術技術Electronic Design Automation 19 library ieee;use ieee.std_logic_1164.all;use iee

26、e.std_logic_unsigned.all;entity cou4 isport (clk,clr:in std_logic; cout : out std_logic; qout : out std_logic_vector(3 downto 0);end cou4;architecture ful of cou4 issignal qqout: std_logic_vector(3 downto 0);begin process(clr,clk)beginif (clr=1) then qqout=0000;cout0010)then qqout=0000; cout=1; else

27、 qqout=qqout+1; cout=0; end if;end if;qout=qqout;end process;end;EDA技術技術Electronic Design Automation 20 library ieee;use ieee.std_logic_1164.all;entity mway isport (servea,serveb:in std_logic; way : out std_logic);end mway;architecture ful of mway isbeginprocess(servea,serveb)beginif(servea=1)then w

28、ay=1;elsif(serveb=1)thenway=0;end if; end process;end;EDA技術技術Electronic Design Automation 21 4 4計分譯碼顯示模塊設計計分譯碼顯示模塊設計計分譯碼顯示模塊包括動態(tài)顯示控制和七段數(shù)碼管譯碼兩個部計分譯碼顯示模塊包括動態(tài)顯示控制和七段數(shù)碼管譯碼兩個部分分.EDA技術技術Electronic Design Automation 22 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity seltime

29、isport( clk : in std_logic; S : in std_logic_vector(31 downto 0); daout: out std_logic_vector(3 downto 0); sel : out std_logic_vector(2 downto 0);end seltime;architecture behav of seltime issignal sec : std_logic_vector(2 downto 0);beginprocess(clk)beginif(clkevent and clk=1) then if(sec=111) then s

30、ec=000;else secdaoutdaoutdaoutdaoutdaoutdaoutdaoutdaoutdaout=XXXX;end case;end process;sel=sec;end behav;EDA技術技術Electronic Design Automation 24 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DELED ISPORT( S: IN STD_LOGIC_VECTOR(3 DOWNTO 0); A,B,C,D,E,F,G,H: OUT STD_LOGIC);END DELED;ARCHITECTURE BEH

31、AV OF DELED ISSIGNAL DATA:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL DOUT:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINDATADOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUT=00000000;END CASE;END PROCESS;H=DOUT(7);G=DOUT(6);F=DOUT(5);E=DOUT(4);D=DOUT(3);C=DOUT(2);B=DOUT(1);A ADD,lpm_representation =

32、 SIGNED, lpm_pipeline = 0, lpm_width = DATA_WIDTH) port map(dataa=a, datab=b, result=y);end rtl;EDA技術技術Electronic Design Automation 40 仿真波形如圖所示仿真波形如圖所示EDA技術技術Electronic Design Automation 41 二、通過二、通過MegaWizardPlugMegaWizardPlug-In Manager -In Manager 例化例化LPMLPM下面我們利用下面我們利用MegaWizardPlugMegaWizardPlug

33、-In Manager-In Manager方法例化方法例化LPMLPM，創(chuàng)建一個創(chuàng)建一個3232位有符號加法器位有符號加法器. .EDA技術技術Electronic Design Automation 42 打開打開MegaWizardPlugMegaWizardPlug-In Manager-In Manager（Tools-Tools-MegaWizardMegaWizard Plug-in Plug-in ManagerManager） EDA技術技術Electronic Design Automation 43 EDA技術技術Electronic Design Automation

34、44 EDA技術技術Electronic Design Automation 45 EDA技術技術Electronic Design Automation 46 EDA技術技術Electronic Design Automation 47 EDA技術技術Electronic Design Automation 48 EDA技術技術Electronic Design Automation 49 EDA技術技術Electronic Design Automation 50 EDA技術技術Electronic Design Automation 51 EDA技術技術Electronic Design

35、 Automation 52 - megafunction wizard: %LPM_ADD_SUB% - GENERATION: STANDARD - VERSION: WM1.0 - MODULE: lpm_add_sub - = - File Name: lpm_add32_2.vhd - Megafunction Name(s): - lpm_add_sub - - Simulation Library Files(s): - lpm - = - * - THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! - - 8.1 Bu

36、ild 163 10/28/2008 SJ Full Version - *EDA技術技術Electronic Design Automation 53 -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporations design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing

37、 -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable a