美新加速度傳感器角度傳感器I2C總線

1、MXC6202xGHMN 是低成本、雙軸加速度計，芯片具有混合信號處理功能和集成式IIC總線，允許該設備直接連接到微處理器?？梢酝瑫r測量動態(tài)加速度（如振動）和靜態(tài)加速度（如重力）。分辨率優(yōu)于1mg（g為重力加速度），量程2g。它輸出即為數(shù)字量，所以省去了模數(shù)轉換所需的硬件和時間，數(shù)字量輸出方式為IIC總線?？偟膩碚f使用該傳感器可以電路硬件簡化。MXC6202各引腳定義如圖：從美新提供的說明書來看芯片外圍電路也很簡單，主要包括的供電部分，IIC總線的上拉電阻和電源去噪部分。電源去噪可使用0.1uF的電容，IIC上拉電阻10k即可。供電部分可使用1N4728a穩(wěn)壓管，測量顯示串聯(lián)電阻為20-50時

2、穩(wěn)壓管端電壓為3V左右。應用電路如圖：MXC6202xx說明書數(shù)據(jù)通信部分的簡單翻譯并沒有完全依照原文翻譯，中間加入了一些內容，部分專業(yè)術語很可能用錯了，將就一下吧。下文中主機指IIC通信主設備（以51單片機為例，型號為STC89C54RD+），從機即IIC從設備指美新加速度計，型號為MXC62020G。數(shù)據(jù)通信示例：第一周期：主機發(fā)出START指令，然后發(fā)送從機地址0010xxx包含寫信號（第8時鐘脈沖，SDA保持低電平，其實就是發(fā)送信號0010xxx0）。xxx（地址位）已由工廠編程決定，一共有8種不同的可用地址。（xxx從芯片的型號標識C6202xx中前一個x可以看出，具體見附圖1。我手

3、中的芯片為C62020G，對應xxx是000）第二周期：主機接收到應答信號（芯片在第9個時鐘脈沖期間保持SDA為低電平）后，主機發(fā)送00000000作為被寫入數(shù)據(jù)的地址。從機應當在結束時發(fā)出應答信號（從機在第9個時鐘脈沖期間保持SDA為低電平，以下提到的應答信號非特殊說明均為此種含義）。注意：因為美新的此種芯片只有一個可被寫入的內部寄存器，使用者應當只聲明00000000作為寫入地址。第三周期：主機向從機寫入代碼xxxxxxx0作為喚醒信號，從機應答，使用STOP指令結束寫入過程。等待75ms以便從機從低能耗模式回到正常模式，等待時間由從機型號決定，一般來說，低功耗產(chǎn)品需要比較長的喚醒時間。第

4、四周期：主機發(fā)送START指令，然后發(fā)送從機地址包含寫信號（參照第一周期）。從機發(fā)出應答信號作為結尾。第五周期：主機向從機寫代碼00000000作為內部寄存器被讀取的開始地址，從這個地址開始的讀取可以作為操作驗證并用于確認寫入指令是成功的。注意：開始地址原則上可以是5個地址中的一個（這五個地址見附圖2）。例如使用者可以從地址00000001開始讀取，該地址是X方向數(shù)據(jù)的高8位。從機應答。另，因為第六周期發(fā)送地址信號是0010xxx1,與先前的0010xxx0不同，主機需要再發(fā)送一次START指令（原文中沒有提到這一點）。第六周期：主機發(fā)送從機地址包含讀信號（第8時鐘脈沖，SDA保持高電平，其實

5、就是發(fā)送信號0010xxx1）。從機應答（從機在第9時鐘脈沖時保持SDA為低電平）。第七周期：主機控制時鐘脈沖，內部寄存器第一個地址上的數(shù)據(jù)出現(xiàn)在SDA線上，如果在第五周期（原文中為step 7，懷疑是打錯了）寫入的代碼是00000000，出現(xiàn)的應該是內部控制寄存器數(shù)據(jù)，從機應答。第八周期：主機繼續(xù)控制時鐘脈沖，內部寄存器的下一字節(jié)數(shù)據(jù)出現(xiàn)在SDA線上(X方向數(shù)據(jù)的高8位)，內部寄存器指針會自動移向下一字節(jié)。主機應答。第九周期：X方向的低8位。主機應答。如果內部控制寄存器的TEON位已被設為1，則上面兩個周期出現(xiàn)的應當是TOUT（溫度）的高8位和低8位。第十周期：Y方向數(shù)據(jù)的高8位。主機應答。

6、第十一周期：Y方向數(shù)據(jù)的低8位。主機發(fā)送非應答信號（主機在一個時鐘脈沖期間保持SDA為高電平）后發(fā)出STOP指令以結束通信。注意：如果主機繼續(xù)控制時鐘脈沖，內部寄存器指針將到達第6和第7的位置，which always have 00000000(這個看不懂)。第7個位置之后，指針將回到0位置注意：主機通過寫入內部控制寄存器數(shù)據(jù)使從機進入低能耗模式。原文：EXAMPLE OF DATA COMMUNICATION First cycle: START followed by a calling to slave address 0010xxx to WRITE (8th SCL, SDA ke

7、ep low). xxx Is determined by factory programming, a total of 8 different addresses are available. Second cycle: After an acknowledge signal is received by the master device (Memsic device pulls SDA line low during 9th SCL pulse), master device sends “00000000” as the target address to be written in

8、to. Memsic device should acknowledge at the end (9th SCL pulse). Note: since Memsic device has only one internal register that can be written into, user should always indicate “00000000” as the write address. Third cycle: Master device writes to internal Memsic device memory code “xxxxxxx0” as a wak

9、e-up call. The Memsic device should send acknowledge signal. A STOP command indicates the end of write operation. A 75msS (typical) wait period should be given to Memsic device to return from a power-down mode. The delay value depends on the type of Memsic device. Generally speaking, low power produ

10、cts tend to have longer startup time. Fourth cycle: Master device sends a START command followed by calling Memsic device address with a WRITE (8th SCL, SDA keep low). An “acknowledge” should be sent by Memsic device at the end. Fifth cycle: Master device writes to Memsic device a “00000000” as the

11、starting address for which internal memory is to be read. Since “00000000” is the address of internal control register, reading from this address can serve as a verification of operation and to confirm the write command has been successful. Note: the starting address in principle can be any of the 5

12、 addresses. For example, user can start read from address 0000001, which is X channel MSB. Sixth cycle: Master device calls Memsic device address with a READ (8th SCL cycle SDA line high). Memsic device should acknowledge at the end. Seventh cycle: Master device cycles SCL line, first addressed memo

13、ry data appears on SDA line. If in step 7, “00000000” was sent, internal control register datashould appear (in the following steps, this case is assumed). Master device should send acknowledge at the end. Eighth cycle: Master device continues cycle SCL line, next byte of internal memory should appe

14、ar on SDA line (MSB of X channel). The internal memory address pointer automatically moves to the next byte. Master acknowledges. Ninth cycle: LSB of X channel. In the case that TOEN bit of internal register was set to “1”, the MSB and LSB of TOUT (temperature) should appear in last two steps. Tenth

15、 cycle: MSB of Y channel. Eleventh cycle: LSB of Y channel. Master ends communications by sending NO acknowledge and followed by a STOP command. Note: if mater device continues to cycle SCL line, the memory pointer will go to sixth and seventh positions, which always have “00000000”. After seventh p

16、osition, pointer will go to zero again. Optional: Master powers down Memsic device by writing into internalcontrol register. (See step 1 through 4 for WRITE operation) 美新MXC6202加速度計數(shù)據(jù)的讀取和顯示 C程序2010-06-16 20:45#include#include /需要用到求絕對值函數(shù)#define uchar unsigned char#define uint unsigned intfloat xg,yg

17、;uchar str0=X-X:;uchar str1=Y-Y:;uchar s=0123;sbitsda=P21;sbitscl=P20;sbitlcdrs=P24;sbitlcden=P26;sbitlcdrw=P25;sbitleden=P37;/*/*定義兩個延時函數(shù)，一個微妙級，一個毫秒級*/void delay() ; ; void delayms(uint z) uinti,j; for(i=z;i0;i-) for(j=115;j0;j-);/*/*LCD的寫指令，寫數(shù)據(jù)，定點插入及初始化*/void lcd_write_com(uchar com) delayms(5); l

18、cdrs=0; P0=com; lcden=1; delay(); lcden=0; void lcd_write_data(uchar date) delayms(5); lcdrs=1; P0=date; lcden=1; delay(); lcden=0; void lcd_row_column_vector_len(ucharrow,ucharcolumn,uchar *vector,ucharlen) ucharposition,cnt; position=128+row*64+column; lcd_write_com(position); for(cnt=0;cntlen;cnt

19、+) lcd_write_data(*vector); vector+; void LCD_init()leden=1;P0=0x00;delay();leden=0; /*我使用的是DY_mini80型學習板，這四步程序是為了關閉數(shù)碼管的顯示功能*/ lcden=0; lcdrw=0; lcd_write_com(0x38); lcd_write_com(0x0c); lcd_write_com(0x06); lcd_write_com(0x01); lcd_row_column_vector_len(0,0,str0,4); lcd_row_column_vector_len(1,0,st

20、r1,4);void start() sda=1; delay(); scl=1; delay(); sda=0; delay(); scl=0; delay();void stop() sda=0; delay(); scl=1; delay(); sda=1; delay();void ack() uchar i; scl=1; delay(); while(sda=1)&(i25)i+; scl=0; delay();void write_byte(uchar date) uchari,temp; temp=date; for(i=0;i8;i+) temp=temp1; scl=0;

21、delay(); sda=CY; delay(); scl=1; delay(); scl=0; scl=0; delay(); sda=1; delay();ucharread_byte() uchari,k; scl=0; delay(); sda=1; delay(); for(i=0;i8;i+) scl=1; delay(); k=(k1)|sda; scl=0; delay(); return k;void acknowledge(uchar a) /*主機應答程序 acknowledge（0）為應答，acknowledge（1）為非應答*/ if(a=0)sda=0;elsesd

22、a=1;delay(); scl=1; delay();scl=0;delay();void MXC_init() start(); /*對應數(shù)據(jù)通信示例的第一至第三周期*/ write_byte(0x20); ack(); write_byte(0x00); ack(); write_byte(0xf0); ack(); stop(); delayms(75);/*/*獲取4個字節(jié)的數(shù)據(jù)*/void receive5bytes() uchar i; start(); write_byte(0x20); /對應數(shù)據(jù)通信示例的第四周期 ack(); write_byte(0x01); /第五周期 ack();start(); write_byte(0x21); /第六周期 ack();for(i=0;i3;i+) /第八至十周期（第七周期省略） si=read_byte(); acknowledge(0); s3=rea