[信息與通信]vhdl考試程序總結(jié)

1、.64位計(jì)數(shù)器12計(jì)時(shí)器83. 波形94顯示譯碼器105. 表決器117四選一148譯碼器149奇偶校正1610 移位寄存器1711 四位減法2012 選擇器2213 循環(huán)顯示135792213 轉(zhuǎn)換成bcd嗎2314 走馬燈2415 全加器2516 8421 BCD碼轉(zhuǎn)換為余3碼電路2717 觸發(fā)器2818 編碼器3264位計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;USE IEEE.STD_LOGIC_ARITH.ALL;entity mchcounter isport(clk,cl

2、r,s,en,updn:in std_logic; d:in integer range 0 to 63; m: in integer range 0 to 63;co:out std_logic;q:buffer integer range 0 to 63);end mchcounter;architecture a1 of mchcounter is-定義計(jì)數(shù)最大值mtempsignal m_temp:integer range 0 to 63;beginprocess(clk,clr,m)beginm_temp<=m-1;-清零功能if clr='1' then q

3、<=0;co<='0'-以時(shí)鐘信號(hào)的上升沿為計(jì)數(shù)觸發(fā)器條件elsif clk'event and clk='1'then-置數(shù)功能if s='1' then q<=d;-防止計(jì)數(shù)時(shí)失控elsif q>m_temp then q<=m_temp;-計(jì)數(shù)使能控制功能elsif en='1' then if updn='1' then -計(jì)數(shù)加法if q=m_temp then q<=0;co<='1'else q<=q+1;co<='

4、0'end if; elsif updn='0' then -計(jì)數(shù)減法 if q=0 then q<=m_temp;co<='1' else q<=q-1;co<='0'end if; end if;end if;end if;end process;end a1;-(1)clk為時(shí)鐘信號(hào)，由時(shí)鐘信號(hào)的上升沿觸發(fā)計(jì)數(shù)；-(2)m為模值輸入端，當(dāng)其變化時(shí)，計(jì)數(shù)容量相應(yīng)發(fā)生變化?-(3)clr為清零控制端，當(dāng)其為高電平時(shí)清零?-(4)s為置數(shù)控制端，當(dāng)其為高電平時(shí)將置數(shù)輸入端d的數(shù)據(jù)加載到輸出端q；-(5)en為使能控

5、制端，當(dāng)其為高電平時(shí)正常計(jì)數(shù)，當(dāng)其為低電平時(shí)暫停計(jì)數(shù)；-(6)updn為計(jì)數(shù)方向控制端，當(dāng)其為高電平時(shí)計(jì)數(shù)器加法計(jì)數(shù)，當(dāng)其為低電平時(shí)計(jì)數(shù)器減法計(jì)數(shù)。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY scount IS PORT (CLK : IN STD_LOGIC; RST : IN STD_LOGIC; ENA : IN STD_LOGIC; OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END s

6、count;ARCHITECTURE behav OF scount IS SIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINP_REG: PROCESS(CLK, RST, ENA) BEGIN IF RST = '1' THEN CQI <= "0000" ELSIF CLK'EVENT AND CLK = '1' THEN IF ENA = '1' THEN CQI <= CQI + 1; ELSE CQI <= "0000" EN

7、D IF; END IF; OUTY <= CQI ;END PROCESS P_REG ;COUT <= CQI(0) AND CQI(1) AND CQI(2) AND CQI(3); END behav;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY yibujishu IS PORT(CLK:IN STD_LOGIC; COUNT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY yibujishu;ARCHITECTURE ART2 OF yibujishu IS SIGNAL C

8、OUNT_IN_BAR:STD_LOGIC_VECTOR(4 DOWNTO 0); COMPONENT D_ff IS PORT(CLK,D:IN STD_LOGIC; Q,nq:OUT STD_LOGIC); END COMPONENT; BEGIN COUNT_IN_BAR(0)<=CLK; GEN1:FOR I IN 0 TO 3 GENERATE U:D_ff PORT MAP (CLK=>COUNT_IN_BAR(I), D=>COUNT_IN_BAR(I+1),Q=>COUNT(I),nq=>COUNT_IN_BAR(I+1); END GENERAT

9、E; END ARCHITECTURE ART2;高級(jí)計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;USE IEEE.STD_LOGIC_ARITH.ALL;entity mchcounter isport(clk,clr,s,en,updn:in std_logic; d:in integer range 0 to 63; m: in integer range 0 to 63;co:out std_logic;q:buffer integer range 0 to 63);end mc

10、hcounter;architecture a1 of mchcounter is-定義計(jì)數(shù)最大值mtempsignal m_temp:integer range 0 to 63;beginprocess(clk,clr,m)beginm_temp<=m-1;-清零功能if clr='1' then q<=0;co<='0'-以時(shí)鐘信號(hào)的上升沿為計(jì)數(shù)觸發(fā)器條件elsif clk'event and clk='1'then-置數(shù)功能if s='1' then q<=d;-防止計(jì)數(shù)時(shí)失控elsif q&

11、gt;m_temp then q<=m_temp;-計(jì)數(shù)使能控制功能elsif en='1' then if updn='1' then -計(jì)數(shù)加法if q=m_temp then q<=0;co<='1'else q<=q+1;co<='0'end if; elsif updn='0' then -計(jì)數(shù)減法 if q=0 then q<=m_temp;co<='1' else q<=q-1;co<='0'end if; end

12、if;end if;end if;end process;end a1;-(1)clk為時(shí)鐘信號(hào)，由時(shí)鐘信號(hào)的上升沿觸發(fā)計(jì)數(shù)；-(2)m為模值輸入端，當(dāng)其變化時(shí)，計(jì)數(shù)容量相應(yīng)發(fā)生變化?-(3)clr為清零控制端，當(dāng)其為高電平時(shí)清零?-(4)s為置數(shù)控制端，當(dāng)其為高電平時(shí)將置數(shù)輸入端d的數(shù)據(jù)加載到輸出端q；-(5)en為使能控制端，當(dāng)其為高電平時(shí)正常計(jì)數(shù)，當(dāng)其為低電平時(shí)暫停計(jì)數(shù)；-(6)updn為計(jì)數(shù)方向控制端，當(dāng)其為高電平時(shí)計(jì)數(shù)器加法計(jì)數(shù)，當(dāng)其為低電平時(shí)計(jì)數(shù)器減法計(jì)數(shù)。十二位計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_log

13、ic_unsigned.all;entity count12 isport (CR,LD,CLK: in std_logic;QIN: in std_logic_vector(3 downto 0); - zhi shu QOUT: out std_logic_vector(3 downto 0); end count12;architecture one of count12 isbeginprocess(CLK)variable tma: std_logic_vector(3 downto 0);beginif CR='0' thentma:="0000"

14、;elsif CLK'event and CLK='1' thenif LD='0' then tma:=QIN;end if;if LD='1' thenif tma="1100" then tma:="0000"else tma:=tma+1;end if;end if;end if;QOUT<=tma;end process;end one;選擇計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.

15、all;entity sel_clock is port(ckdsp:in std_logic;a,b:in std_logic_vector(3 downto 0);num:out std_logic_vector(3 downto 0);end;architecture a4 of sel_clock issignal cnt8:std_logic_vector(2 downto 0);beginp1:process(cnt8) begin case cnt8 is when "000"=> num<=a; when "001"=>

16、 num<=b; when others =>null; end case; end process p1;p2:process(ckdsp) begin if ckdsp'event and ckdsp='1' then cnt8<=cnt8+1; end if; if cnt8="010" then cnt8<="000" end if; end process p2;end;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSI

17、GNED.ALL;ENTITY COUNT10 IS PORT(CLK,R,S:IN STD_LOGIC;DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);CO:OUT STD_LOGIC;Q:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);END COUNT10;ARCHITECTURE test OF COUNT10 ISBEGINCO<='1' WHEN (Q="1001") ELSE '0'PROCESS(CLK,R)BEGINIF (R='0') THEN Q&l

18、t;="0000"ELSIF (CLK'EVENT AND CLK='1') THENIF(S='1') THEN Q<=DATA;ELSIF (Q=9) THEN Q<="0000"ELSE Q<=Q+1;END IF;END IF;END PROCESS;END test;2計(jì)時(shí)器 異步計(jì)數(shù) ARCHITECTURE ART2 OF yibujishu IS SIGNAL COUNT_IN_BAR:STD_LOGIC_VECTOR(4 DOWNTO 0); COMPONENT D_ff IS

19、PORT(CLK,D:IN STD_LOGIC; Q,nq:OUT STD_LOGIC); END COMPONENT; BEGIN COUNT_IN_BAR(0)<=CLK; GEN1:FOR I IN 0 TO 3 GENERATE U:D_ff PORT MAP (CLK=>COUNT_IN_BAR(I), D=>COUNT_IN_BAR(I+1),Q=>COUNT(I),nq=>COUNT_IN_BAR(I+1); END GENERATE; END ARCHITECTURE ART2;3. 波形library ieee;use ieee.std_logi

20、c_1164.all;use ieee.std_logic_unsigned.all;entity aquare_gen is port(clk:in std_logic; input:in std_logic_vector(6 downto 0); q:out std_logic);end aquare_gen;architecture a of aquare_gen is signal ff:bit;beginprocess(clk)variable num:integer range 0 to 100;beginif clk'event and clk='1' t

21、hen if num<input then ff<='1' num:=num+1; elsif num<100 then num:=num+1; ff<='0' else num:=0; end if;end if;end process;process(clk)begin if clk'event and clk='1' then if ff='1' then q<='1' else q<='0' end if; end if;end process;e

22、nd a;4顯示譯碼器八段LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY deled IS PORT( NUM:IN STD_LOGIC_VECTOR(3 DOWNTO 0); SG :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END;ARCHITECTURE ONE OF deled ISBEGINPROCESS(NUM)BEGINCASE NUM ISWHEN "0000"=>SG<="0111111"W

23、HEN "0001"=>SG<="0000110"WHEN "0010"=>SG<="1011011"WHEN "0011"=>SG<="1001111"WHEN "0100"=>SG<="1100110"WHEN "0101"=>SG<="1101101"WHEN "0110"=>SG<="11

24、11101"WHEN "0111"=>SG<="0000111"WHEN "1000"=>SG<="1111111"WHEN "1001"=>SG<="1101111"WHEN "1010"=>SG<="1000000"WHEN OTHERS=>NULL;END CASE;END PROCESS;END;七段 library ieee; use ieee.std_logic

25、_1164.all; entity yima is port(d0,d1,d2,d3:in std_logic;a,b,c,d,e,f,g:out std_logic); end yima; architecture behav of yima is signal m: std_logic_vector(3 downto 0); signal seg7:std_logic_vector(6 downto 0); begin m<=d3&d2&d1&d0;WITH m SELECTseg7<="0111111" when "000

26、0" , "0000110" when "0001" , "1011011" when "0010" , "1001111" when "0011" , "1100110" when "0100" , "1101101" when "0101" , "1111101" when "0110" , "0000111" when &

27、quot;0111" , "1111111" when "1000" , "1100111" when "1001" , "1110111" when "1010" , "1111100" when "1011" , "0111001" when "1100" , "1011110" when "1101" , "1111001"

28、; when "1110" , "1110001" when "1111" , "0000000" when others; g<=seg7(6); f<=seg7(5); e<=seg7(4); d<=seg7(3); c<=seg7(2); b<=seg7(1); a<=seg7(0); end behav;5. 表決器表決器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;

29、ENTITY BIAOJUE ISPORT( CLK:IN STD_LOGIC; A,B,C,D,E:IN STD_LOGIC; COU:OUT STD_LOGIC); END; ARCHITECTURE ONE OF BIAOJUE ISSIGNAL CNT:STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL ZH:STD_LOGIC;SIGNAL ZH1:STD_LOGIC;BEGIN PROCESS(CLK,A,B,C,D,E)VARIABLE CNT_LB:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINIF CLK'EVENT AND

30、CLK='1' THEN CNT_LB:=CNT_LB+1;IF CNT_LB<"10" THEN ZH1<='1' -喇叭響-ELSE ZH1<='0'END IF;END IF;CNT<=A&B&C&D&E; CASE CNT ISWHEN "00000" => ZH<='0'WHEN "00001" => ZH<='0'WHEN "00010" =&g

31、t; ZH<='0'WHEN "00100" => ZH<='0'WHEN "01000" => ZH<='0'WHEN "10000" => ZH<='0'WHEN "00011" => ZH<='0'WHEN "00110" => ZH<='0'WHEN "01100" => ZH<='0&#

32、39;WHEN "11000" => ZH<='0'WHEN "10001" => ZH<='0'WHEN "10010" => ZH<='0'WHEN "10100" => ZH<='0'WHEN "01001" => ZH<='0'WHEN "01010" => ZH<='0'WHEN "0010

33、1" => ZH<='0'WHEN OTHERS=>ZH<='1'END CASE; END PROCESS ;COU<=ZH AND ZH1;END;6，二選一 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity sel_clock is port(ckdsp:in std_logic;a,b:in std_logic_vector(3 downto 0);num:out std_logic_vector(3 do

34、wnto 0);end;architecture a4 of sel_clock issignal cnt8:std_logic_vector(2 downto 0);beginp1:process(cnt8) begin case cnt8 is when "000"=> num<=a; when "001"=> num<=b; when others =>null; end case; end process p1;p2:process(ckdsp) begin if ckdsp'event and ckdsp=

35、'1' then cnt8<=cnt8+1; end if; if cnt8="010" then cnt8<="000" end if; end process p2;end;7四選一LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xzq4_1 ISPORT( a,b:IN STD_LOGIC;i0,i1,i2,i3:IN STD_LOGIC;f:OUT STD_LOGIC);END xzq4_1;ARCHITECTURE behavior OF ymq83 IS SIGNAL

36、 sel:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN sel<=B&A;PROCESS(sel) BEGINCASE sel ISWHEN “00”=>F<=i0;WHEN “01”=>F<=i1;WHEN “10”=>F<=i2;WHEN “11”=>F<=i3;WHEN OTHERS=>NULL; END CASE;END behavior8譯碼器2-4譯碼器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;

37、use ieee.std_logic_unsigned.all;entity decode_behavior isport (A1,B1,G1:in std_logic;Y1:out std_logic_vector(3 downto 0);end entity decode_behavior;architecture behavioral of decode_behavior issignal data: std_logic_vector(1 downto 0);begindata <= A1&B1;process (data,G1)begin if (G1='0

38、9;) then case data iswhen "00"=>Y1<="1110"when "01"=>Y1<="1101"when "10"=>Y1<="1011"when "11"=>Y1<="0111"when others =>Y1<="1111"end case;else Y1<="1111"end if;end pro

39、cess;end behavioral;3-8譯碼器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ymq83 ISPORT(A,B,C:IN STD_LOGIC;Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ymq83;ARCHITECTURE behavior OF ymq83 IS SIGNAL INDATA:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN INDATA<=C&B&A;PROCESS(INDATA) BEGINCASE INDATA ISWHEN “

40、000” => Y<=“11111110”;WHEN “001” => Y<=“11111101”;WHEN “010” => Y<=“11111011”;WHEN “011” => Y<=“11110111”;WHEN “100” => Y<=“11101111”;WHEN “101” => Y<=“11011111”;WHEN “110” => Y<=“10111111”;WHEN “111” => Y<=“01111111”;WHEN OTHERS => Y<=“XXXXXXXX”

41、;END CASE;END PROCESS;END behavior;9奇偶校正LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY kk ISPORT (a:IN STD_LOGIC_VECTOR (4 DOWNTO 0);y:OUT STD_LOGIC);END kk;ARCHITECTURE arch OF kk ISBEGINPROCESS(a)VARIABLE temp:STD_LOGIC;BEGINtemp:='0' -偶校驗(yàn)初始值設(shè)為0，奇校驗(yàn)初始值設(shè)為1FOR i IN 0 TO 4 LOOPtemp:=temp XOR

42、 a(i);END LOOP;y<=temp;END PROCESS;END arch; 9位奇偶校正LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY jou9 ISPORT( a:IN STD_LOGIC_VECTOR(8 DOWNTO 0);y:OUT STD_LOGIC);END jou9;ARCHITECTURE behavior OF ymq83 ISBEGINPROCESS(a) VARIABLE temp:STD_LOGIC;BEGIN temp:=1; FOR i IN 0 TO 8 LOOP temp:=temp XOR a

43、(i); END LOOP;END PROCESS;y<=temp;END behavior;10 移位寄存器雙向移位寄存器 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ss IS PORT(clk:IN STD_LOGIC;dat_in:in std_logic;dat:in std_logic_vector(4 downto 0); outt:out std_logic_vector(4 downto 0) );END;ARCHITECTURE ONE OF ss IS signal x:std_logic_vector(4 dow

44、nto 0):="01110"signal xx:std_logic_vector(4 downto 0);-signal cc:std_logic;BEGIN process(clk)beginif clk'event and clk='1' thenif dat_in='1'thenx(4)<=x(3);x(3)<=x(2);x(2)<=x(1);x(1)<=x(0);x(0)<=x(4);end if;if dat_in='0'then x(0)<=x(1);x(1)<=

45、x(2);x(2)<=x(3);x(3)<=x(4);x(4)<=x(0);end if;end if;x<=xx;end process;process(dat)begin xx<=dat;end process;outt<=x; END ONE; library ieee; use ieee.std_logic_1164.all; entity yiwei_r is port(ld:in std_logic; cp:in std_logic; d:in std_logic_vector(3 downto 0); q:buffer std_logic_ve

46、ctor(3 downto 0); end yiwei_r; architecture one of yiwei_r is begin process(ld,cp,d) variable aa:std_logic_vector(3 downto 0); begin if ld ='1' then q<=d; elsif cp'event and cp='1'then aa(2 downto 0):=q(3 downto 1); aa(3):=q(0); q<=aa; end if; end process; end one;循環(huán)左移位寄存器l

47、ibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY Vhdl1 IS PORT ( clk : IN std_logic; rst : IN std_logic; dataout : OUT std_logic_vector(7 DOWNTO 0); END Vhdl1;ARCHITECTURE arch OF Vhdl1 IS SIGNAL cnt : std_logic_vector(22 DOWNTO 0); SIGNAL d

48、ataout_tmp : std_logic_vector(7 DOWNTO 0); BEGIN dataout <= dataout_tmp; PROCESS(clk,rst) BEGIN IF (NOT rst = '1') THEN cnt <= "00000000000000000000000" dataout_tmp <= "10011111" -為0的bit位代表要點(diǎn)亮的LED的位置 ELSIF(clk'event and clk='1')THEN cnt <= cnt + &q

49、uot;00000000000000000000001" IF (cnt = "11111111111111111111111") THEN dataout_tmp(6 DOWNTO 0) <= dataout_tmp(7 DOWNTO 1); dataout_tmp(7) <= dataout_tmp(0); END IF; END IF; END PROCESS;END arch;11 四位減法Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee

50、.std_logic_unsigned.all;entity try isport (input1: in std_logic_vector( 3 downto 0);-beijianshu input2: in std_logic_vector( 3 downto 0);-jianshu over_led: out bit; led_tong: out bit;output_led: out std_logic_vector(0 to 6);end try;architecture arch of try issignal result:std_logic_vector(3 downto 0

51、);beginprocess(input1, input2)beginled_tong <='1'if(input2>input1)then over_led <='1'-yichuresult <=input2-input1;elseover_led<='0'result <=input1-input2;end if;case CONV_INTEGER(result) iswhen 0 =>output_led <= "0111111" ;when 1 =>output_

52、led <= "0000110" ;when 2 =>output_led <= "1011011" ;when 3 =>output_led <= "1001111" ;when 4 =>output_led <= "1100110" ;when 5 =>output_led <= "1101101" ;when 6 => output_led <= "1111101" ;when 7 => outpu

53、t_led <= "0000111" ;when 8 =>output_led <= "1111111" ;when 9 =>output_led <= "1101111" ;when 10 =>output_led <= "1110111" ;when 11 =>output_led <= "1111100" ;when 12 =>output_led <= "0111001" ;when 13 =>o

54、utput_led <= "1011110" ;when 14 => output_led <= "1111001" ;when 15 => output_led <= "1110001" ;when others => output_led <= null;end case;end process;end arch;12 選擇器library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity

55、mux4 is port(d0,d1,d2,d3 :in std_logic; a0,a1 :in std_logic; q :out std_logic); end mux4; architecture behavioral of mux4 is signal sel :integer; begin with sel select q <= d0 after 10ns when 0, d1 after 10ns when 1, d2 after 10ns when 2, d3 after 10ns when 3, x after 10ns when other; sel <= 0

56、 when a0 =0 and a1 =0 else 1 when a0 =1 and a1 =0 else 2 when a0 =0 and a1 =1 else 3 when a0 =1 and a1 =1 else 4; end behavioral13 循環(huán)顯示13579LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SCAN_LED IS PORT( CLK :IN STD_LOGIC; SG :OUT STD_LOGIC_VECTOR(6 DOWNTO 0); BT :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END;ARCHITECTURE ONE OF SCAN_LED ISSIGNAL CNT8:STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL A:INTEGER RANGE 0 TO 9;BEGINP1:PROCESS(CNT8)BEGIN CASE CNT8 ISWHEN"000"