Chapter Five--Introduction to Logic Design

1、1Combinational logic(組合邏輯組合邏輯)the output at any instant of time depends only on what the inputs are at that time.Sequential system (時序系統(tǒng)時序系統(tǒng))the output will depend not only on the present input but also on the past historywhat has happened earlier.2IntroductionnClocked systems (referred to as synchr

2、onous(同步同步) A clock is just a signal that alternates(over time) between 0 and 1 at a regular rate.TThe period of the signal (T on the diagram) is the length of one cycle.The frequency is the inverse (1/T).In most synchronous systems, it is the transition of the clock signal that causes changes to oc

3、cur in sequential systems.clk1clk2Hz、KHz、MHz、GHz3Introduction (Con.)Conceptual view of a sequential systemMemoryCombinational Logic1qmqclock1xnx1zkzn inputsk outputsm binary storage devicesThe combinational logic is a function of the system inputs and the contents of memory; the combinational logic

4、outputs are the system outputs and signals to update the memory.4Introduction (Con.)new terminology to describe sequential systemsnState(狀態(tài)狀態(tài)): what is stored in memory(binary devices).nState table (狀態(tài)表狀態(tài)表): shows for each input combination and each state, what the output is and what the next state

5、is, that is, what is to be stored in memory after the next clock.nState diagram (or state graph) (狀態(tài)圖狀態(tài)圖): a graphical representation of the state table.State Machines Finite State Machines(FSM)5Introduction (Con.)a sample state table to illustrate these definitionsState tableABCD0/01/00/10/01/0X/01

6、/00/01/0State diagram column indicates the present state(現(xiàn)態(tài)現(xiàn)態(tài)); columns indicate the next state(次態(tài)次態(tài));qq*The next state(次態(tài)次態(tài))is a function of the present state(現(xiàn)態(tài)現(xiàn)態(tài)) and the input . Similarly, the output, , also depends on the present state and the input .xxzInput/Outputx/zeach statea possible state

7、 transitionthe input that causes that transition followed by the output that occursThis state diagram contains the identical information as the state table.65.1 Latches and Flip FlopsnLatch(閂鎖、鎖存器閂鎖、鎖存器): a binary storage device, composed of two or more gates, with feedback(反饋反饋).SRPQA NOR gate latc

8、hP = (S +Q)Q = (R+ P)The normal storage state is both inputs 0(inactive). If S and R are 0, then state P is the opposite of Q. The latch can store either a 0(Q=0 and P=1)or a 1(Q=1 and P=0), thus, the P output is usually labeled .QQ = P P = QS R Q Premarkresetsetnot allowednot the complement of each

9、 other (彼此彼此)0 0 0 11 01 1P Q0 11 00 0P=Q75.1 Latches and Flip Flops(Con.)QRSQnRS(Reset-Set)flip-flop: The Set (S) input causes a 1 to be stored in the flip flop at the next active clock edge; the Reset (R) input causes a 0 to be stored.nNote:The S and R inputs are never made 1 at the same time.SRq*

10、00110101q0101RS011000010010State diagramRqq*0011001101010101010011S00001111Behavioral tablenot allowed保持保持復位復位置位置位不允許不允許保持保持復位復位保持保持置位置位置位置位8Rqq*0011001101010101010011S00001111RS-FF Behavioral tablen We map q*. Notice that two of the squares are dont cares, since we will never make both S and R equa

11、l to 1 at the same time.n Then we can write the equation:*qSRqNote: RS=0A timing example is shown in Figure 5.16, on Page 33400 x110 x1SRq00011110015.1 Latches and Flip Flops(Con.)95.1 Latches and Flip Flops(Con.)SGRGPQSRGateA gated latchWhen the Gate signal is inactive(=0, 無效無效), SG and RG are both

12、 0, and the latch remains unchanged. Only when Gate goes to 1, can a 0 or 1 be stored in the latch.105.1 Latches and Flip Flops(Con.)nFlip Flop(觸發(fā)器觸發(fā)器): a clocked binary storage device;The state of the system changes on the transition of the clock. That change takes place when the clock goes from 1

13、to 0; that is referred to as trailing-edge triggered(下降沿觸發(fā)下降沿觸發(fā)). That change takes place when the clock goes from 0 to 1; that is referred to as leading-edge triggered (上升沿觸發(fā)上升沿觸發(fā)).ClockQDelayInput must be stableTrailing-edge triggered flip flop timing diagramslanted to indicate that they do not ch

14、ange instantaneouslyNote that the input must be available from just before the clock begin to go down, but is not required after the output starts to change.115.1 Latches and Flip Flops(Con.)nFlip-flops have one or two outputs. One output is the state of the flip flop (the other output is the comple

15、ment of the state).We will introduce the D、JK、SR and T flip flops. And we will use two forms of a truth table and a state diagram to describe the behavior of each type of flip flop.DqqDqqTrailing-edge triggeredLeading-edge triggeredD flip-flop diagramsDqq*001101010011Dq*010101D0101Truth tableState d

16、iagramThe next state(次態(tài)次態(tài)) of a flip flop can be described algebraically as a function of its inputs and present state. In the case of the D flip flop, the equation isq* = D125.1 Latches and Flip Flops(Con.)The behavior of a trailing-edge triggered D flip flop is illustrated in the timing diagram of

17、 figure 5.9.ClockDqqDNote that if the D input were to go back and forth between clock transitions, the output would not be affected, since the value of D is only relevant near the time of a trailing edge.qfigure 5.9A leading-edge triggered D flip flop is shown in figure 5.10.DClockfigure 5.10Dqq第5章

18、觸發(fā)器 13時序電路描述方式之一：時序圖時序電路描述方式之一：時序圖 時序圖的畫法一般按以下步驟進行：時序圖的畫法一般按以下步驟進行： 以時鐘以時鐘CP的作用沿為基準，劃分時間間隔，的作用沿為基準，劃分時間間隔，CP作用作用沿來到前為沿來到前為現(xiàn)態(tài)現(xiàn)態(tài)，作用沿來到后為，作用沿來到后為次態(tài)次態(tài)。 每個時鐘脈沖作用沿來到后，根據(jù)觸發(fā)器的狀態(tài)方程每個時鐘脈沖作用沿來到后，根據(jù)觸發(fā)器的狀態(tài)方程或狀態(tài)表確定其次態(tài)。或狀態(tài)表確定其次態(tài)。 異步直接置異步直接置0、置、置1端端(RD、SD)的操作不受時鐘的操作不受時鐘CP的控的控制，畫波形時要特別注意。制，畫波形時要特別注意。 145.1 Latches a

19、nd Flip Flops(Con.)Two flip flopsDqqDrrClockxWe connect the output of one flip flop to the input of another, and clock them simultaneously, as shown in Figure 5.11.Timing for two flip flopsNote: The output of flip flop r is a replica of that of q, delayed by one clock period. The name of the D flip

20、flop comes from Delay.Thats all.Clockqr155.1 Latches and Flip Flops(Con.)nThe behavior of flip flops with static (asynchronous, 異步異步) clear(清零清零) and preset (預置預置) inputs.Flip flop with clear and preset inputsTrailing-edge triggeredDqqPREClockCLRActive lowDqq *0101111PRECLR1001111XXX0011XXX010110001

21、1staticimmediatenot allowedclocked(as before)D flip flop with clear and preset inputs behavioral tablePRETiming for flip flop with clear and presetClockCLRDq16nT(Toggle) flip-flop: only one input, T, such that if T=1, the flip flop changes state (that is, is toggled), and if T=0, the state remains t

22、he same.5.1 Latches and Flip Flops(Con.)Tqq*001101010110Tq*01qqTqqClockThe behavioral equation is:*qTqA timing example is shown in Figure 5.18, on Page 33501T1100State diagram0110Tq0101保持保持翻轉翻轉17nJK flip-flop: it is a combination of the RS and T.5.1 Latches and Flip Flops(Con.)Kqq*001100110101010101

23、001110J00001111JK-FF Behavioral tableJKq*00110101q01qState diagram01JK0111000100101011From the first truth table, we can map it and derive the equation for q*:*qJqKqA timing example is shown in Figure 5.20, on Page 336JqqK保持保持翻轉翻轉復位復位置位置位10011010JKq0001111001q* 【例【例 1】 邊沿邊沿JK觸發(fā)器和觸發(fā)器和D觸發(fā)器分別如圖觸發(fā)器分別如圖

24、(a)、 (b)所示，所示，其輸入波形見圖其輸入波形見圖(c)，試分別畫出，試分別畫出Q、Q2端的波形。端的波形。（設電路初態(tài)均為（設電路初態(tài)均為0 ）C11D(b)RDSDCPA1Q2B12345CPA BQ1Q2(c)Q11JC11K(a)RDSDCPAB11第5章 觸發(fā)器 19C11D(b)RDSDCPA1Q2B12345CPA BQ1Q2(c)Q11JC11K(a)RDSDCPAB11111111QBQAQKQJQnADQn12（當（當B=0時，時， ）012nQ設電路初態(tài)均為設電路初態(tài)均為0分析：分析：第5章 觸發(fā)器 20 【例【例 2】 TTL邊沿觸發(fā)器組成的電路分別如圖邊沿觸發(fā)器

25、組成的電路分別如圖(a)、(b)所示，所示，其輸入波形見圖其輸入波形見圖(c)，試分別畫出，試分別畫出Q1、Q2端的波形。（設電路初端的波形。（設電路初態(tài)均為態(tài)均為0） 12345Q1Q2(c)CPA BC12345CPA BQ1Q2(c)CC11D(a)CPAQ1&FF1Q21JC11K(b)RDABCFF2=1=1CP1第5章 觸發(fā)器 22Q：如何用沿觸發(fā)的：如何用沿觸發(fā)的DFF、TFF及及JKFF實現(xiàn)實現(xiàn)2分頻電路分頻電路？第5章 觸發(fā)器 23 【例【例 3】 圖圖 (a)是由兩個是由兩個JK觸發(fā)器構成的單脈沖發(fā)生器，其輸觸發(fā)器構成的單脈沖發(fā)生器，其輸入入ui為時鐘脈沖的連續(xù)序列，輸出由

26、人工按鈕開關為時鐘脈沖的連續(xù)序列，輸出由人工按鈕開關S1控制，每按控制，每按一次，輸出一個脈沖。輸出脈沖的寬度僅決定于輸入時鐘脈沖的一次，輸出一個脈沖。輸出脈沖的寬度僅決定于輸入時鐘脈沖的周期。試畫出輸出端周期。試畫出輸出端uo的波形圖。的波形圖。Q21JC11K(a)RDFF21uiQ11JC11KRDFF11uoS1Q112345678CP(ui)J2(S1)245.1 Latches and Flip Flops(Con.)nSome of the commercially available flip flop packagesnD and JK flip flops are the

27、most common.7473: a dual JK flip flop package7474: a dual D flip flop package74174: a hex(six) D flip flop package74175: a quad(four) D flip flop package25Do some review. Some Edge-Triggered Flip-Flops5.2 Analysis of Sequential SystemsFFs Symbols:Characteristic Equations:RSFFDFFJKFFTFF Positive-edge

28、-triggered FFNegative-edge-triggered FFDFF: D*Q JKFF: QKQJ*QTFF: QT*QRSFF: QRS*Q0RS265.2 Analysis of Sequential SystemsObjectivesn This section introduces synchronous sequential systems with the following goals:u Definition of synchronous sequential systemsu Introduce two versions models of sequenti

29、al circuits: Mealy and Moore modelsu Demonstrate by example how to analyze synchronous sequential circuitsn Reading Assignmentu Mealy and Moore Models: P337u Analysis of sequential circuits: P343275.2 Analysis of Sequential Systemsn Definition: A sequential circuit is said to be a synchronous sequen

30、tial system if it satisfies the following conditions: All flip-flops have the same type of dynamic clock All clock inputs of all the flip-flops are driven by the same clock signal.5.2 Analysis of Sequential SystemsMemoryCombinational Logic1qmq1xnx1zkz1yjyZ = F(X,Q)Y = G(X,Q)Q* = H(Y,Q)Output Equatio

31、nInput EquationState Equationclock5.2 Analysis of Sequential Systems Two different type sequential modelsMemoryCombinational Logic1qmq1xnx1zkz1yjyclock Y=G(X, Q)Q*=H(Y, Q)A sequential system whose output depends on both state and input is called a Mealy-type output.Z=F(X, Q)MemoryCombinational Logic

32、1qmq1xnx1zkz1yjyclock Y=G(X, Q)Q =H(Y, Q)A sequential system whose output depends on the state alone is called a Moore-type output.Z=F(Q)5.2 Analysis of Sequential Systems Two different type sequential models315.2 Analysis of Sequential Systems (Con.)nThe Classification of Sequential SystemsnOn the

33、basis of the characteristic of State change: Synchronous Sequential systems Asynchronous Sequential SystemsnOn the basis of the characteristic of Output signals(P337): Mealy model: the output depends on the current input as well as the contents of memory. Z=F(X, Q) Moore model: the output depends on

34、ly on the present state of the system. Z=F(Q)325.2 Analysis of Sequential Systems (Con.)nFunctional description of Sequential SystemsnLogic Equation Z=F(X, Q) Q*=H(Y, Q) Y=G(X, Q)nState Transition Table (that is: State Table) Mealy model: Next states/Outputs Moore model: Next states and Outputs are

35、listed respectivelynState diagramnTiming graph33nState Transition Table (that is: State Table)5.2 Analysis of Sequential Systems (Con.)10/100/011/110/11011/100/011/100/01111/100/001/101/10110/000/001/100/00010110100n+1n+110QQ/Z1X0X10QQ01111010001100100111010010n+1n+110QQX10QQZ0100Mealy modelMoore mo

36、del345.2 Analysis of Sequential Systems (Con.)nState diagram00/001/010/011/111110000X10/QQZMealy modelMoore model10/100/011/110/11011/100/011/100/01111/100/001/101/10110/000/001/100/00010110100n+1n+110QQ/Z1X0X10QQ000001011111101010/101/111/011/001/011/000/010/111/000/010/100/110/101/101/100/1Q1Q0XX/

37、Z355.2 Analysis of Sequential Systems (Con.)nState diagram00011110Q1Q010/101/111/011/011/001/000/010/111/000/010/100/110/101/101/100/110/X XZ00/001/010/011/111110000X10/QQZMealy modelMoore model01111010001100100111010010n+1n+110QQX10QQZ0100Sequential systems can be represented in many forms. State (

38、transition) table 【狀態(tài)（轉移）表【狀態(tài)（轉移）表】 State diagram 【狀態(tài)圖【狀態(tài)圖】 State equations 【狀態(tài)方程【狀態(tài)方程】 Flip-flop input (excitation) funcations 【激勵方程】【激勵方程】 Circuit output functions 【輸出方程【輸出方程】 Timing diagram 【時序圖【時序圖】 Circuit diagram 【電路圖【電路圖】 These equivalent forms show the inputs, outputs, and flip-flop state ch

39、anges for sequential circuits.37nThe Steps of analysis5.2 Analysis of Sequential Systems (Con.)Logic CircuitInput equationOutput equationState equationState DiagramFunctionTiming5.2 Analysis of Sequential Systems Analysis ExamplesnExample 5.2.1 A simple synchronous sequential circuit with two negati

40、ve-edge-triggered JK flip-flops. Please analyze its behavior. At the trailing edge of the clock signal (CP), each JKFF samples its JK inputs and transfers these values to its Q output. Therefore, to determine the next value of Q (Q*), we must first determine the current value of J and K.5.2 Analysis

41、 of Sequential Systems Analysis ExamplesExample 5.2.11. Derive the excitation and output equationsJ0=K0=1Q0J1=K1=0QX XQ1Q001QQXZMealy-type output405.2 Analysis of Sequential Systems Analysis ExamplesExample 5.2.12. Derive the state equations from the excitation equationsJ0=K0=1J1=K1=0QX 01QQXZu Use

42、the characteristic equation for JK flip-flops:QKQJ*Qu The resulting state equations are:11111QKQJ*Q1010Q)QX(Q)QX(10QQX00000QKQJ*Q0Q3. State table and state diagram (列狀態(tài)表，畫狀態(tài)圖列狀態(tài)表，畫狀態(tài)圖) 時序電路狀態(tài)表時序電路狀態(tài)表 state diagram0000010110101111Q1Q0X/ /Z0/00/01/01/01/11/11/01/01/01/00/00/00/00/00/00/0XQ0Q1Z12345678

43、9CP4. Timing graph (Initial states are 0.)5. Logical FunctionFrom the state diagram, we can see:If X=0, its state 0001101100If X=1, its state 0011100100This is a synchronous up/down counter and its module is 4.Where, X is control signal of up/down.Z is carry/borrow signal.Thats all for today!465.2 A

44、nalysis of Sequential Systemsu Determine the excitation equations (激勵方程激勵方程) for the flip-flop control inputs.u Substitute the excitation equations into the flip-flop characteristic equations to obtain state equation (狀態(tài)方程狀態(tài)方程).u Use the state equations to construct a state table (狀態(tài)表狀態(tài)表).u Determin

45、e the output equations (輸出方程輸出方程).u Draw a state transition diagram (狀態(tài)圖狀態(tài)圖) corresponding to the state/output table.u Obtain the behavior (邏輯功能邏輯功能) of the circuit. In summary The detailed steps for analyzing a synchronous systems are as follows:47nExample 5.2.15.2 Analysis of Sequential Systems (C

46、on.)Explanation:1. Input and Output equations211001010221100D =Q , D =QD =Q +Q =Q QZ =Q , Z =Q , Z =Q2. State equation1221111010010nnnQDQQDQQDQQ3. State table and state diagram This sequential circuit is Moore model.1221111010010nnnQDQQDQQDQQ221100Z =Q , Z =Q , Z =Q2. State equation00000000100101001

47、0101101Q2Q1Q0110110011011111111100100有效狀態(tài)、無效狀態(tài)、自啟動有效狀態(tài)、無效狀態(tài)、自啟動123456CPQ0Q1Q2000000001010101Q2Q1Q01001100111114. Timing graph （時序波形）（時序波形）5. Logical Function （邏輯功能）（邏輯功能） Pulse distributor000001010101Q2Q1Q0100110011111 時序電路中的所有時序電路中的所有經過數(shù)個經過數(shù)個CP脈沖后都能進入脈沖后都能進入，稱電路為，稱電路為Q2Q1Q0 / Z000/0001/1010/0111/11

48、00/0101/1110/0011/1可自啟動電路可自啟動電路與與不可自啟動電路不可自啟動電路狀態(tài)圖狀態(tài)圖53 YQ1Q1Q2Q21J C11K1J C11K1J C11K&Q0Q0FF0 FF1 FF2CPnnQQY21nnnnnnQKQJQKQJQKQJ202001011212 輸出方程：輸出方程：Moore型時序電路型時序電路驅動方程：驅動方程：1寫寫方方程程式式【例】：分析下面同步時序電路的功能?！纠浚悍治鱿旅嫱綍r序電路的功能。542求狀態(tài)方程求狀態(tài)方程JK觸發(fā)器的特性方程：觸發(fā)器的特性方程：nnnQKQJQ1將各觸發(fā)器的驅動方程代入，即得電路的狀態(tài)方程：將各觸發(fā)器的驅動方程代入，

49、即得電路的狀態(tài)方程：nnnnnnnnnnnnnnnnnnnnnnnnQQQQQQKQJQQQQQQQKQJQQQQQQQKQJQ202020000100101011111112121222212nnnnnnQKQJQKQJQKQJ202001011212 YQ1Q1Q2Q21J C11K1J C11K1J C11K&Q0Q0FF0 FF1 FF2CP55現(xiàn) 態(tài)次 態(tài)輸 出nnnQQQ012 101112 nnnQQQY3列狀態(tài)表列狀態(tài)表nnnnnnnnQQYQQQQQQ122100111120 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 10 1 11

50、0 11 1 10 0 00 1 01 0 01 1 0000011000001000101112YQQQnnn0001010101112YQQQnnn0001001101112YQQQnnn0001011101112YQQQnnn1100100101112YQQQnnn1100110101112YQQQnnn0000101101112YQQQnnn0000111101112YQQQnnn YQ1Q1Q2Q21J C11K1J C11K1J C11K&Q0Q0FF0 FF1 FF2CP564畫狀態(tài)圖、時序圖畫狀態(tài)圖、時序圖狀態(tài)圖狀態(tài)圖有效循環(huán)有效循環(huán)無效循環(huán)無效循環(huán)電路不能自啟動。電路不能自啟

51、動。57CPQ0Q1Q2Y5電電路路功功能能時時序序圖圖有效循環(huán)的有效循環(huán)的6個狀態(tài)分別是個狀態(tài)分別是05這這6個十進制數(shù)字的格雷碼，并且在個十進制數(shù)字的格雷碼，并且在時鐘脈沖時鐘脈沖CP的作用下，這的作用下，這6個狀態(tài)是按遞增規(guī)律變化的，即：個狀態(tài)是按遞增規(guī)律變化的，即：000001011111110100000所以這是一個用格雷碼表示的六進制同步加法計數(shù)器。當對第所以這是一個用格雷碼表示的六進制同步加法計數(shù)器。當對第6個個脈脈沖計數(shù)時，計數(shù)器又重新從脈脈沖計數(shù)時，計數(shù)器又重新從000開始計數(shù)，并產生輸出開始計數(shù)，并產生輸出Y1。 YQ1Q1Q2Q21J C11K1J C11K1J C11K

52、&Q0Q0FF0 FF1 FF2CP YQ1Q1Q2Q21J C11K1J C11K1J C11K&Q0Q0FF0 FF1 FF2CPExamples:(a)(b)(c)595.3 The Design Process for Synchronous Sequential Systems(P337)Design aim(Word description)Original State diagram(state table)Reduced State diagram(state table)State reduceBinary state tableStateassignInput equati

53、onOutput equationSelect the type of Flip FlopsLogic CircuitTo check whether it can turn on by itself?124653605.4 Flip-Flop Design TechniquesnThe flip-flop design table (input equation): This table allows us to determine the inputs of the flip-flop, which can be most readily obtained from the state d

54、iagram.010101D010110JK010110Tqq*00110101Jqq*01XX00110101KXX10Tqq*011000110101state diagramFlip-flop design table0101DExcitation table615.4 Flip-Flop Design Techniques (Cont.)nExample 5.4.1 (P352 Table 5.15)Truth table to develop flip flop inputs001100110101010100000111x000011111q2q1q*2q*000010110011

55、00110101010100000111x000011111q2q1q*2q*0000101100XX01XXXX11XX001J1K0X0X1X1XX1X1X1X02J2K001101001T010111102T00000111000010111D2DMap the K-Map of the D and J、K and T , then we can obtain the Logic of flip-flop inputs12Z = q qInput (excitation) table:State table:625.4 Flip-Flop Design Techniques (Cont.

56、)nFor the JK flip flop, the resulting maps are shown as below. (P353 Map5.5)x000111100XX1XX12q q11Jx0001111001XXX1X12q q11Kx0001111001XXX1X12q q12Jx000111100XX11X1X12q q12KThe JK-FF input equations are121JxqKx221JxKxqnExample 5.4.1 (Method 1)12Z = q qImplementation using JK-FF:FF1FF2635.4 Flip-Flop

57、Design Techniques (Cont.)nThe method for design (it does not apply to the other types of flip flop) takes advantage of a property of JK flip flops.001100110101010100000111x000011111q2q1q*2q*00001011State Equation of JK flip flop isq* = Jq+ Kqxx00011110011112q q11q*00011110011112q q12q*)1211q = (xq q

58、 +(x)q)2122q = (x q +(xq )q*121JxqKx221JxKxqComparednExample 5.4.1 (Method 2)Implementation using JK-FF:FF1FF2645.4 Flip-Flop Design Techniques (Cont.)nExample 5.4.1001100110101010100000111x000011111q2q1q*2q*0000101112Z = q qHow to do with D flip-flop?State Equation of DFF isq* = D65 clocknIn this s

59、ection, we will look at the design of a type of synchronous sequential system referred to as a counter(計數(shù)器計數(shù)器). 【term: Module（模）（模）】nMost counters are devices with no data input, that go through a fixed sequence of states on successive clocks. The output is often just the state of the system, that i

60、s the contents of all of the flip flops.5.5 The Design of Synchronous Counters (P365)66nClassification of the Counters:nOn the basis of control mode of the clock: Synchronous Counters & Asynchronous CountersnOn the basis of the up or down of the sequence: up counters & down counters & up/down counte