EDA與VHDL斷改錯(cuò)題集

1、EDA 與 VHDL 斷改錯(cuò)題集一、判斷對(duì)錯(cuò)(并改正)1、CONSTANT T2: std_logic = 0；(錯(cuò)) 改正：把 qqqq=d;END CASE;答案：CASE語句缺 WHEN OTHERS語句。.已知 data_in1, data_in2為 STD_LOGIC_VECTOR(15 DOWNTO 0)類型的輸入 端口 , data_out為 STD_LOGIC_VECTOR(15 DOWNTO 0)類型的輸出端口 , add_sub為STD_LOGIC類型的輸入端口，請(qǐng)判斷下面給出的程序片段：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;

2、ENTITY add ISPORT (data_in1, data_in2 IN INTEGER ；data_out OUT INTEGER);END add;ARCHTECTURE add_arch OF add ISCONSTANT a:INTEGER=2 ;BEGINdata_out=( data_in1+ data_in2) * aEND addsub_arch;答案：常量聲明時(shí)賦初值的“二符號(hào)應(yīng)改用、”符號(hào)。.已知Q為STD_LOGIC類型的輸出端口，請(qǐng)判斷下面的程序片段:ARCHITECTURE test_arch OF test IS BEGINSIGNAL B : STD_LO

3、GIC ;QQQ Q Q = 0;END CASE;END test ;【參考答案】：CAS晤句應(yīng)該存在于進(jìn)程 PROCESS。.已知start為STD_LOGICt型的彳言號(hào)，sum INTEGE嚶型的信號(hào)，請(qǐng)判斷下面的程 序片斷：PROCESS （start）BEGINFOR i IN 1 TO 9 LOOP sum := sum + i ;END LOOP ;END PROCES S【參考答案】：sum是信號(hào)，其賦值符號(hào)應(yīng)該由“：=改為“ =。.已知Q為STD_LOGICt型的輸出端口，請(qǐng)判斷下面的程序片斷：ARCHITECTURE test OF test ISBEGINSIGNAL

4、B : STD_LOGIC ;Q = B ;END test ;【參考答案】：信號(hào)SIGNAL勺申明語句應(yīng)該放在 BEGINS句之前。.已知A口 Bt勻?yàn)镾TD_LOGI類型的信號(hào)，請(qǐng)判斷下面的語句：A = 0;B = x;【參考答案】：不定態(tài)符號(hào)應(yīng)該由小寫的x改為大寫的X。. 已知A為INTEGER1型的信號(hào)，B為STD_LOGICt型的信號(hào)，請(qǐng)判斷下面的程序片斷：ARCHITECTURE test OF test ISBEGINB q q q q = d ;END CASE;【參考答案】：CASE1句缺 WHEN OTHER第旬。四、判斷下面程序中是否有錯(cuò)誤，若有錯(cuò)誤請(qǐng)改正；1、SIGNA

5、L A,EN:STD_LOGIC;PROCESS(A,EN)VARIABLE B:STD_LOGIC;BEGINIF EN= 1 THENB=A;END ;END PROCESS;2、RCHITECTURE ONE OF SAMPLE ISVARIABLE A B, C: INTEGERBEGINC=A+B;END ;五、判斷下列程序是否有錯(cuò)誤，如有則指出錯(cuò)誤所在(10分)程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY

6、zyt12 ISPORT(R,EN,CP: IN bit;Q: BUFFER STD_LOGIC_VECTOR(0 DOWNTO 3);CO: OUT STD_LOGIC);END zyt;ARCHITECTURE c10 OF zyt12BEGINCO=1 WHEN(EN=1 AND Q=1011) ELSE ;0;PROCESS(R,CP)BEGINIF R=1 THENQ=0000;ELSIF (CPEVENT AND CP=1) THENIF EN=0 THENQ=Q;ELSIF Q=1011 THENQ=0000;ELSEQ:=Q+1;END IF;END PROCESS;END o

7、ne;六、VHDL程序改錯(cuò)：(10分)01 LIBRARY IEEE ;02USE IEEE.STD_LOGIC_1164.ALL ;03USE IEEE.STD_LOGIC_UNSIGNED.ALL;04 ENTITY LED7CNT IS05PORT ( CLR : IN STD_LOGIC;06CLK : IN STD_LOGIC;僅供學(xué)習(xí)與交流，如有侵權(quán)請(qǐng)聯(lián)系網(wǎng)站刪除謝謝7070809101112131415161718192021222324252627282930313233343536LED7s : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END LED

8、7CNT;ARCHITECTURE one OF LED7CNT ISSIGNAL TMP : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINCNT&ROCESS(CLR,CLK)BEGINIF CLR = 1 THENTMP = 0;ELSE IF CLKEVENT AND CLK = 1 THENTMP LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S 0);END CASE;END PROCESS;END one;在程序中存在兩處錯(cuò)誤，試指出，并說明理由: 提示：在MAX+PlusII

9、 10.2上編譯時(shí)報(bào)出的第一條錯(cuò)誤為:Error yine 15: File */led7cnt.vhd: Type error: type in waveform element must be“std_logic_vector弟 仃，乍日認(rèn):改正：弟 仃,乍日深:改正：七、判斷下列程序是否有錯(cuò)誤，如有則指出錯(cuò)誤所在，并為以下兩個(gè)程序配上相應(yīng)的實(shí)體和結(jié)構(gòu)體。（10分）（10 分）程序1:ARCHITECTURE one OF sample ISVARIABLE a,b,c:INTEGER;BEGINC=a+bEND;程序2:signal A,EN: std_logic;process（A,E

10、N）variable B: std_logic;beginif EN=1 then B=A;end if;end process;八、判斷下列程序是否有錯(cuò)誤，如有則指出錯(cuò)誤所在，并為以下兩個(gè)程序配上相應(yīng)的實(shí)體和結(jié)構(gòu)體。程序1:library ieee;use ieee.std_logic_1164.all;ENTITY sample isport(a,b:in integer;c:out integer);end sample;architecture one of sample isbeginc=a+b;end one;程序2:ENTITY sample1 isport(a,en:in st

11、d_logic;b:out std_logic);end sample1;architecture one of sample1 isbeginprocess(A,EN)beginif EN=1 then B=A;end if;end process;end one;九、程序改錯(cuò)題(仔細(xì)閱讀下列程序后回答問題，12分)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY gc ISPORT ( CLK : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(3 D

12、OWNTO 0);END gc;ARCHITECTURE bhv OF gc ISSIGNAL Q1 : RANGE 0 TO 9;BEGINPROCESS (clk,Q)BEGINIF RISING_EDGE(CLK) THENIF Q1 1001 THENQ1 = Q1 + 1 ;ELSEQ1 0);END IF;END IF;END PROCESS ;Q out1 out1= 0; 當(dāng) value 取十時(shí)END CASE;程序段2 :ARCHITECTURE bad OF ex ISSIGNAL a_vect: STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL b_

13、vect: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN0 &a=b;END;程序段3:IF sel = 1 THENC =“01” ；ELSIF John = 100 THENC= 10 ；ELSE c= 00” ;ELSE C= 11” ;END IF;第2題：判斷下列VHDL標(biāo)識(shí)符是否合法，如果有誤則指出原因。(1) _Decoder_1;(2) 2FFT;(3) Sig_ #N;(4)RyY_RsT_;(5) data_ _BUS;第3題：下面的賦值語句執(zhí)行之后矢量a ,b將分別得到什么值？ARCHITECTURE rtl OF ex ISSIGNAL a, b

14、: STD_LOGIC_VECTOR (4 downto 0);SIGNAL c: STD)LOGIC_VECTOR (0 to 2);BEGINa 0, 2=1, 4=1, others=b(4);a 的第一賦值為0 ,二四位賦值為1 ,其他位(0,3位)賦值為b的第四位0,其結(jié)果為10100僅供學(xué)習(xí)與交流，如有侵權(quán)請(qǐng)聯(lián)系網(wǎng)站刪除 謝謝12b i, 2=0, 3=1,others=c(1);b 的第 0 三位賦值為1 ,第二位賦值為0,其他位(1 , 4位)賦值為c的第一位0,結(jié)果為01001c out1 out1 NULL ;END CASE;第2題：ENTITY case_ex ISPO

15、RT(a: IN STD_LOGIC_VECTOR(4 DOWNTO 0);q:out STD_LOGIC_VECTOR(2 DOWNTO 0);END;ARCHITECTURE rtl OF case_ex ISBEGINP1:PROCESS(a)BEGINCASE a ISWHEN “00000 = q q q= 000 ” ;END CASE;END PROCESS;END;第3題：IF sel = 11 THENIF td = 1 THENC= “01” ；ELSIF td = 0 THENC= 10 ；ELSE c dd dd= 0;END CASE;第2題：IF sel = 01

16、THENC =“01 ” ；IF sel = 10 THENC= 10 ；ELSE c= 00” ;END IF;第3題：ARCHITECTURE bad OF ex ISSIGNAL a:BIT_VECTOR(2 DOWNTO 0);SIGNAL b:BIT_LOGIC_VECTOR(2 DOWNTO 1);BEGINa S_out S_out = 1;END CASE;第2題：ARCHITECTURE bhv OF ex ISSIGNAL a:STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL b:STD_LOGIC_VECTOR(0 TO 4);SIGNAL c: S

17、TD_LOGIC;BEGINa = 1101 ” ;b =c;b (0 TO 3)=a (3 DOWNTO 0);END;第3題：IF a = 1 THENC =111”；ELSIF b = 100 THENC= 110w ;ELSE c= 010” ;END IF;END IF;十四、VHDL程序改錯(cuò)：仔細(xì)閱讀下列程序，回答問題LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CNT10 ISPORT ( CLK : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END CNT10;ARCH

18、ITECTURE bhv OF CNT10 ISSIGNAL Q1 : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS (CLK) BEGINIF RISING_EDGE(CLK) beginIF Q1 9 THENQ1 = Q1 + 1 ;ELSEQ1 0);END IF;END IF;END PROCESS ;Q DEI1 Locate In Floorplan EditorHelp on Message4 架物區(qū)注映(J of 0M等燃裝十五、VHDL程序改錯(cuò)：本題程序?yàn)镋DA實(shí)驗(yàn)中的示例程序sch.vhd ,仔細(xì)閱讀程序，回答問題.對(duì)該程序進(jìn)行編譯時(shí)

19、出現(xiàn)錯(cuò)誤提示：“ VHDL Design File“sch” mustcontain an entity of the same name. ”這是什么原因？如何修改？.修改問題1的錯(cuò)誤后，如果編譯時(shí)出現(xiàn)“ Can t open VHDL “WORK” ”這樣的錯(cuò)誤提示。這又是什么原因，如何修改？library ieee;-1use ieee.std_logic_1164.all;-2entity schk is-3port (din, clk, clr : in std_logic; -串行輸入數(shù)據(jù)位/工作時(shí)鐘/復(fù)位信號(hào)4ab: out std_logic_vector(3 downto 0

20、)-檢測結(jié)5-5);-6end schk;-7architecture bhv of schk is-8signal q : integer range 0 to 8;-9signal d : std_logic_vector(7 downto 0);- 8 位待檢測預(yù)置數(shù)10 一begin-11d = 11100101;- 8位待檢測預(yù)置數(shù)-12process (clk, clr)-13begin-14if clr = 1 then q if din = d(7) then q = 1; else q if din = d(6) then q = 2; else q if din = d(5

21、) then q = 3; else q if din = d(4) then q = 4; else q if din = d(3) then q = 5; else q if din = d(2) then q = 6; else q if din = d(1) then q = 7; else q if din = d(0) then q = 8; else q q = 0;-26end case;-27end if;-28end process;-29process (q)-30begin-31if q = 8 then ab = 1010;-32elseab = 1011;-33en

22、d if;-34end process;-35end bhv;-36end end end end end end end end.在上述程序代碼中存在兩處錯(cuò)誤，編譯時(shí)出現(xiàn)如下提示，試修改錯(cuò)誤：Error: Line 12: File f:edaschk.vhd: VHDL syntax error: unexpected signal d in Concurrent Statement PartError: Line 29:File f:edaschk.vhd: VHDL syntax error: if statement must have END IF, but found PROCE

23、SS instead錯(cuò)誤1行號(hào)：程序改為:錯(cuò)誤2行號(hào)：程序改為:十六、VHDLS序改錯(cuò)仔細(xì)閱讀下列程序，回答問題LIBRARY IEEE;-1USE IEEE.STD_LOGIC_1164.ALL;-2ENTITY LED7SEG IS-3PORT ( A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);-4CLK : IN STD_LOGIC;-5LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);-6END LED7SEG;-7ARCHITECTURE one OF LED7SEG IS-8SIGNAL TMP : STD_LOGIC;-9B

24、EGIN-10SYNC : PROCESS(CLK, A)-11BEGIN-12IF CLKEVENT AND CLK = 1 THEN-13TMP LED7s LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S = 1101111;-29END CASE;-30END PROCESS;-31END one;-32.在程序中存在兩處錯(cuò)誤，試指出，并說明理由:.修改相應(yīng)行的程序：錯(cuò)誤1行號(hào)： 程序改為:錯(cuò)誤2行號(hào)： 程序改為:十八、VHDLS序改錯(cuò)仔細(xì)閱讀下列程序，回答問題LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;-2ENTITY LED7SEG IS-3PORT ( A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);-4CLK : IN STD_LOGIC;-5LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);-6END LED7SEG;-7ARCHITECTURE one OF LED7SEG IS-8 SIGNA