基于單片機(jī)的視覺系統(tǒng)外文翻譯

1、精選優(yōu)質(zhì)文檔-傾情為你奉上精選優(yōu)質(zhì)文檔-傾情為你奉上專心-專注-專業(yè)專心-專注-專業(yè)精選優(yōu)質(zhì)文檔-傾情為你奉上專心-專注-專業(yè)原 文Title：VISION SYSTEM BASED ON A SINGLE-CHIP MICROCOMPUTER Vision sensors which use dynamic RAM are cheaper and easier to interface than their alternatives - videcon or CCD. Andrew Russell describes a DRAM-based intelligent vision syste

2、m in which all interfacing and image processing functions are provided by an 8751 single-chip microcomputer The paper describes a compact and inexpensive binary vision system in which all interfacing and data processing functions are performed by an Intel 8751 single-chip microcomputer. The vision s

3、ensor is a 64k bit dynamic RAM chip which is capable of providing a picture resolution of up to 256 X 128 pixels. Picture processing algorithms are implemented within the vision system and object statistics are transferred to the host computer over a serial interface. The resulting system is impleme

4、nted using only four integrated circuits and is eminently suitable for component identification and inspection in a flexible manufacturing system environment. Microsystems computer vision DRAM optical sensors 8751 Computer vision systems are being used in increasing numbers for a variety of industri

5、al inspection, part identification and control tasks. Dynamic random-access memory (DRAM) circuits have been developed as binary optical sensors for these applications 12. DRAM-based vision systems are very low in cost and have direct compatibility with digital electronics. These advantages are not

6、shared by the alternative types of system available- videcon or CCD (charge coupled device) vision sensors-which are relatively expensive, were originally designed for compatibility with television displays and therefore do not provide an output which can be readily accessed by a computer. For many

7、inspection and identification tasks the higher resolution of videcon or CCD sensors is not required, and in such applications a DRAM-based system can be a more cost effective solution. This paper describes an intelligent vision sensor in which all interfacing and image processing functions are perfo

8、rmed by an Intel 8751 single-chip microcomputer. The 8751 contains a complete 8-bit microprocessor as well as EPROM, RAM, two timers, a full duplex I/O port and parallel I/O lines g. These resources within the 8751 are used to : directly control the DRAM optical sensor, an IS32 OpticRAM manufactured

9、 by Micron Technology Inc. perform address descramble and interpolation functions on the data in the DRAM either transmit the image to a host computer in compressed form or perform image processing algorithms and transmit the resulting statistics to a host computer. The 8751-based vision system impl

10、emented contains only four integrated circuits including the Optic RAM. The large quantity of interfacing electronics required by similar DRAM vision systems is eliminated. In addition, a truly intelligent sensor is created by incorporating vision processing functions within the 8751. Using a dram a

11、s a vision sensorA DRAM stores information in an array of memory cells, each consisting of a capacitor and a transistor 4. Figure 1 shows the memory cell layout. Data is read from or written to a memory cell by the following operations. An 8-bit row address is established on the DRAM address lines.

12、Ros. address strobe (RAS) is asserted, causing the row address decoder to select one of 256 row lines. The 256 transistors Q connected to the selected row line are switched on and transfer charge from the associated capacitor C to a column line. Charge from the memory cell is regeneratively amplifie

13、d and fed back onto the column lines to re-establish the original charge on the capacitors. An 8-bit column address is presented on the DRAM address lines. Column address strobe (CAS) is asserted, initiating the selection of one out of 256 column sense amplifiers and directing its output to the data

14、 out (DOUT) pin ,the DRAM. If a memory write operation is required data from the data in (DIN) pin would be routed to the, selected sense amplifier and hence to the appropriate memory cell. Charge on the memory cell capacitors tends to leak away. If data is to be retained the charge must be sensed b

15、efore it has decayed away completely, and restored its original level. The operation of restoring memory charge is called refresh and occurs when a read or writ cycle is performed on the same row as the cell.If light incident on the capacitors their rate of charge decay increased. Thus if all capaci

16、tors are charged and a suitable length of tinqe is allowed to elapse before reading the memory cells it will be found that some of the bits haw, been corrupted. Those bits which are corrupted will come from capacitors subjected to a higher level of illumination than those which are not corrupted. If

17、 the physical layout of the. memory cells can be determined it will be possible to locate those areas of the circuit where the light intensity, is above a certain threshold and thus to produce a image of the incident illumination. The 65 536 memory cells in the IS32 integrated circuits are grouped i

18、nto two regions with an area contain sense amplifiers between them. For most applications a large gap in the visual field will be unacceptable. Camera systemA DRAM optical sensor may be interfaced to a micro- computer by direct connection to the processor address bus or indirectly via an I/O port .

19、Connection through an I/O port is slower and requires a more complicated control program. These drawbacks are balanced by a considerable reduction in circuit complexity. The aim of this project was to produce a simple, inexpensive vision system and therefore the DRAM was connected through an I/O por

20、t .Memory refresh This process restores the charge level on memory ceil capacitors and is only stopped during image acquisition to make the memory cells sensitive to light. Timing for the refresh operation is controlled by one of the 8751, internal 16-bit counters. Counter 0 is programmed to generat

21、e an interrupt every 1.3 ms. The timer interrupt service routine performs a RAS-only refresh cycle on the 128 rows used to form the image. The service routine then restarts the timer and performs a return from interrupt. A large portion of the available processing time is used by the refresh operati

22、on and therefore efficient coding of this part of the program is essential. Acquiring an image write ls to the memory cells inhibit interrupts pedorm a timing loop to measure the required exposure time re-enable interrupts.Reading and writing Subroutines were written to transfer data between the 875

23、1 and Optic RAM. These subroutines control the output of 8751 ports 1 and 3 to perform read cycles and write cycles on the DRAM. Once again Boolean bit set and clear instructions are used except in those cases where more than one output line is required to change state simultaneously. In these cases

24、 it is quicker to write a byte o1 data to the I/O port .Descramble and interpolation of the imageThe IS32 is a development of the GT4264 64k bit DRAM. For this reason positioning of memory cells on the silicon hip surface was presumably governed by considerations of convenient and efficient layout.

25、The memory cells are not positioned physically on the chip in the same order as they are addressed electrically. To overcome this problem a look-up table was used to convert physical addresses into electrical addresses. The 8751 provides a move constant instruction which allows indexed addressing in

26、to rogram memory using either the program counter or a 16-bit data pointer register (DPTR) as base value. Acknowledgement The work reported here was supported by the Research Grant Committee of the University of 中文為宋體、西文為Times New Roman、小四，首行縮進(jìn)2字符，行距固定值22磅中文為宋體、西文為Times New Roman、小四，首行縮進(jìn)2字符，行距固定值22磅

27、。譯 文題目：基于單片機(jī)的視覺系統(tǒng) 使用動態(tài)隨機(jī)存取存儲器的視覺傳感器比使用他們的替代品videcon或CCD更便宜、更易于接口。安德魯羅素描述了一個(gè)動態(tài)隨機(jī)存取存儲器的智能可視系統(tǒng)，在這個(gè)系統(tǒng)所有接口和圖像的視覺系統(tǒng)處理功能由8751單片機(jī)提供。 本論文闡述了一個(gè)緊湊的和廉價(jià)的二進(jìn)制視覺系統(tǒng)，在這里的所有接口和數(shù)據(jù)處理函數(shù)是由英特爾8751單片機(jī)微機(jī)操作。視覺傳感器是一個(gè)每秒64比特的DRAM芯片，能夠提供一幅分辨率為256x128像素的畫面。在視覺系統(tǒng)中實(shí)現(xiàn)圖像處理算法和將統(tǒng)計(jì)數(shù)據(jù)傳輸?shù)街鳈C(jī)上都是通過串行接口完成的。所得到的系統(tǒng)只需要由四個(gè)集成電路實(shí)現(xiàn)，且非常適合于在靈活制造系統(tǒng)中進(jìn)行成分

28、標(biāo)識和檢測。微系統(tǒng)公司 計(jì)算機(jī)視覺 動態(tài)隨機(jī)存取存儲器 光學(xué)傳感 8751 計(jì)算機(jī)視覺系統(tǒng)正在被越來越多的使用，適用于各種工業(yè)檢測，零件識別和控制任務(wù)等領(lǐng)域。為了實(shí)現(xiàn)這些應(yīng)用程序，動態(tài)隨機(jī)存取存儲器電路已經(jīng)被開發(fā)成二進(jìn)制光學(xué)傳感器?；谝曈X系統(tǒng)的動態(tài)隨機(jī)存取存儲器成本非常低并且具有與數(shù)字電子技術(shù)直接的兼容性的優(yōu)勢。這些優(yōu)勢不與另一種可用“videcon”或CCD(電荷耦合裝置)視覺傳感器的系統(tǒng)類型所共享，這種類型相對昂貴，其最初設(shè)計(jì)是為了與電視顯示更好的兼容，因此不能提供一個(gè)可以方便地訪問計(jì)算機(jī)的輸出。而對于許多檢查和識別任務(wù)，這種方案對較高分辨率的videcon或CCD傳感器不是必需的，在這

29、樣的應(yīng)用中，基于動態(tài)隨機(jī)存儲器的系統(tǒng)是一個(gè)更有效的解決方案。本文描述了一種“智能”的視覺傳感器，所有接口和圖像處理功能都是由英特爾8751單片機(jī)來操作控制的。8751包含一個(gè)完整的8位微處理器還有EPROM、內(nèi)存、兩個(gè)定時(shí)器、一個(gè)全雙工的I / O端口和并行I / O線。這些資源被用于以下方面： 直接控制動態(tài)隨機(jī)存取存儲器光學(xué)傳感器，一個(gè)由美光科技公司制造的IS32 Optic RAM。 執(zhí)行地址“descramble”和插值函數(shù)在動態(tài)隨機(jī)存取存儲器中的數(shù)據(jù)。 圖像傳輸?shù)街鳈C(jī)電腦，壓縮形式或執(zhí)行圖像處理算法和結(jié)果統(tǒng)計(jì)數(shù)據(jù)傳輸?shù)街鳈C(jī)電腦。 基于單片機(jī)8751的視覺系統(tǒng)，它的實(shí)現(xiàn)過程只有四個(gè)包含O

30、ptic RAM的集成電路。大量需要類似動態(tài)隨機(jī)存取存儲器的視覺系統(tǒng)的電子產(chǎn)品被淘汰了。此外，一個(gè)真正的智能傳感器是由8751的視覺處理函數(shù)創(chuàng)造出來的。使用動態(tài)隨機(jī)存取存儲器作為視覺傳感器 一個(gè)動態(tài)隨機(jī)存取存儲器將信息存儲在一個(gè)存儲單元的數(shù)組中，每一個(gè)存儲單元由電容和晶體管組成。通過以下操作完成數(shù)據(jù)從一個(gè)存儲單元中讀取或?qū)懭胍粋€(gè)存儲單元： 一個(gè)8位行地址建立在動態(tài)隨機(jī)存取存儲器地址線上。 行地址閃光燈的顯示，導(dǎo)致行地址譯碼器去選擇一個(gè)256行線。256個(gè)晶體管Q轉(zhuǎn)移電容電荷從C列線連接到所選行線。 從存儲單元充電就是放大并反饋到列行而去重建原來的電容器。 一個(gè)8位的出現(xiàn)在動態(tài)隨機(jī)存取存儲器地址線上的列地址。確定選通列地址(CAS)，開始選擇一個(gè)256列放大器并指導(dǎo)其輸出到DRAM的輸出引腳(DOUT)端。如果一個(gè)內(nèi)存寫操作是必需的，從DIN引腳里取出的數(shù)據(jù)將被傳送到選定的讀出放大器，并且傳送到適當(dāng)?shù)拇鎯卧?。在充電存儲單元電容器往往發(fā)生泄漏。如果數(shù)據(jù)被保留，那么它的電荷必須在它已經(jīng)完全衰減并且恢復(fù)原來的水平之前被檢測?；謴?fù)內(nèi)存的控制操作也被稱為”刷新”，其讀或?qū)懸恢鲁霈F(xiàn)在同一行上的執(zhí)行周期。如果光出現(xiàn)在電容器上，其充電率衰減就會增加。因而如果在所有電容器充電和合適的允許消逝長度之