內(nèi)容文稿ni培訓(xùn)lesson optimizing for speed and

1、Lesson 8Optimizing FPGA Application for Speed and SizeBenchmarkingHow LabVIEW is Transformed for FPGAOptimizing for SpeedOptimizing for SizeA. Benchmarking1 Tick = 1 Clock cycleClock cycle depends on compile rate (Default 40 MHz) 32-bit counter increments on rising edge of the clockThe Tick Count VI

2、 returns the counter valueBenchmark the Loop Rate of a VIBenchmark the Loop Rate of a VITimestamp each iterationCalculate the differenceMeasurements done in parallel*Code can be removed later*Take advantage of parallel execution of FPGABenchmark the Execution Time of a VIGet initial timeExecute code

3、Get final timeCalculate the differenceMeasurements done in parallel*Code can be removed later*Take advantage of parallel execution of FPGABenchmarking the Size of a VISpeedTheoretical maximum compile rate shown in parenthesisSizeIOBs Input/output blocksMULT18X18s multipliersSLICEs Combination of loo

4、kup tables (LUTs) and flip flops (FFs)BUFGMUXs portal to the clock net, which clocks FFsB. How LabVIEW is Transformed for FPGAThree components necessary to maintain data flowThe corresponding logic functionSynchronizationThe enable chainEnforcing Dataflow in FPGAEnforcing Dataflow in FPGA (Continued

5、)C. Optimizing for SpeedParallel LoopsPipeliningSingle-Cycle Timed LoopsParallel ExecutionGraphical programming promotes parallel code architecturesLabVIEW Windows and Real-Time serialize executionLabVIEW FPGA implements truly parallel executionParallel Execution ExampleLoop rates limited by longest

6、 pathAI takes 170 ticks, DI takes 1 tickSeparate functions to allow DI to run independent of AI173 Ticks 4.3Sec4 Ticks .1 SecPipeliningWithin a loop you can separate your code into different loop iterations to reduce the length of each iterationHandle different parts of the process flow in parallel

7、within one loop iterationPass data to the next iteration using shift registersPipelining Example720 clock cycles (18 s)365 clock cycles (9.13 s)Single-Cycle Timed Loop (SCTL)Loop contents execute in a single clock periodMinimizes synchronization and enable chain overheadHowever, there are restrictio

8、nsSome VIs and functions cant be used in the loop at allAnalog input, analog outputNested loopsAny that require more than a single clock cycle to executeShared resourcesLoop timerWaitSCTL ExampleSaved 5 Ticks by placing this code in a SCTL1 Tick6 TicksImproving Loop PerformanceWhat to do if your dia

9、gram executes too slowly?12 clock cycles12345678910FFsFFsFFsFFsFFsFFsFFsFFsFFsFFsFFsFFsFFsFFs1112Reduce the Depth of the Data FlowShorten the longest path9 clock cycles1234567FFsFFsFFsFFsFFsFFsFFsFFsFFsFFsFFsFFs89Pipeline the DiagramWatch out for pipeline effects6 clock cycles1234FFsFFsFFsFFsFFsFFsF

10、FsFFsFFsFFsFFsFFs56Use the Single-Cycle Timed LoopEliminates synchronization and enables chain in the loop1 clock cycle1FFsFFsFFsFFsFFsD. Optimizing for SizeSubVIsFront Panel ObjectsDatatypesFunctions Using Lots of SpaceSingle-Cycle Timed LoopsNon-reentrant subVI is a shared resourceSlower execution

11、Less space (generally)Sharing SubVIsReentrant subVI recreates logic for each instanceFaster executionMore space (generally)Reentrant Non-Reentrant Number of MULT18X18s 18 out of 40 45%3 out of 40 7%Number of SLICEs 2116 out of 5120 41%2028 out of 5120 39%Limit Front Panel Objects (FPO)Have additiona

12、l logic to control data transfers to/from hostFront panel arrays are very expensiveReduce array sizeStore data in user memory insteadBetter Data Transfer MethodUse scalars to pass data between FPGA memory and the host. Using a front panel array to pass data to the host takes up a significant portion

13、 of FPGA space.Use Minimum Datatype NecessaryDatatype BitpackingCombine small datatypes into a 32-bit numericReduces front panel objectsFaster data transfers to/from hostSplit NumberFunctions Using Lots of Space Quotient Remainder Scale By Power of 2 (Use a constant for power) Array Functions (Use c

14、onstants where possible)FFsFFsFFsFFsFFsFFsFFsFFsFFsFFsFFsFFsFFsSingle-Cycle Timed Loop Removes Enable Chain OverheadFFsOptimize for Size ExampleThis VI is too large to compile.Optimize for Size Example (Continued)This VI takes 21% of the 1M gate FPGA. Optimize for Size Example (Continued)This VI takes 9% of the FPGA.Optimize for Size Example (Continued)This VI uses 8% of the FPGA.SummaryUse Timing VIs to benchmark the codeFPGA uses an enable chain to maintain dataflowImprove speed performance byReducing depth of dataflow pathUsing p