CPU高效編程技術(shù)課件

1、微處理器的核心技術(shù)流水線處理運(yùn)算器高速化RISC和CISC超標(biāo)量執(zhí)行亂序執(zhí)行分支預(yù)測緩存多核心1微處理器的核心技術(shù)流水線處理1了解處理器Nehalem E5620長流水線 = 15級X86指令解釋為微指令后亂序執(zhí)行等待執(zhí)行的微指令放在Reserveration Station多個(gè)ALU運(yùn)算單元并發(fā)、亂序執(zhí)行Reorder Buffer中實(shí)現(xiàn)串行化Instruction Retirement了解處理器Nehalem E5620長流水線 = 15級Pipeline示例：4級和8級的流水線Pipeline示例：4級和8級的流水線Intel的長流水線Intel的長流水線Front End讀入x86指令

2、，每個(gè)時(shí)鐘周期16字節(jié)x86指令解析為微指令（op）微指令（op）緩存Front End讀入x86指令，x86指令解析為微指令（亂序執(zhí)行-1寄存器重命名微指令進(jìn)入保留站分配臨時(shí)寄存器發(fā)射指令各種運(yùn)算Load/StoreEUEUEU亂序執(zhí)行-1寄存器重命名微指令進(jìn)入保留站分配臨時(shí)寄存器發(fā)射指亂序執(zhí)行-2存入臨時(shí)寄存器EU中計(jì)算結(jié)果Load/Store按指令順序?qū)懗鼋Y(jié)果指令生效，真正寫入內(nèi)存和物理寄存器觸發(fā)具有數(shù)據(jù)依賴的指令執(zhí)行亂序執(zhí)行-2存入臨時(shí)寄存器EU中計(jì)算結(jié)果Load/Store指令量化分析取指令，每個(gè)16字節(jié)/cycleX86指令解析為微指令簡單指令3條/cycle復(fù)雜指令1條/cycl

3、e保留站到EU的Port，總共6個(gè)P0，P1，P5到ALU單元P2，P3，P4到Load/Store單元Instruction Retirement，4條op/cycleDependency Chain長度指令量化分析取指令，每個(gè)16字節(jié)/cycle指令優(yōu)化長流水線 = 15級Branch prediction miss性能損耗大減少Branch prediction miss率減少/消除conditional branchBit運(yùn)算代替比較Comvg指令代替比較充分發(fā)揮Intel處理器亂序執(zhí)行的能力避免指令間存在long dependency chain避免指令間隱性的依賴關(guān)系，例如對efl

4、ags的依賴指令優(yōu)化長流水線 = 15級CPU內(nèi)部各部件訪問速度10CPU內(nèi)部各部件訪問速度10充分利用寄存器# define LZ4_COPYSTEP(s,d) A64(d) = A64(s); d+=8; s+=8;# define LZ4_COPYPACKET(s,d) LZ4_COPYSTEP(s,d)#define LZ4_WILDCOPY(s,d,e) do LZ4_COPYPACKET(s,d) while (d32) r=4; else r=0; val=32; if (!(val16) r+=2; val=8; else val=24; r += (!val);return

5、r;12位運(yùn)算int r;12并行執(zhí)行*op+=*ref+;*op+=*ref+;*op+=*ref+;*op+=*ref+;13并行執(zhí)行*op+=*ref+;13消除Conditional Branch如何消除這個(gè)if語句if (a 31;r = (mask & c) | (mask & d);Bit運(yùn)算版本2int mask = (a-b) 31;r = d + mask & (c-d);cmovg版本r = (a b) ？c : d;消除Conditional Branch如何消除這個(gè)if語句分支可能性提示#define likely(expr) expect(expr) != 0, 1

6、)#define unlikely(expr) expect(expr) != 0, 0)while likely(ipmatchlimit-(STEPSIZE-1)15分支可能性提示#define likely(expr) exThe Blocking Technique16The Blocking Technique16The Blocking Technique/ Increasing memory usage improves compression ratio/ Reduced memory usage can improve speed, due to cache effect/

7、Default value is 14, for 16KB, which nicely fits into Intel x86 L1 cache#define MEMORY_USAGE 14#define HASH_LOG (MEMORY_USAGE-2)#define HASHTABLESIZE (1 HASH_LOG)structrefTablesHTYPEhashTableHASHTABLESIZE;17The Blocking Technique/ Incrememchrmagic_bits = (unsigned long int) 0 x7efefefe 32) | 0 xfefe

8、feff;/* Set up a longword, each of whose bytes is C. */charmask = c | (c 8); charmask |= charmask 16; charmask |= charmask = sizeof (longword) longword = *longword_ptr+ charmask; if (longword + magic_bits) & magic_bits) != 0) 18memchrmagic_bits = (unsigned memchr續(xù) const unsigned char *cp = (const un

9、signed char *) (longword_ptr - 1); if (cp0 = c) return (_ptr_t) cp; . if (cp7 = c) return (_ptr_t) &cp7; n -= sizeof (longword);19memchr續(xù) 19False sharing20False sharing20對齊cachelinetypedef union GFAllctr_t gfa; char align_gfaERTS_ALC_CACHE_LINE_ALIGN_SIZE(sizeof(GFAllctr_t); ErtsAllocatorState_t;cha

10、r *states = erts_sys_alloc(0, + ERTS_CACHE_LINE_SIZE - 1); states = (UWord) states) & ERTS_CACHE_LINE_MASK) ? (char *) (UWord) states) & ERTS_CACHE_LINE_MASK) + ERTS_CACHE_LINE_SIZE) : (char *) states);21對齊cachelinetypedef union 21perf listRAW HARDWARE EVENT DESCRIPTOR Even when an event is not avai

11、lable in a symbolic form within perf right now, it can be encoded in a per processor specific way. For instance For x86 CPUs NNN represents the raw register encoding with the layout of IA32_PERFEVTSELx MSRs (see Intel(R) 64 and IA-32 Architectures Software Developers Manual Volume 3B: System Programming Guide Figure 30-1 Layout of IA32_PERFEVTSELx MSRs) or AMDs PerfEvtSeln (see AMD64 Architecture Programmers Manual Volume 2: System Programming, Page 344, Figure 13-7 Performanc