串口硬件設(shè)計(jì)文檔

空調(diào)溫控器設(shè)計(jì)方案版本信息序號版本號改正信息說明改正人時(shí)間V1.0設(shè)計(jì)方案草稿1目錄1概括···············································································································31.1硬件構(gòu)造連結(jié)······························································································31.2半雙工串行通訊數(shù)據(jù)格式···············································································3一次收發(fā)數(shù)據(jù)傳輸格式·························3連續(xù)收發(fā)的數(shù)據(jù)傳輸格式························31.3MAX3483CSA介紹·······················································································31.4軟件接見接口函數(shù)流程圖···············································································42.半雙工串行收發(fā)器接口·························································································42.1接口設(shè)計(jì)框圖·······························································································42.2接口描繪·····································································································52.3接口定義·····································································································53.控制模塊·········································································································63.1功能描繪·····································································································63.2內(nèi)部存放器說明····························································································63.3構(gòu)造框圖····································································································73.4接口定義·····································································································74.接收模塊·········································································································84.1功能描繪·····································································································84.2設(shè)計(jì)框圖····································································································8整體設(shè)計(jì)框圖·····························8接收控制邏輯部分··························94.3接口定義·····································································································94.4接收時(shí)序圖································································································105.發(fā)送模塊········································································································105.1功能描繪····································································································105.2設(shè)計(jì)框圖····································································································10整體設(shè)計(jì)框圖····························10發(fā)送控制邏輯部分··························115.3接口定義····································································································125.4發(fā)送時(shí)序圖·································································································122概括1.1硬件構(gòu)造連結(jié)該方案實(shí)現(xiàn)nios核中半雙工串行收發(fā)器接口和外接單片機(jī)之間的通訊，通訊線路之間采用MAX3483，傳輸協(xié)議依照UART半雙工串行收發(fā)通訊方式。接口地點(diǎn)如圖1中半雙工串行收發(fā)器接口。FPGArst_nnios_csROnios_rdRXDnios_wrREnios_adder[1:0]半雙工串MAX3nios_data_in[7:0]DE行收發(fā)器483CSTXDnios核nios_data_out[7:0]fpga_clk接口DIATIRIframe_error

單片機(jī)圖1硬件構(gòu)造連結(jié)1.2半雙工串行通訊數(shù)據(jù)格式一次收發(fā)數(shù)據(jù)傳輸格式01234567開端位數(shù)據(jù)位停止位安閑位連續(xù)收發(fā)的數(shù)據(jù)傳輸格式0707停止位安閑位開端位數(shù)據(jù)位停止位開端位數(shù)據(jù)位1.3MAX3483CSA介紹MAX3483CSA采納半雙工通訊方式，RO和DI端分別為接收器的輸出和驅(qū)動器的輸入端，與單片機(jī)連結(jié)時(shí)只要分別與單片機(jī)的RXD端和TXD相連，/RE和DE端分別為接受和發(fā)送的使能端，/RE為邏輯0時(shí)，器件處于接收狀態(tài)，當(dāng)DE為邏輯1時(shí)，器件處于發(fā)送狀態(tài)。31.4軟件接見接口函數(shù)流程圖發(fā)送數(shù)據(jù)過程接收數(shù)據(jù)過程開始開始否向控制存放器寫0，表示接收數(shù)據(jù)flag_reg=2軟件是讀狀態(tài)存放器的值寫到flag_reg辦理向數(shù)據(jù)緩沖存放器寫入1個(gè)字節(jié)數(shù)據(jù)是flag_reg=6讀狀態(tài)存放器的值寫到flag_reg否否軟件flag_reg=3辦理否是flag_reg=2接收數(shù)據(jù)是否否數(shù)據(jù)接收達(dá)成數(shù)據(jù)發(fā)送完成是是結(jié)束向控制存放器寫1結(jié)束圖2發(fā)送接收數(shù)據(jù)過程2.半雙工串行收發(fā)器接口2.1接口設(shè)計(jì)框圖nios_data_in[7:0]tr_spacetransmitDInios_cstrbuf_empty_indnios_rdtrdata_reg_selnios_wrrst_nDEnios_adder[1:0]ControlUart_data_out[7:0]RETI分分rebuf_full_indRIstopbit_err_indreceiveROFrame_errorre_spacenios_data_out[7:0]uart_clkfpga_clk分分圖3半雙工串行收發(fā)器構(gòu)造圖42.2接口描繪收發(fā)器接口總構(gòu)造如圖4所示，在默認(rèn)和復(fù)位狀況下收發(fā)器處于發(fā)送狀態(tài)。在發(fā)送狀態(tài)，查問到控制存放器的值為0，而且tr_space為高時(shí)，則將DE和/RE清0，此時(shí)收發(fā)器從發(fā)送狀態(tài)切換到接收狀態(tài)。在接收狀態(tài)，查問到控制存放器的值為1，而且r_space為高時(shí)，則將DE和/RE置1，收發(fā)器從接收狀態(tài)切換到發(fā)送狀態(tài)。發(fā)送狀態(tài)時(shí)，在發(fā)送安閑（tr_space為高）時(shí)期檢測到發(fā)送數(shù)據(jù)緩沖存放器有數(shù)據(jù)（tr_buf_empty_ind為低），第一將緩沖器的數(shù)據(jù)搬到移位存放器，而且給高位加1，低位加0，同時(shí)將tr_buf_empty_ind信號置高，接著啟動發(fā)送波特率計(jì)數(shù)器，同時(shí)將tr_space信號清0，而后每隔16個(gè)uart_clk時(shí)鐘周期發(fā)送1位數(shù)據(jù)，發(fā)送完最后1位數(shù)據(jù)后，再次將tr_space置高，表示發(fā)送安閑。接收狀態(tài)時(shí)，第一檢測降落沿，當(dāng)檢測到降落沿后，將re_space信號清0，同時(shí)啟動接收數(shù)據(jù)波特率計(jì)數(shù)器，當(dāng)計(jì)數(shù)器加到8時(shí)，采樣RO的值，為低，表示此時(shí)是一個(gè)起始信號，而后每隔16個(gè)uart_clk時(shí)鐘周期接收1位數(shù)據(jù)，當(dāng)接收到第9位數(shù)據(jù)，也就是停止位時(shí)，判斷停止位能否正確，若正確則將數(shù)據(jù)寫到接收緩沖存放器，同時(shí)將re_space信號置高，若停止位不正確則給出一個(gè)幀犯錯(cuò)指示信號，并放棄數(shù)據(jù)輸出。當(dāng)把數(shù)據(jù)從移位存放器寫到接收緩沖存放器時(shí)，將re_buf_full_ind置高，當(dāng)cpu把數(shù)據(jù)從接收緩沖存放器讀走，將re_buf_full_ind信號清0。fpga_clk為cpu工作時(shí)鐘，頻次為66.66MHZ，uart_clk為串行收發(fā)器接口的采樣時(shí)鐘，頻次為串口數(shù)據(jù)傳遞波特率的16倍，數(shù)據(jù)傳遞的波特率為9600bps。2.3接口定義序引腳名稱I/O功能描繪備注號1.rst_nI復(fù)位信號，低有效2.fpga_clkIcpu工作時(shí)鐘，頻次為66.66MHZ3.nios_csIcpu發(fā)送的片選信號，低有效4.nios_wrIcpu發(fā)送的寫使能，低有效5.nios_rdIcpu發(fā)送的讀使能，低有效6.nios_adder[1:0]Icpu接見接口內(nèi)部存放器的地點(diǎn)7.nios_data_in[7:0]Icpu向外接單片機(jī)中發(fā)送的數(shù)據(jù)8.nios_data_out[7:0]OCpu從外接單片機(jī)中接收的數(shù)據(jù)9.ROI串行數(shù)據(jù)接收引腳10./REO接收使能，低有效11.DIO串行數(shù)據(jù)發(fā)送引腳512.DEO發(fā)送使能，高有效13.TIO發(fā)送達(dá)成信號，高有效14RIO接收達(dá)成信號，高有效15fram_errorO幀犯錯(cuò)信號，高有效3.控制模塊3.1功能描繪該模塊主要實(shí)現(xiàn)以下功能：依據(jù)tr_space、re_space和控制存放器的值改變DE和/RE，實(shí)現(xiàn)收發(fā)器狀態(tài)的切換生成發(fā)送緩沖器寫使能，接收緩沖器讀使能，狀態(tài)存放器讀使能信號。3.2內(nèi)部存放器說明序號存放器名稱讀/寫地點(diǎn)存放器說明備注1.control_reg讀寫00讀寫控制存放器，最低位為讀寫判斷位，0，表示發(fā)送，1表示接收。其余位保存。2.uart_state只讀01狀態(tài)存放器，8位，低3位狀態(tài)標(biāo)志位，bit0發(fā)送數(shù)據(jù)緩沖存放器空滿標(biāo)記位，1為空，0為滿。bit1接收緩沖存放器空滿標(biāo)記，1為滿，0為空。bit2幀錯(cuò)誤指示信號，1表示有錯(cuò)誤，0表示正確。其余位保存。3.tran_buf_reg只寫10發(fā)送緩沖存放器，8位，只有緩沖存放器寫使能有效時(shí)，cpu才能向該存放器寫數(shù)據(jù)。4.rece_buf_reg只讀11接收緩沖存放器，8位，只有接收緩沖存放器讀使能有效時(shí)，cpu才能讀該存放器。63.3構(gòu)造框圖nios_wrnios_addernios_csnios_data_out

2'b00&RstControl_reg2'b10DFF2'b01&set2'b1101uart_state

tr_spaceDEre_spacetrdata_reg_selstate_reg_selredata_reg_sel10rece_buf_reg圖4控制模塊整體框圖3.4接口定義序號引腳名稱I/O功能描繪備注1.rst_nI復(fù)位信號，低有效2.fpga_clkICpu工作時(shí)鐘，頻次為66.66mhz，上漲沿采樣，占空比為50%。3.uart_clkI分頻后產(chǎn)生的采樣時(shí)鐘，頻次為波特率的16倍，上漲沿采樣，占空比為50%4.nios_csIcpu發(fā)送的片選信號，低有效5.nios_wrIcpu發(fā)送的寫使能，低有效6.nios_rdIcpu發(fā)送的讀使能，低有效7.nios_adder[1:0]Icpu接見接口內(nèi)部存放器的地點(diǎn)8.nios_data_in[7:0]Icpu向外接單片機(jī)中發(fā)送的數(shù)據(jù)9.nios_data_out[7:0]OCpu從外接單片機(jī)中接收的數(shù)據(jù)10./REO接收使能，低有效11.DEO發(fā)送使能，高有效12.TIO發(fā)送達(dá)成信號，高有效13.RIO接收達(dá)成信號，高有效14.fram_errorO幀犯錯(cuò)信號，高有效15.tr_spaceI發(fā)送安閑狀態(tài)指示信號，高有效16.trbuf_empty_indI發(fā)送緩沖存放器數(shù)據(jù)空指示信號，高有效17.trdata_reg_setO發(fā)送緩沖存放器寫使能信號，高有效18.rece_buf_reg[7:0]I接收緩沖存放器數(shù)據(jù)輸出719.rebuf_full_indI接收緩沖存放器數(shù)據(jù)滿指示信號，好有效20.stopbit_err_indI幀錯(cuò)誤izhishi信號，高有效21.re_spaceI接收狀態(tài)安閑指示信號，高有效22.state_reg_selO狀態(tài)存放器讀使能信號，高有效23.redata_reg_selO接收緩沖存放器讀使能信號，高有效4.接收模塊4.1功能描繪該部分主要達(dá)成以下功能：達(dá)成幀開端信號的檢測依據(jù)uart協(xié)議正確接收RO上數(shù)據(jù)，而且寫到接收緩沖存放器內(nèi)。當(dāng)接收數(shù)占有誤時(shí)，發(fā)送錯(cuò)誤指示信號，等候CPU讀取后，將錯(cuò)誤指示信號消除。生成re_space、rebuf_full_ind指示信號4.2設(shè)計(jì)框圖整體設(shè)計(jì)框圖re_spaceBufferrece_buf_reg[7:0]Shiftreg&Ctrlre_frame_errDLogicre_validDFFsetstopbit_err_inuart_rece_beginDFFdREDROuart_clkrstredata_reg_selstate_reg_selfpga_clk

&&DDFFDDFFsetrebuf_full_indDFFD圖5接收模塊整體框圖圖6中控制邏輯部分為狀態(tài)機(jī)，詳細(xì)狀態(tài)轉(zhuǎn)移以下所講。Uart_rece_begin為檢測到降落沿的指示信號，re_frame_error和re_valid為狀態(tài)機(jī)的輸出信號，用fpga_clk時(shí)鐘的上漲沿分別檢測re_frame_error和re_valid信號的降落沿，檢測到降落沿的時(shí)候讓8stopbit_err_ind和rebuf_full_ind分別置1，當(dāng)cpu把狀態(tài)存放器的值讀走將stopbit_err_ind信號清0.當(dāng)cpu把接收緩沖存放器的數(shù)據(jù)讀走，rebuf_full_ind信號清0。接收控制邏輯部分rst_nuart_rece_begin=0eecr&u&=4'h7=4'd8re_idleart_rntnt=reece_cc1_st__bbp_bibpsgin__=re&&Rcnt=receO=1=4'h7startre_bps_cnt==4'h7&&RO=0圖6接收部分狀態(tài)機(jī)re_idle接收安閑狀態(tài)；start接收幀開端信號狀態(tài)，rece接收數(shù)據(jù)狀態(tài)。復(fù)位時(shí)處于接收安閑狀態(tài)，當(dāng)檢測到降落沿后進(jìn)入start狀態(tài)，此時(shí)啟動接收波特率計(jì)數(shù)器，當(dāng)計(jì)數(shù)器計(jì)到8時(shí)，檢測RO的值，為0，表示幀開端信號，則進(jìn)入rece接收數(shù)據(jù)狀態(tài)。檢測RO的值，為1，進(jìn)入安閑狀態(tài)。接收完數(shù)據(jù)后跳到安閑狀態(tài)。在接收安閑狀態(tài)re_space信號為高，其余狀態(tài)信號都為低，即re_space=(re_state==re_idle)。4.3接口定義序引腳名稱I/O功能描繪備注號1.fpga_clkICpu工作時(shí)鐘，頻次為66.66mhz，上漲沿采樣，占空比為50%。2.uart_clkI分頻后產(chǎn)生的采樣時(shí)鐘，頻次為波特率的16倍，上漲沿采樣，占空比為50%3.ROI串行數(shù)據(jù)接收引腳4./REO接收使能，低有效5.rece_buf_reg[7:0]I接收緩沖存放器數(shù)據(jù)輸出6.rebuf_full_indI接收緩沖存放器數(shù)據(jù)滿指示信號，好有效7.stopbit_err_indI幀錯(cuò)誤izhishi信號，高有效8.re_spaceI接收狀態(tài)安閑指示信號，高有效9.state_reg_selO狀態(tài)存放器讀使能信號，高有效10.redata_reg_selO接收緩沖存放器讀使能信號，高有效94.4接收時(shí)序圖uart_clkREROre_statere_idlestartrecere_idlere_spacere_validset_full_indrebuf_full_indredata_reg_sel圖7正確數(shù)據(jù)uart_clkREROre_stateidlestartreceidlere_frame_errstopbit_err_indstate_reg_sel圖8錯(cuò)誤數(shù)據(jù)5.發(fā)送模塊5.1功能描繪該模塊實(shí)現(xiàn)以下功能把數(shù)據(jù)從發(fā)送緩沖存放器搬到移位存放器，依據(jù)uart協(xié)議，正確發(fā)送數(shù)據(jù)生成tr_space、trbuf_empty_ind指示信號5.2設(shè)計(jì)框圖整體設(shè)計(jì)框圖10CtrlLogictr_spaceset_empty_indDFFDrst_nuart_clk

&orDE&nios_wrsettrdata_reg_selDDFFtrbuf_empty_indfpga_clknios_data_intran_buf_reg1Shiftreg0DI圖7發(fā)送部分整體框圖圖7中控制邏輯部分為狀態(tài)機(jī)，詳細(xì)