時(shí)鐘數(shù)據(jù)恢復(fù)電路英文文獻(xiàn)

ClockandDataRecoveryCircuitAttheoutputofthelimitingamplifier,theamplifieddatasignalwithsharpeneddataedgesisavailableforfurtherprocessing,butuniqueinterpretationofthereceivedsignalrequirestiminginformation.Serialcommunicationlinksdonotprovideasynchronizationsignalonaseparatechannelandthereforethereceivermustrelyontheextractionofthetiminginformationfromthedatastream.Thisclockanddatarecoveryprocesscanbeperformedinasimilarmannerinopticalcommunication,electricalseriallinks,harddriveread-outchannels,aswellasinsomememoryinterfaces.Inthelatterfield,advocatesandopponentsoftheclockforwardingschemestilldebateabouttheadvantagesanddrawbacksofper-channelclockrecoverycircuits.Properdenominationofthewholesynchronizationprocesswouldbeclockrecoveryanddataretiming,betterdescribingthebehaviorallyindependentoperations.Indeedtherecoveredclockisusedtore-sampletheincoming(orsometimesdelayed)datatoprovidepropertiminginformation,i.e.synchronicity,forthefollowingblocks(Figure8.1).However,inmanyimplementations,theretimingoperationisembeddedintheclockrecoveryparttoachieveimprovedcircuitperformance.FIGURE8.1.ClockrecoveryanddataretimingprincipleThemajorchallengesofmultichannelclockrecoverycircuitdesignhavealreadybeenpresented,namely,theachievementoflow-powerandlow-areaoverheadwithminimumimpactonthecircuitperformance.First,anintroductiontotheimportantconceptsinthedesignofclockrecoverycircuitsispresented.Then,anoverviewofavarietyofclockrecoverytopologieswiththeirrespectiveadvantagesanddrawbacksallowsthereadertofullyunderstandthedesignchoicesoperatedlaterinthischapter.Afterdiscussionofappropriatetopologiesformultichannelclockrecovery,atop-downdesignapproachispresentedwhichvalidatesthejitterperformanceoftheselectedtopologyattheconceptlevel,atthebehaviorallevelandatthetransistorlevel.Finally,thetransistor-leveldesignoftheCDRisbrieflydiscussedandcharacterizationtechniquesareintroduced.1.ClockRecoveryPrinciplesHistorically,clockrecoverywasperformedusingresonantfilter-basedstructures,eitherusingdiscretepassiveelementsorresonantelementslikesurfaceacousticwave(SAW)devices.Intheeraofsystems-on-chip,requirementsforsmallsystemformfactorsandminimumbillofmaterial,theuseofsuchoff-chipcomponentsisstronglydiscouraged.Inthelong-haulmarket,wherefiber-opticcommunicationsmadetheirbreakthroughfirst,phase-lockedloop(PLL)topologieshavebecomethemainstreamsolution,thankstotheircapabilityofmonolithicintegrationwithaminimumnumberofexternalcomponents,typicallyonlyoneloopfiltercapacitor.BeyondthefactthatthePLLcurrentlystilldominatesthefieldandisthemostwell-knownclockrecoverytopology,wewouldliketousethisCDRstructureasabasistotheexplanationofsomeconceptstothenovicereader.AmoredetaileddiscussionofPLL-basedclockrecoverycircuitscanbefoundin[83].Forsimplification,letusfirstconsideraphase-lockedloopwithaperiodicinputsignal(Figure8.2).Thethreemainbuildingblocksarethephasedetector(PD),theloopfilter(LF)andthevoltage-controlledoscillator(VCO).ThephasedetectorcomparesthephaseerrorbetweentheinputsignalandthegeneratedsignalattheVCOoutput.Thephaseerrorisintegratedinthelow-passloopfilterandtheresultingcontrolsignaltunestheVCOfrequency,whichinturnreducesthephaseerror.FIGURE8.2.PLLwithperiodicinputsignalTheperiodicinputsignalf(tbanbewrittenasthesumofsineandcosinefunctions,namely,itsFourierseries:3(EQ8.1)灼(f)=y-V[選cos㈣十如(EQ8.1)-1J1Jr/ii1J177=1Inmosthighdatarateapplications,wecanneglectthehigherorderharmonicsandfocusonthefundamentalsignal,whichcanbewrittenas:(EQ8.2)vin(0=4*sin(4)(0)(EQ8.2)Theinstantaneousvaluef(t)ofasinewaveisdefinedbyitspeakamplitudeAanditsinstantaneousphase(t),whichcanagainbedecomposedintoaconstantangularfrequencyw0=2nfOandatime-varyinphaseangleO(t).Inphaseandfrequencymodulationschemesusedinwirelessdatatransmission,thistime-varyingphaseanglecontainstheinformationtobetransmitted.Infiberopticlinks,itdoesnotcontainanyusefulinformation,butrepresentsthephasenoiseduetochannelandcircuitimperfectionslikenoiseandlimitedbandwidth.Vjn(t)=A■sin(?or+e(O)=4?sin(2n%f+0(t))(eq疆戶Inbothtypesofapplications,thephase-lockedlooptechniqueallowstoextractthetime-dependentphaseinformationandtracktheinputsignal.Thein-phaseoutputsignalvout,lockedtotheinputsignal,guaranteesaverysmallphaseerror^e(t)betweentheinputphase9i(t)andtheoutputphase^o(t)。Thissituationiscalledphaselock.Asfrequencyisthederivativeoftheinstantaneousphase,constantphaseerrorprovideszerofrequencyerrorbetweeninputandoutputsignals.Theloopbandwidthbeinglimitedbythelow-passfilter,thesecharacteristicsarenotguaranteedforvariationsd&(t)/dtathigherfrequencies.Asalreadymentioned,thetwo-levelamplitudemodulationofthecarrierinseriallinkscanleadtodatarunswhichdonotcontainanytransitions.Thelow-passbehavioroftheloopfilterallowsthePLLtomemorizethesignalfrequencyduringtheselongrunswithoutlossofphaselock.Thecapturerangedefinesthefrequencyspanoftheinputsignalforwhichphaselockcanbeachieved.Forfrequenciesoutsidethisspan,thePLLwillremaininafree-runningsituation.Lockrangeontheotherhanddefinesthefrequencyspanforwhichlockcanbemaintainedonceitisacquired.Withoutgoingintomoredetails,theseparametersdependonthecharacteristicsofthePLLbuildingblocks,amongwhichtheVCO’stuningrange,definingthespanoffrequenciestheoscillatorcangeneratewhendrivingitscontrolvoltagefromoneendtotheotheroftherange.中文譯文時(shí)鐘及數(shù)據(jù)恢復(fù)電路在限幅放大器的輸出端，與銳化的數(shù)據(jù)邊緣的放大的數(shù)據(jù)信號(hào)是可用于進(jìn)一步處理，但所接收的信號(hào)的獨(dú)特的解釋需要定時(shí)信息。串行通信鏈路不提供在一個(gè)單獨(dú)的信道的同步信號(hào)，因此，接收器必須依賴于從數(shù)據(jù)流中的定時(shí)信息的提取。該時(shí)鐘和數(shù)據(jù)恢復(fù)過程，可以以類似的方式進(jìn)行，在光通信，電串行鏈路，硬盤驅(qū)動(dòng)器讀出的信道，以及在一些存儲(chǔ)器接口。在后場(chǎng)，時(shí)鐘傳送方案的倡導(dǎo)者和反對(duì)者的辯論的優(yōu)點(diǎn)和缺點(diǎn)，每個(gè)通道的時(shí)鐘恢復(fù)電路。適當(dāng)?shù)拿骖~為整個(gè)同步過程中，將時(shí)鐘恢復(fù)和數(shù)據(jù)重定時(shí)，更好地描述行為獨(dú)立操作。事實(shí)上，所恢復(fù)的時(shí)鐘被用于重新采樣傳入的（或有時(shí)延遲）的數(shù)據(jù)，以提供適當(dāng)?shù)亩〞r(shí)信息，即同步性，為下面的塊（圖8.1）。然而，在許多實(shí)施方式中，再定時(shí)操作被嵌入的時(shí)鐘恢復(fù)部，以達(dá)到提高電路性能。圖8.1時(shí)鐘恢復(fù)和數(shù)據(jù)重定時(shí)原則多通道的時(shí)鐘恢復(fù)電路設(shè)計(jì)的主要挑戰(zhàn)已經(jīng)被提出，即實(shí)現(xiàn)對(duì)電路性能的影響最小的低功耗和小面積的開銷。首先，介紹的時(shí)鐘恢復(fù)電路設(shè)計(jì)中的重要概念。然后，概述的各種時(shí)鐘恢復(fù)拓?fù)涓髯缘膬?yōu)點(diǎn)和缺點(diǎn)，可以讓讀者充分了解操作將在本章后面的設(shè)計(jì)選擇。討論適當(dāng)拓?fù)浣Y(jié)構(gòu)的多路時(shí)鐘恢復(fù)后，自頂向下的設(shè)計(jì)方法，驗(yàn)證所選擇的拓?fù)浣Y(jié)構(gòu)的概念，在行為層面，在晶體管級(jí)的抖動(dòng)性能。最后，簡(jiǎn)要討論的晶體管級(jí)設(shè)計(jì)的CDR和表征技術(shù)。1.時(shí)鐘恢復(fù)原理從歷史上看，使用諧振基于過濾器的結(jié)構(gòu)，無論是使用分立的無源元件或類似的表面聲波（SAW）器件的諧振元件執(zhí)行時(shí)鐘恢復(fù)。的系統(tǒng)級(jí)芯片的時(shí)代，小型系統(tǒng)的外形尺寸和最低物料清單的要求，這樣的斷片式元件的使用是強(qiáng)烈勸阻。在長(zhǎng)途市場(chǎng)，其中光纖通訊，他們的突破，鎖相環(huán)（PLL）的拓?fù)浣Y(jié)構(gòu)已經(jīng)成為主流的解決方案，用最少的外部元件數(shù)量的單片集成的能力，通常只有一個(gè)循環(huán)濾波電容。

除了PLL目前仍然占主導(dǎo)地位的領(lǐng)域，是最知名的時(shí)鐘恢復(fù)拓?fù)洌覀兿Ｍo新手閱讀器使用CDR結(jié)構(gòu)為基礎(chǔ)的一些概念的解釋?；赑LL的時(shí)鐘恢復(fù)電路的更詳細(xì)的討論，在［83］中可以找到。為簡(jiǎn)化起見，讓我們先考慮用一個(gè)周期性的輸入信號(hào)鎖相回路（圖8.2）。的三個(gè)主要建筑塊的相位檢測(cè)器（PD），環(huán)路濾波器（LF）和壓控振蕩器（VCO）。的相位檢測(cè)器的輸入信號(hào)和在VCO的輸出端所產(chǎn)生的信號(hào)之間的相位誤差進(jìn)行比較。被集成在低通環(huán)路濾波器和所得的控制信號(hào)，調(diào)諧VCO號(hào)，調(diào)諧VCO頻率，這反過來又降低相位誤差的相位誤差。圖8.2PLL與周期性輸入信號(hào)周期性輸入信號(hào)f（t）可以寫成正弦和余弦函數(shù)，即，它的傅里葉級(jí)數(shù)的總和:(EQ8.1)七"=y-y電,cos㈤)+力,si】]("]n=(E