計(jì)算機(jī)組成與結(jié)構(gòu)：chapter15 The IA-64 Architecture

ComputerOrganization&ArchitectureChapter15TheIA-64Architecture15.1Motivation64-bitprocessordevelopedbyIntelandHPBasicconceptsunderlyingIA-64referstoasexplicitlyparallelinstructioncomputing(EPIC)Explicitinstruction-levelparallelismLongandverylonginstructionwordsBranchpredicationSpeculativeloadingSoftwarepipeliningItaniumisfirstIntelproductTable15.1givesuskeydifferencesbetweenIA-64andanormalsuperscalarSuperscalarvs.IA-64NewArchitectureNothardwarecompatiblewithx86NowhavetensofmillionsoftransistorsavailableonchipCouldbuildbiggercacheDiminishingreturnsAddmoreexecutionunitsIncreasesuperscalaring“Complexitywall”Moreunitsmakesprocessor“wider”MorelogicneededtoorchestrateImprovedbranchpredictionrequiredLongerpipelinesrequiredLargernumberofrenamingregistersrequiredAtmostsixinstructionspercycleGreaterpenaltyformispredictionExplicitParallelismInstructionparallelismscheduledatcompiletimeIncludedwithmachineinstructionProcessorusesthisinfotoperformparallelexecutionRequireslesscomplexcircuitryforparallelschedulingCompilerhasmuchmoretimetodeterminepossibleparalleloperationsCompilerseeswholeprogram15.2GeneralOrganizationAgenerousnumberofregisters256registers128forinteger,logical,andgeneral-purposeuse12882bitforFPsandgraphicsuse641-bitpredicateregistersUsedforpredicateexecutionTosupporthighdegreeofparallelismMultipleexecutionunits8ormoreparallelunitsSeefig.15.1GeneralOrganizationforIA-64IA-64ExecutionUnitsI-UnitIntegerarithmeticShiftandaddLogicalCompareIntegermultimediaopsM-UnitLoadandstoreBetweenregisterandmemorySomeintegerALUB-UnitBranchinstructionsF-UnitFloatingpointinstructions15.3Predication,speculationandsoftwarepipelingInstructionFormat128-bitbundle:3instructionsandatemplatefields,seefig.15.2TheprocessorcanfetchonebundleatatimeTemplatefieldcontainsinformationthatindicateswhichinstructionscanbeexecutedinparallelTheprocessorcanlookatmultiplebundlestodecideinstructionsinparallelTheinstructionsarereorderandtemplateissetbycompilerIA-64InstructionWordFormat41PredicatedExecutionPredicationisatechniquewherebythecompilerdetermineswhichinstructionsmayexecuteinparallelIntheprocess,thecompilereliminatesbranchesfromtheprogrambyusingconditionalexecutionFortheconditionalexecution,apredicationregisterisusedforeachwayWhentheconditioninstructioniscompleted,cancelonewaypipelineinstructionsSeefig.15.3aIA64-predicationSpeculativeload:theprocessorloadsdatafrommemorybeforetheprogramneedsit,toavoidmemorylatencySpeculativeloadisanotherinnovationinIA-64CompilerrearrangethecodesothatloadsaredoneasearlyaspossibleAloadinstructioninoriginalprogramisreplacedbytwoinstructions:AspeculativeloadAcheckinstructionSeefig.15.3bIA-64SpeculativeLoadingLoopunrolling—

softwarepipeliningY[i]=x[i]+cL1:ld4r4=[r5],4;;addr7=r4,r9;;st4[r6]=r7,4

br.cloopL1Note:pipelining,butcannotparallelizing5iterationsin7cyclesld4r32=[r5],4;;//cycle0ld4r33=[r5],4;;//1ld4r34=[r5],4//2addr36=r32,r9;;//2ld4r35=[r5],4//3addr37=r33,r9//3st4[r6]=r36,4;;//3

ld4r36=[r5],4//4addr38=r34,r9//4st4[r6]=r37,4;;//4addr39=r35,r9//5st4[r6]=r38,4;;//5addr40=r36,r9//6st4[r6]=r39,4;;//6st4[r6]=r40,4;;//7ItaniumProcessorDiagramAdvancedloadaddresstableMulti-CoreTechnologyDualcore:twooperationcoresintegratedinaCPUBasedonX86architectureIdeacomesfromHyperThreadAMD,IntelAMDDCore:twocoresintegratedinadie