VHDL設(shè)計應(yīng)用實例

VHDL設(shè)計應(yīng)用實例7.1移位相加8位硬件乘法器電路設(shè)計7.1.1設(shè)計原理圖7.18位乘法器原理圖7.1.2硬件乘法器的設(shè)計1．選通與門模塊源程序例【7-1】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYANDARITHIS --選通與門模塊

PORT( ABIN :IN STD_LOGIC; DIN :IN STD_LOGIC_VECTOR(7DOWNTO0); DOUT :OUT STD_LOGIC_VECTOR(7DOWNTO0));ENDANDARITH;ARCHITECTUREbehaveOFANDARITHISBEGINPROCESS(ABIN,DIN)BEGIN FORIIN0TO7LOOP --循環(huán)，完成8位與1位運算

DOUT(I)<=DIN(I)ANDABIN;ENDLOOP;ENDPROCESS;ENDbehave;2．8位加法器源程序例【7-2】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYADDER8BIS PORT( CIN :INSTD_LOGIC;A,B:INSTD_LOGIC_VECTOR(7DOWNTO0);S:OUTSTD_LOGIC_VECTOR(7DOWNTO0);COUT:OUTSTD_LOGIC);ENDADDER8B;ARCHITECTUREbehaveOFADDER8BIS SIGNALSINT,AA,BB:STD_LOGIC_VECTOR(8DOWNTO0);BEGIN AA <= '0'&A;BB<= '0'&B;SINT<=AA+BB+CIN;S<=SINT(7DOWNTO0); COUT<=SINT(8);ENDbehave;3．8位右移寄存器源程序例【7-3】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYSREG8BIS --8位右移寄存器

PORT(CLK:INSTD_LOGIC; LOAD:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(7DOWNTO0); QB:OUTSTD_LOGIC);ENDSREG8B;ARCHITECTUREbehaveOFSREG8BISSIGNALREG8: STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(CLK,LOAD)BEGIN IFCLK'EVENTANDCLK='1'THEN IFLOAD='1'THEN --裝載新數(shù)據(jù)

REG8<=DIN; ELSE --數(shù)據(jù)右移

REG8(6DOWNTO0)<=REG8(7DOWNTO1);ENDIF;ENDIF;ENDPROCESS;QB<=REG8(0); --輸出最低位ENDbehave;4．16位鎖存器源程序例【7-4】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYREG16BIS--16位鎖存器

PORT( CLK:INSTD_LOGIC; CLR :INSTD_LOGIC; D:INSTD_LOGIC_VECTOR(8DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(15DOWNTO0));ENDREG16B;ARCHITECTUREbehaveOFREG16BIS SIGNALR16S: STD_LOGIC_VECTOR(15DOWNTO0);BEGINPROCESS(CLK,CLR)BEGIN IFCLR='1'THEN --清零信號

R16S<="0000000000000000"; ELSIFCLK'EVENTANDCLK='1'THEN--時鐘到來時，鎖存輸入值，并右移低8位

R16S(6DOWNTO0) <=R16S(7DOWNTO1);--右移低8位

R16S(15DOWNTO7)<=D;--將輸入鎖到高8位

ENDIF;ENDPROCESS;Q<=R16S;ENDbehave;5.運算控制模塊源程序例【7-5】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYARICTLIS PORT( CLK :INSTD_LOGIC; START:INSTD_LOGIC; CLKOUT:OUTSTD_LOGIC; RSTALL:OUTSTD_LOGIC; ARIEND:OUTSTD_LOGIC);ENDARICTL;ARCHITECTUREbehaveOFARICTLIS

SIGNALCNT4B : STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK,START)BEGIN RSTALL<=START;IFSTART='1'THEN CNT4B<="0000";ELSIFCLK'EVENTANDCLK='1'THENIFCNT4B<8THENCNT4B<=CNT4B+1;ENDIF;ENDIF;ENDPROCESS;PROCESS(CLK,CNT4B,START)BEGIN IFSTART='0'THENIFCNT4B<8THENCLKOUT<=CLK;ARIEND<='0';ELSECLKOUT<='0';ARIEND<='1';ENDIF;ELSECLKOUT<=CLK;ARIEND<='0';ENDIF;ENDPROCESS;ENDbehave;6．8位乘法器的源程序例【7-6】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYMULTI8X8IS--8位乘法器頂層設(shè)計

PORT( CLK,START:INSTD_LOGIC; A,B:IN STD_LOGIC_VECTOR(7DOWNTO0);ARIEND:OUTSTD_LOGIC; DOUT:OUTSTD_LOGIC_VECTOR(15DOWNTO0));ENDMULTI8X8;ARCHITECTUREbehaveOFMULTI8X8ISCOMPONENTARICTLPORT(CLK,START:INSTD_LOGIC;CLKOUT,RSTALL,ARIEND:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTANDARITHPORT(ABIN:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(7DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;COMPONENTADDER8BPORT(CIN:INSTD_LOGIC;A,B:INSTD_LOGIC_VECTOR(7DOWNTO0);S:OUTSTD_LOGIC_VECTOR(7DOWNTO0); COUT:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTSREG8BPORT(CLK,LOAD:INSTD_LOGIC; DIN:IN STD_LOGIC_VECTOR(7DOWNTO0); QB:OUT STD_LOGIC);ENDCOMPONENT;COMPONENTREG16BPORT(CLK,CLR:INSTD_LOGIC; D:INSTD_LOGIC_VECTOR(8DOWNTO0); Q:OUT STD_LOGIC_VECTOR(15DOWNTO0));ENDCOMPONENT; SIGNAL GNDINT,INTCLK,RSTALL,QB:STD_LOGIC;SIGNAL ANDSD :STD_LOGIC_VECTOR(7DOWNTO0);SIGNAL DTBIN :STD_LOGIC_VECTOR(8DOWNTO0);

SIGNAL DTBOUT :TD_LOGIC_VECTOR(15DOWNTO0);BEGINDOUT<=DTBOUT; GNDINT<='0'; U1:ARICTLPORTMAP(CLK=>CLK,START=>START, CLKOUT=>INTCLK,RSTALL=>RSTALL,ARIEND =>ARIEND); U2:SREG8BPORTMAP(CLK=> INTCLK,LOAD =>RSTALL, DIN=> B,QB=> QB); U3:ANDARITHPORT MAP(ABIN=>QB,DIN=> A, DOUT =>ANDSD); U4:ADDER8BPORT MAP(CIN=>GNDINT,A=>DTBOUT(15DOWNTO8),B =>ANDSD,S=> DTBIN(7DOWNTO0), COUT =>DTBIN(8)); U5:REG16BPORTMAP(CLK=> INTCLK,CLR=> RSTALL, D=>DTBIN,Q=> DTBOUT);ENDbehave;7.1.3系統(tǒng)仿真圖7.28位乘法器的仿真波形7.2數(shù)字頻率計設(shè)計7.2.1設(shè)計原理圖7.38位十進制數(shù)字頻率計的電路邏輯圖7.2.2數(shù)字頻率計設(shè)計1．測頻控制信號發(fā)生器設(shè)計測頻控制信號發(fā)生器的工作時序如圖7.3所示。為了產(chǎn)生這個時序圖，需首先建立一個由D觸發(fā)器構(gòu)成的二分頻器，在每次時鐘CLK上沿到來時其值翻轉(zhuǎn)。其中控制信號時鐘CLK的頻率取1Hz，而信號TSTEN的脈寬恰好為1s，可以用作閘門信號。此時，根據(jù)測頻的時序要求，可得出信號LOAD和CLR_CNT的邏輯描述。由圖7.4可見，在計數(shù)完成后，即計數(shù)使能信號TSTEN在1s的高電平后，利用其反相值的上跳沿產(chǎn)生一個鎖存信號LOAD，0.5s后，CLR_CNT產(chǎn)生一個清零信號上跳沿。圖7.4頻率計測頻控制器TESTCTL測控時序圖例【7-7】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL; ENTITYTESTCTLIS--測頻控制信號發(fā)生器

PORT(CLK:INSTD_LOGIC;--1Hz測頻控制時鐘

TSTEN:OUTSTD_LOGIC;--計數(shù)器時鐘使能

CLR_CNT:OUTSTD_LOGIC;--計數(shù)器清零

LOAD:OUTSTD_LOGIC);--輸出鎖存信號ENDTESTCTL;ARCHITECTUREbehaveOFTESTCTLISSIGNALDiv2CLK:STD_LOGIC;BEGINPROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THEN--1Hz時鐘二分頻Div2CLK<=NOTDiv2CLK;ENDIF;ENDPROCESS;PROCESS(CLK,Div2CLK)BEGINIFCLK='0'ANDDiv2CLK='0'THEN--產(chǎn)生計數(shù)器清零信號

CLR_CNT<='1';ELSECLR_CNT<='0';ENDIF;ENDPROCESS;LOAD<=NOTDiv2CLK;TSTEN<=Div2CLK;ENDbehave;2．十進制計數(shù)器設(shè)計例【7-8】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT10ISPORT(CLK,RST,EN:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDCNT10;ARCHITECTUREbehaveOFCNT10ISBEGINPROCESS(CLK,RST,EN)VARIABLECQI:STD_LOGIC_VECTOR(3DOWNTO0);BEGINIFRST='1'THENCQI:=(OTHERS=>'0');--計數(shù)器復(fù)位

ELSIFCLK'EVENTANDCLK='1'THEN--檢測時鐘上升沿

IFEN='1'THEN--檢測是否允許計數(shù)

IFCQI<"1001"THENCQI:=CQI+1;--允許計數(shù)

ELSECQI:=(OTHERS=>'0');--大于9，計數(shù)值清零

ENDIF;ENDIF;ENDIF;IFCQI="1001"THENCOUT<='1';--計數(shù)大于9，輸出進位信號

ELSECOUT<='0';ENDIF;CQ<=CQI;--將計數(shù)值向端口輸出

ENDPROCESS;ENDbehave;3．32位鎖存器設(shè)計例【7-9】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYREG32BIS--32位鎖存器

PORT(LOAD:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(31DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(31DOWNTO0));ENDREG32B;ARCHITECTUREbehaveOFREG32BISBEGINPROCESS(LOAD,DIN)BEGINIFLOAD'EVENTANDLOAD='1'THENDOUT<=DIN;--鎖存輸入數(shù)據(jù)

ENDIF;ENDPROCESS;ENDbehave;4．?dāng)?shù)字頻率計的源程序例【7-10】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYFREQISPORT(FSIN:INSTD_LOGIC;CLK:INSTD_LOGIC;DOUT:OUTSTD_LOGIC_VECTOR(31DOWNTO0));ENDFREQ;ARCHITECTUREbehaveOFFREQISCOMPONENTCNT10PORT(CLK,RST,EN:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTTESTCTLPORT(CLK:INSTD_LOGIC; TSTEN:OUTSTD_LOGIC; CLR_CNT:OUTSTD_LOGIC; LOAD:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTREG32BPORT(LOAD:INSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(31DOWNTO0);DOUT:OUTSTD_LOGIEC_VECTOR(31DOWNTO0));ENDCOMPONENT;SIGNALTSTEN:STD_LOGIC;SIGNALCLR_CNT:STD_LOGIC;SIGNALLOAD:STD_LOGIC;SIGNALC1:STD_LOGIC;SIGNALC2:STD_LOGIC;SIGNALC3:STD_LOGIC;SIGNALC4:STD_LOGIC;SIGNALC5:STD_LOGIC;SIGNALC6:STD_LOGIC;SIGNALC7:STD_LOGIC;SIGNALC8:STD_LOGIC;SIGNALDIN:STD_LOGIC_VECTOR(31DOWNTO0);BEGINU0:TESTCTLPORTMAP(CLK=>CLK,TSTEN=>TSTEN,

CLR_CNT=>CLR_CNT,LOAD=>LOAD);U1:CNT10PORTMAP(CLK=>FSIN,RST=>CLR_CNT,EN=>TSTEN,CQ=>DIN(3DOWNTO0),COUT=>C1);U2:CNT10PORTMAP(CLK=>C1,RST=>CLR_CNT,EN=>TSTEN,CQ=>DIN(7DOWNTO4),COUT=>C2);U3:CNT10PORTMAP(CLK=>C2,RST=>CLR_CNT,EN=>TSTEN,CQ=>DIN(11DOWNTO8),COUT=>C3);U4:CNT10PORTMAP(CLK=>C3,RST=>CLR_CNT,EN=>TSTEN,CQ=>DIN(15DOWNTO12),COUT=>C4);U5:CNT10PORTMAP(CLK=>C4,RST=>CLR_CNT,EN=>TSTEN,CQ=>DIN(19DOWNTO16),COUT=>C5);U6:CNT10PORTMAP(CLK=>C5,RST=>CLR_CNT,EN=>TSTEN,CQ=>DIN(23DOWNTO20),COUT=>C6);U7:CNT10PORTMAP(CLK=>C6,RST=>CLR_CNT,EN=>TSTEN,CQ=>DIN(27DOWNTO24),COUT=>C7);U8:CNT10PORTMAP(CLK=>C7,RST=>CLR_CNT,EN=>TSTEN,CQ=>DIN(31DOWNTO28),COUT=>C8);U9:REG32BPORTMAP(LOAD=>LOAD,DIN=>DIN(31DOWNTO0),DOUT=>DOUT);ENDbehave;7.2.3系統(tǒng)仿真頻率計設(shè)計的仿真波形如圖7.5所示。在一個CLK時鐘周期內(nèi)，F(xiàn)ISN有5個時鐘周期，因此DOUT輸出為00000005。圖7.5頻率計設(shè)計的仿真波形7.3電梯控制系統(tǒng)的設(shè)計7.3.1設(shè)計要求要求用FPGA設(shè)計實現(xiàn)一個3層電梯的控制系統(tǒng)。系統(tǒng)的要求如下：（1）電梯運行規(guī)則：當(dāng)電梯處在上升模式時，只響應(yīng)比電梯所在位置高的上樓請求，由下向上逐個執(zhí)行，直到最后一個上樓請求執(zhí)行完畢。如果高層有下樓請求，直接升到有下樓請求的最高樓層，然后進入下降模式。電梯處在下降模式時，工作方式與上升模式相反。設(shè)電梯共有3層，每秒上升或下降一層。（2）電梯初始狀態(tài)為一層，處在開門狀態(tài)，開門指示燈亮。（3）每層電梯入口處均設(shè)有上下請求開關(guān)，電梯內(nèi)部設(shè)有乘客到達樓層的停站請求開關(guān)及其顯示。（4）設(shè)置電梯所處位置的指示及電梯上升或下降的指示。（5）電梯到達有停站請求的樓層后，電梯門打開，開門指示燈亮。開門4秒后，電梯門關(guān)閉，開門指示燈滅，電梯繼續(xù)運行，直至執(zhí)行完最后一個請求信號后停在當(dāng)前層。（6）電梯控制系統(tǒng)能記憶電梯內(nèi)外的請求信號，并按照電梯運行規(guī)則工作，每個請求信號執(zhí)行完畢后清除。7.3.2設(shè)計思路根據(jù)電梯控制系統(tǒng)的設(shè)計要求，除了具備系統(tǒng)時鐘信號CLK以外，還應(yīng)該定義輸入信號和輸出信號。（1）輸入信號定義如下：

系統(tǒng)復(fù)位信號：RESET，高電平有效；

電梯入口處一層、二層的上樓請求開關(guān)：UP1、UP2；

電梯入口處二層、三層的下樓請求開關(guān)：DOWN2、DOWN3；電梯內(nèi)部到達樓層的停站請求開關(guān)：STOP1、STOP2、STOP3。

所有輸入信號的規(guī)定為：輸入信號等于1，表示有請求，信號等于0，表示無請求。（2）輸出信號定義如下：電梯外部上升和下降請求指示燈：UPLIGHT和DOWNLIGHT，這些信號與UPl、UP2、DOWN2和DOWN3信號相對應(yīng)；

電梯內(nèi)部乘客到達樓層的停站請求燈：STOPLIGHT，該信號與STOP1、STOP2和STOP3信號相對應(yīng)；

電梯運行模式指示：UDSIG，1代表下降模式，0代表上升模式；

電梯所在樓層指示：POSITION，表示電梯在對應(yīng)樓層；電梯門狀態(tài)指示：DOORLIGHT，1表示開門，0表示關(guān)門。7.3.3設(shè)計實現(xiàn)圖7.6狀態(tài)機設(shè)計流程例【7-11】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYFLIFTISPORT(CLK,RESET,UP1,UP2,DOWN2,DOWN3,STOP1,STOP2,STOP3:INSTD_LOGIC;UPLIGHT,DOWNLIGHT,STOPLIGHT:BUFFERSTD_LOGIC_VECTOR(3DOWNTO1);UDSIG:BUFFERSTD_LOGIC;POSITION:BUFFERINTEGERRANGE1TO3;DOORLIGHT:OUTSTD_LOGIC);ENDFLIFT;ARCHITECTUREBEHAVOFFLIFTISTYPESTATE_TYPEIS(STOPONL,DOOROPEN,DOORCLOSE,WAITL,WAIT2,WAIT3,WAIT4,UP,DOWN,STOP);SIGNALSTATE:STATE_TYPE:=STOPONL;SIGNALCLEARUP,CLEARDN,BUTTCLK,FLICLK:STD_LOGIC;SIGNALQ:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK)--分頻進程，產(chǎn)生電梯控制時鐘FLIFTCLK和按鍵控制時鐘BUFFCLK；BEGINIFRESET='1'THENQ<="0000";ELSIFRISING_EDGE(CLK)THENQ<=Q+1;ENDIF;BUTTCLK<=Q(0);FLICLK<=Q(3);ENDPROCESS;CONT:PROCESS(RESET,FLICLK)--狀態(tài)機進程VARIABLEPOS:INTEGERRANGE3DOWNTO1;BEGINIFRESET='1'THENSTATE<=STOPONL;CLEARUP<='0';CLEARDN<='0';ELSIFRISING_EDGE(FLICLK)THENCASESTATEISWHENSTOPONL=>DOORLIGHT<='1';POSITION<=1;POS:=1;STATE<=WAITL;--電梯在1層WHENWAITL=>STATE<=WAIT2;WHENWAIT2=>CLEARUP<='0';CLEARDN<='0';STATE<=WAIT3;WHENWAIT3=>STATE<=WAIT4;WHENWAIT4=>STATE<=DOORCLOSE;WHENDOORCLOSE=>DOORLIGHT<='0';IFUDSIG='0'THEN--上升情況

IFPOSITION=3THEN--電梯在3層

IFSTOPLIGHT="000"ANDUPLIGHT="000"ANDDOWNLIGHT="000"THENUDSIG<='1';STATE<=DOORCLOSE;ELSEUDSIG<='1';STATE<=DOWN;ENDIF;ELSIFPOSITION=2THEN--電梯在2層IFSTOPLIGHT="000"ANDUPLIGHT="000"ANDDOWNLIGHT="000"THENUDSIG<='0';STATE<=DOORCLOSE;ELSIFSTOPLIGHT(3)='1'ORDOWNLIGHT(3)='1'THENUDSIG<='0';STATE<=UP;ELSEUDSIG<='1';STATE<=DOWN;ENDIF;ELSIFPOSITION=1THEN--電梯在1層

IFSTOPLIGHT="000"ANDUPLIGHT="000"ANDDOWNLIGHT="000"THENUDSIG<='0';STATE<=DOORCLOSE;ELSEUDSIG<='0';STATE<=UP;ENDIF;ENDIF;ELSIFUDSIG='1'THEN--下降情況

IFPOSITION=1THEN--電梯在1層

IFSTOPLIGHT="000"ANDUPLIGHT="000"ANDDOWNLIGHT="000"THENUDSIG<='0';STATE<=DOORCLOSE;ELSEUDSIG<='0';STATE<=UP;ENDIF;ELSIFPOSITION=2THEN--電梯在2層IFSTOPLIGHT="000"ANDUPLIGHT="000"ANDDOWNLIGHT="000"THENUDSIG<='1';STATE<=DOORCLOSE;ELSIFSTOPLIGHT(1)='1'ORUPLIGHT(1)='1'THENUDSIG<='1';STATE<=DOWN;ELSEUDSIG<='0';STATE<=UP;ENDIF;ELSIFPOSITION=3THEN--電梯在3層IFSTOPLIGHT="000"ANDUPLIGHT="000"ANDDOWNLIGHT="000"THENUDSIG<='1';STATE<=DOORCLOSE;ELSEUDSIG<='1';STATE<=DOWN;ENDIF;ENDIF;ENDIF;WHENUP=>POSITION<=POSITION+1;POS:=POS+1;--電梯上一層

IFPOS=2AND(STOPLIGHT(3)='1'ORDOWNLIGHT(3)='1')THENSTATE<=UP;ELSESTATE<=STOP;ENDIF;WHENDOWN=>POSITION<=POSITION-1;POS:=POS-1;--電梯下一層

IFPOS=2AND(STOPLIGHT(1)='1'ORUPLIGHT(1)='1')THENSTATE<=DOWN;ELSESTATE<=STOP;ENDIF;WHENSTOP=>STATE<=DOOROPEN;--電梯停止

WHENDOOROPEN=>DOORLIGHT<='1';CLEARUP<='1';CLEARDN<='1';STATE<=WAITL;--電梯開門

WHENOTHERS=>STATE<=STOPONL;ENDCASE;ENDIF;ENDPROCESSCONT;BUTT:PROCESS(RESET,BUTTCLK)--讀按鍵、控制指示燈進程BEGINIFRESET='1'THENSTOPLIGHT<="000";UPLIGHT=<"000";DOWNLIGHT<="000";ELSEIFRISING_EDGE(BUTTCLK)THENIFCLEARUP='1'THENSTOPLIGHT(POSITION)<='0';UPLIGHT(POSITION)<='0';ELSEIFUP1='1'THENUPLIGHT(1)<='1';ELSIFUP2='1'THENUPLIGHT(2)<='1';ENDIF;ENDIF;IFCLEARDN='1'THENSTOPLIGHT(POSITION)<='0';DOWNLIGHT(POSITION)<='0';ELSEIFDOWN2='1'THENDOWNLIGHT(2)<='1';ELSIFDOWN3='1'THENDOWNLIGHT(3)<='1';ENDIF;ENDIF;IFSTOP1='1'THENSTOPLIGHT(1)<='1';ELSIFSTOP2='1'THENSTOPLIGHT(2)<='1';ELSIFSTOP3='1'THENSTOPLIGHT(3)<='1';ENDIF;ENDIF;ENDIF;ENDPROCESSBUTT;ENDBEHAV;7.3.4系統(tǒng)仿真圖7.7電梯控制系統(tǒng)的仿真波形一圖7.8電梯控制系統(tǒng)的仿真波形二7.4多功能信號發(fā)生器的設(shè)計7.4.1設(shè)計思路用FPGA設(shè)計一個多功能信號發(fā)生器，根據(jù)輸入信號的選擇可以輸出遞增鋸齒波、遞減鋸齒波、三角波、階梯波和方波等5種信號。信號發(fā)生器的控制模塊可以用數(shù)據(jù)選擇器實現(xiàn)，用5選1數(shù)據(jù)選擇器實現(xiàn)對5種信號的選擇。7.4.2多功能信號發(fā)生器的設(shè)計實現(xiàn)1．遞增鋸齒波的設(shè)計例【7-12】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYsawtooth_adderIS--遞增鋸齒波sawtooth

PORT(clk,reset:INstd_logic;--復(fù)位信號reset，時鐘信號clkq:OUTstd_logic_vector(7DOWNTO0));--輸出信號qENDsawtooth_adder;ARCHITECTUREbehaveOFsawtooth_adderISBEGINPROCESS(clk,reset)VARIABLEtmp:std_logic_vector(7DOWNTO0);BEGINIFreset='0'THEN

tmp:="00000000";ELSIFrising_edge(clk)THENIFtmp="11111111"THEN

tmp:="00000000";ELSE

tmp:=tmp+1;--遞增信號的變化

ENDIF;ENDIF;q<=tmp;ENDPROCESS;ENDbehave;2．遞減鋸齒波的設(shè)計例【7-13】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;entitysawtooth_minusIS--遞減鋸齒波sawtooth_minus

PORT(clk,reset:instd_logic;--復(fù)位信號reset，時鐘信號clkq:outstd_logic_vector(7downto0));--輸出信號q，8位數(shù)字信號ENDsawtooth_minus;ARCHITECTUREbehaveOFsawtooth_minusISBEGINPROCESS(clk,reset)VARIABLEtmp:std_logic_vector(7DOWNTO0);BEGINIFreset='0'then

tmp:="11111111";ELSIFrising_edge(clk)THENIFtmp="00000000"THEN

tmp:="11111111";ELSE

tmp:=tmp-1;--遞減信號的變化

ENDIF;ENDIF;q<=tmp;ENDPROCESS;ENDbehave;3．三角波的設(shè)計例【7-14】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYtriangleIS--三角波triangle

PORT(clk,reset:instd_logic;--復(fù)位信號reset，時鐘信號clkq:outstd_logic_vector(7DOWNTO0));--輸出信號q，8位數(shù)字信號ENDtriangle;ARCHITECTUREbehaveOFtriangleISBEGINPROCESS(clk,reset)VARIABLEtmp:std_logic_vector(7DOWNTO0);VARIABLEa:std_logic;BEGINIFreset='0'THEN

tmp:="00000000";ELSIFrising_edge(clk)THENIFa='0'thenIFtmp="11111110"TEEN

tmp:="11111111";a:='1';ELSE

tmp:=tmp+1;ENDIF;ELSEIFtmp="00000001"THEN

tmp:="00000000";a:='0';ELSE

tmp:=tmp-1;ENDIF;ENDIF;ENDIF;q<=tmp;ENDPROCESS;ENDbehave;4．階梯波的設(shè)計例【7-15】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYladderIS--階梯波ladder

PORT(clk,reset:instd_logic;--復(fù)位信號reset，時鐘信號clkq:outstd_logic_vector(7DOWNTO0));--輸出信號q，8位數(shù)字信號ENDladder;ARCHITECTUREbehaveOFladderISBEGINPROCESS(clk,reset)VARIABLEtmp:std_logic_vector(7DOWNTO0);BEGINIFreset='0'THEN

tmp:="00000000";ELSIFrising_edge(clk)THENIFtmp="11111111"THEN

tmp:="00000000";ELSE

tmp:=tmp+16;--階梯信號的產(chǎn)生

ENDIF;ENDIF;q<=tmp;ENDPROCESS;ENDbehave;5.方波的設(shè)計例【7-16】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYsquareis--方波square

PORT(clk,reset:instd_logic;--復(fù)位信號reset，時鐘信號clkq:outstd_logic_vector(7DOWNTO0));--輸出信號q，8位數(shù)字信號ENDsquare;ARCHITECTUREbehaveOFsquareISSIGNALa:std_logic;BEGINPROCESS(clk,eset)VARIABLEtmp:std_logic_vector(7downto0);BEGINIFreset='0'thena<='0';ELSIFrising_edge(clk)THENIFtmp="11111111"THEN

tmp:="00000000";ELSEtmp:=tmp+1;ENDIF;IFtmp<="10000000"thena<='1';ELSEa<='0';ENDIF;ENDIF;ENDPROCESS;PROCESS(clk,a)BEGINIFrising_edge(clk)THENIFa='1'THENq<="11111111";ELSEq<="00000000";ENDIF;ENDIF;ENDPROCESS;ENDbehave;6．?dāng)?shù)據(jù)選擇器的設(shè)計例【7-17】LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYmux51IS--選擇信號sel

PORT(sel:instd_logic_vector(2downto0);--5路輸入信號

d1,d2,d3,d4,d5:instd_logic_vector(7downto0);--被選擇的信號輸出

q:outstd_logic_vector(7downto0));ENDmux51;ARCHITECTUREbehaveOFmux51ISBEGINPROCESS(sel)BEGINCASEselisWHEN"001"=>q<=d1;--選擇信號sel=001，選擇第1路信號輸出

WHEN"010"=>q<=d2;--選擇信號sel=010，選擇第2路信號輸出

WHEN"011"=>q<=d3;--選擇信號sel=011，選擇第3路信號輸出

WHEN"100"=>q<=d4;--選擇信號sel=100，選擇第4路信號輸出

WHEN"101"=>q<=d5;--選擇信號sel=101，選擇第5路信號輸出

WHENothers=>null;ENDCASE;ENDPROCESS;ENDbehave;7．頂層電路的設(shè)計圖7.9信號發(fā)生器頂層電路7.4.3系統(tǒng)仿真圖7.10遞增斜波仿真波形圖7.11遞減斜波仿真波形圖7.12三角波仿真波形圖7.13階梯波仿真波形圖7.14方波仿真波形7.5數(shù)字鬧鐘系統(tǒng)設(shè)計7.5.1鬧鐘系統(tǒng)的設(shè)計要求及設(shè)計思路要求設(shè)計一個24小時的數(shù)字鬧鐘，該數(shù)字鬧鐘的面板如圖7.15所示，它包括以下幾個組成部分：（1）顯示屏，由7個七段數(shù)碼管組成，其中6個用于顯示當(dāng)前時間（時：分：秒）或設(shè)置的鬧鐘時間，而另一個則用于顯示系統(tǒng)內(nèi)部產(chǎn)生的周期性循環(huán)變化的待選預(yù)置數(shù)字；（2）YES（確認(rèn)）鍵：用于輸入新的時間或新的鬧鐘時間時，對每位待選預(yù)置數(shù)字輸入的確認(rèn)；圖7.15數(shù)字鬧鐘面板圖（3）TIME（時間）鍵：用于確定新的時間設(shè)置；（4）ALARM（鬧鐘）鍵：用于確定新的鬧鐘時間設(shè)置，或顯示已設(shè)置的鬧鐘時間；（5）揚聲器，在當(dāng)前時鐘時間與鬧鐘時間相同時，發(fā)出蜂鳴聲。7.5.2鬧鐘系統(tǒng)的總體設(shè)計思路圖7.16計時器的外部端口7.5.3鬧鐘系統(tǒng)的控制器的設(shè)計圖7.17鬧鐘控制器的外部端口表7.1控制器狀態(tài)轉(zhuǎn)換及控制輸出表由于在整個系統(tǒng)中有多個模塊需要用到自行設(shè)計的數(shù)據(jù)類型，并且這些數(shù)據(jù)類型大部分相同，因此我們?yōu)榱耸褂蒙系姆奖?，可設(shè)計一個程序包P_ALARM，該程序既可加在調(diào)用該程序包的程序前面，也可加在整個系統(tǒng)的頂層設(shè)計程序的前面。但是對于一個比較復(fù)雜系統(tǒng)的設(shè)計，一般是分模塊進行設(shè)計和調(diào)試，所以加在各個調(diào)用該程序包的程序前面會比較方便寫。程序包P_ALARM的具體設(shè)計如下：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;PACKAGEP_ALARMISSUBTYPET_DIGITALISINTEGERRANGE0TO9;SUBTYPET_SHORTISINTEGERRANGE0TO65535;TYPET_CLOCK_TIMEISARRAY(5DOWNTO0)OFT_DIGITAL;TYPET_DISPLAYISARRAY(5DOWNTO0)OFT_DIGITAL;ENDPACKAGEP_ALARM;例【7-18】--控制器源程序CONTROL.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEWORK.P_ALARM.ALL;ENTITYCONTROLISPORT(KEY:INSTD_LOGIC;ALARM_BUTTON:INSTD_LOGIC;TIME_BUTTON:INSTD_LOGIC;CLK:INSTD_LOGIC;RESET:INSTD_LOGIC;LOAD_NEW_A:OUTSTD_LOGIC;LOAD_NEW_C:OUTSTD_LOGIC;SHOW_NEW_TIME:OUTSTD_LOGIC;SHOW_A:OUTSTD_LOGIC);ENDENTITYCONTROL;ARCHITECTUREBEHAVEOFCONTROLISTYPET_STATEIS(S0,S1,S2,S3,S4);CONSTANTKEY_TIMEOUT:T_SHORT:=500;CONSTANTSHOW_ALARM_TIMEOUT:T_SHORT:=500;SIGNALCURR_STATE:T_STATE;SIGNALNEXT_STATE:T_STATE;SIGNALCOUNTER_K:T_SHORT;SIGNALENABLE_COUNT_K:STD_LOGIC;SIGNALCOUNT_K_END:STD_LOGIC;SIGNALCOUNTER_A:T_SHORT;SIGNALENABLE_COUNT_A:STD_LOGIC;SIGNALCOUNT_A_END:STD_LOGIC;BEGINPROCESS(CLK,RESET)ISBEGINIFRESET='1'THENCURR_STATE<=S0;ELSIFRISING_EDGE(CLK)THENCURR_STATE<=NEXT_STATE;ENDIF;ENDPROCESS;PROCESS(KEY,ALARM_BUTTON,TIME_BUTTON,CURR_STATE,COUNT_A_END,COUNT_K_END)BEGINNEXT_STATE<=CURR_STATE;LOAD_NEW_A<='0';LOAD_NEW_C<='0';SHOW_A<='0';SHOW_NEW_TIME<='0';ENABLE_COUNT_K<='0';ENABLE_COUNT_A<='0';CASECURR_STATEISWHENS0=>IF(KEY='0')THENNEXT_STATE<=S1;SHOW_NEW_TIME<='1';ELSIF(ALARM_BUTTON='1')THENNEXT_STATE<=S4;SHOW_A<='1';ELSENEXT_STATE<=S0;ENDIF;WHENS1=>IF(KEY='1')THENNEXT_STATE<=S1;ELSIF(ALARM_BUTTON='1')THENNEXT_STATE<=S2;LOAD_NEW_A<='1';ELSIF(TIME_BUTTON='1')THENNEXT_STATE<=S3;LOAD_NEW_C<='1';ELSEIF(COUNT_K_END='1')THENNEXT_STATE<=S0;ELSENEXT_STATE<=S1;ENDIF;ENABLE_COUNT_K<='1';ENDIF;SHOW_NEW_TIME<='1';WHENS2=>IF(ALARM_BUTTON='1')THENNEXT_STATE<=S2;LOAD_NEW_A<='1';ELSENEXT_STATE<=S0;ENDIF;WHENS3=>IF(TIME_BUTTON='1')THENNEXT_STATE<=S3;LOAD_NEW_C<='1';ELSENEXT_STATE<=S0;--ENDIF;WHENS4=>IF(KEY='1')THENNEXT_STATE<=S1;ELSENEXT_STATE<=S4;IF(COUNT_A_END='1')THENNEXT_STATE<=S0;ELSENEXT_STATE<=S4;SHOW_A<='1';ENDIF;ENABLE_COUNT_A<='1';ENDIF;WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;COUNT_KEY:PROCESS(ENABLE_COUNT_K,CLK)ISBEGINIF(ENABLE_COUNT_K='0')THENCOUNTER_K<=0;COUNT_K_END<='0';ELSIF(RISING_EDGE(CLK))THENIF(COUNTER_K>=KEY_TIMEOUT)THENCOUNT_K_END<='1';ELSECOUNTER_K<=COUNTER_K+1;ENDIF;ENDIF;ENDPROCESS;COUNT_ALARM:PROCESS(ENABLE_COUNT_A,CLK)ISBEGINIF(ENABLE_COUNT_A='0')THENCOUNTER_A<=0;COUNT_A_END<='0';ELSIFRISING_EDGE(CLK)THENIF(COUNTER_A>=SHOW_ALARM_TIMEOUT)THENCOUNT_A_END<='1';ELSECOUNTER_A<=COUNTER_A+1;ENDIF;ENDIF;ENDPROCESS;ENDARCHITECTUREBEHAVE;7.5.4鬧鐘系統(tǒng)的預(yù)置寄存器的設(shè)計圖7.18預(yù)置寄存器示意圖例【7-19】--預(yù)置寄存器的VHDL源程序KEYBUFFER.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEWORK.P_ALARM.ALL;ENTITYKEYBUFFERISPORT(KEY:INSTD_LOGIC;CLK:INSTD_LOGIC;RESET:INSTD_LOGIC;KEYNUM:OUTSTD_LOGIC_VECTOR(3DOWNTO0);NEW_TIME:OUTT_CLOCK_TIME);ENDENTITYKEYBUFFER;ARCHITECTUREBEHAVEOFKEYBUFFERISSIGNALN_T:T_CLOCK_TIME;SIGNALCNT:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALTEMP:T_DIGITAL;BEGINPROCESS(CLK)ISBEGINIF(CLK'EVENTANDCLK='1')THENIFCNT=9THENCNT<="0000";ELSE