EDA技術(shù)與FPGA應(yīng)用設(shè)計(jì) 第三版 課件 第6章常用電路的VHDL描述

第6章常用電路的VHDL描述組合電路設(shè)計(jì)時(shí)序電路設(shè)計(jì)存儲(chǔ)器設(shè)計(jì)本章內(nèi)容：6.1組合邏輯電路VHDL描述組合邏輯電路的功能可以用真值表、表達(dá)式、電路圖等方式描述?；谶@3種方式可以分別采用行為式、數(shù)據(jù)流式和結(jié)構(gòu)式的VHDL描述風(fēng)格及層次。常見(jiàn)的組合邏輯電路：基本門電路加法器編碼器譯碼器選擇器分配器等組合電路的VHDL描述方法：

1、真值表：行為描述（IF：有優(yōu)先級(jí)；CASE），例如優(yōu)先編碼器例7-7、譯碼器例7-8

2、表達(dá)式：數(shù)據(jù)流（賦值），例如比較器例7-9、加法器例5-26

3、邏輯電路：結(jié)構(gòu)式（元件例化），例如等值比較器例4-5、例7-3。

4、三態(tài)門及雙向電路設(shè)計(jì):例7-15、例7-176.1組合邏輯電路VHDL描述6.1組合邏輯電路VHDL描述行為式1：【例6-7】?jī)?yōu)先編碼器74LS148程序設(shè)計(jì)。真值表符號(hào)libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;entityencoder_74ls148isport(d:instd_logic_vector(7downto0); st:instd_logic; y:outstd_logic_vector(2downto0); yex:outstd_logic; ys:outstd_logic);endencoder_74ls148;6.1組合邏輯電路VHDL描述程序設(shè)計(jì)—實(shí)體architectureBehavioralofencoder_74ls148isbeginprocess(st,d)beginifst='1'then

y<="111"; yex<='1';s<='1';

elsifd="11111111"then y<="111"; yex<='1';ys<='0';elsifd(7)='0'then

y<="000"; yex<='0';ys<='1';

…

…elsifd(0)='0'then y<="111"; yex<='0';ys<='1';endif;endprocess;endBehavioral;6.1組合邏輯電路VHDL描述程序設(shè)計(jì)—結(jié)構(gòu)體行為式2：【例6-8】譯碼器74LS138程序設(shè)計(jì)。6.1組合邏輯電路VHDL描述真值表符號(hào)libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;entitydecoderisport(sta:instd_logic; stb:instd_logic; stc:instd_logic; a:instd_logic_vector(2downto0); y:outstd_logic_vector(7downto0) );enddecoder;6.1組合邏輯電路VHDL描述程序設(shè)計(jì)—實(shí)體architectureBehavioralofdecoderisbeginprocess(sta,stb,stc,a)begin if(sta='1'andstb='0'andstc='0')then caseaiswhen"000"=>y<="11111110";

…

…

when"111"=>y<="01111111";

whenothers=>y<="11111111"; endcase; else y<="11111111"; endif;endprocess;endBehavioral;6.1組合邏輯電路VHDL描述程序設(shè)計(jì)—結(jié)構(gòu)體libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;

entitycompisport(a:instd_logic_vector(3downto0); b:instd_logic_vector(3downto0);a_greater_b:outstd_logic;a_less_b:outstd_logic;a_equal_b:outstd_logic);endcomp;6.1組合邏輯電路VHDL描述行為式3：【例6-9】?jī)蓚€(gè)4位二進(jìn)制數(shù)比較器程序設(shè)計(jì)。architectureBehavioral1ofcompisbeginprocess(a,b) begin ifa>bthena_greater_b<='1';a_less_b<='0';a_equal_b<='0'; elsifa<bthen a_greater_b<='0';a_less_b<='1';a_equal_b<='0'; else a_greater_b<='0';a_less_b<='0'; a_equal_b<='1'; endif;endprocess;endBehavioral1;6.1組合邏輯電路VHDL描述architectureBehavioral2ofcompisbegina_greater_b<='1'whena>belse‘0’; a_less_b<='1'whena<belse‘0’; a_equal_b<='1'whena=belse‘0’;endBehavioral2;6.1組合邏輯電路VHDL描述6.1組合邏輯電路VHDL描述數(shù)據(jù)流式：例5-26全加器真值表表達(dá)式libraryieee;useieee.std_logic_1164.all;entityadder1isport(a,b,ci:instd_logic;co,s:outstd_logic);endadder1;6.1組合邏輯電路VHDL描述程序設(shè)計(jì)—實(shí)體6.1組合邏輯電路VHDL描述architecturebehavioralofadder1ISbeginco<=(aandb)or(aandci)or(bandci);s<=axorbxorci;endbehavioral;程序設(shè)計(jì)—結(jié)構(gòu)體結(jié)構(gòu)化:例4-5（4位等值比較器）、

【例6-3】4輸入與邏輯設(shè)計(jì)6.1組合邏輯電路VHDL描述表達(dá)式:結(jié)構(gòu)圖:6.1組合邏輯電路VHDL描述兩輸入與邏輯設(shè)計(jì)【例6-1】:libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;entityand_gate_2isport(a:instd_logic; b:instd_logic;f:outstd_logic);endand_gate_2;architectureBehavioralofand_gate_2isbeginf<=aandb;endBehavioral;6.1組合邏輯電路VHDL描述4輸入與邏輯程序設(shè)計(jì)：architectureBehavioralofand_gate_4is

signaltemp1,temp2:std_logic;componentand_gate_2isport(a:instd_logic; b:instd_logic; f:outstd_logic);endcomponent;begin

U1:and_gate_2portmap(a=>a,b=>b,f=>temp1);

U2:and_gate_2portmap(a=>c,b=>d,f=>temp2);

U3:and_gate_2portmap(temp1,temp2,f);

endBehavioral;

6.1組合邏輯電路VHDL描述libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;entitytri_gateisport(a:instd_logic; b:instd_logic; en:instd_logic; f:outstd_logic);endtri_gate;6.1.7三態(tài)門電路描述例6-13三態(tài)與非門6.1.7三態(tài)門電路描述architectureBehavioraloftri_gateisbegin process(a,b,en) begin ifen='1'then f<=anandb; else

f<='Z'; endif; endprocess;endBehavioral;6.1.7三態(tài)門電路描述單向總線驅(qū)動(dòng)器在微型計(jì)算機(jī)的總線驅(qū)動(dòng)中經(jīng)常要用單向總線緩沖器，它通常由多個(gè)三態(tài)門組成，用來(lái)驅(qū)動(dòng)地址總線和控制總線。一個(gè)8位的單向總線緩沖器如下圖所示。單向總線驅(qū)動(dòng)器程序設(shè)計(jì)—實(shí)體LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；ENTITYTRI_BUF8ISPORT(DIN：INSTD_LOGIC_VECTOR(7DOWNTO0)；

EN：INSTD_LOGIC；

DOUT：OUTSTD_LOGIC_VECTOR(7DOWNTO0))；ENDENTITYTRI_BUF8；單向總線驅(qū)動(dòng)器ARCHITECTUREARTOFTRI_BUF8ISBEGINPROCESS(EN，DIN)ISBEGINIF(EN=‘1’)THENDOUT<=DIN；

ELSE

DOUT<="ZZZZZZZZ"；

ENDIF；

ENDPROCESS；ENDARCHITECTUREART；程序設(shè)計(jì)—結(jié)構(gòu)體多通道三態(tài)總線電路設(shè)計(jì)【例】8位4通道三態(tài)總線結(jié)構(gòu)圖：多通道三態(tài)總線電路設(shè)計(jì)libraryieee;useieee.std_logic_1164.all;entitytriisport(ctl:instd_logic_vector(1downto0);datain1，datain2，datain3，datain4:instd_logic_vector(7downto0);q:outstd_logic_vector(7downto0));endtri;architecturebody_trioftriisbegin

q<=datain1whenctl="00"else(others=>'Z');q<=datain2whenctl="01"else(others=>'Z');q<=datain3whenctl="10"else(others=>'Z');q<=datain4whenctl="11"else(others=>'Z');endbody_tri;程序設(shè)計(jì)：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYBIDIRISPORT(A,B：INOUTSTD_LOGIC_VECTOR(7DOWNTO0);DIR：INSTD_LOGIC);ENDENTITYBIDIR;6.1.8雙向端口ABDIR結(jié)構(gòu)圖：雙進(jìn)程描述：【例】6-14程序設(shè)計(jì)—實(shí)體ARCHITECTUREARTOFBIDIRISSIGNALAOUT,BOUT：STD_LOGIC_VECTOR(7DOWNTO0);BEGINPROCESS(A,DIR)IS --A為輸入BEGINIF(DIR=‘1’)THENBOUT<=A;ELSEBOUT<="ZZZZZZZZ"；

ENDIF;B<=BOUT; --B為輸出ENDPROCESS;6.1.8雙向端口程序設(shè)計(jì)—結(jié)構(gòu)體ABDIRPROCESS(B,DIR)IS --B為輸入BEGINIF(DIR=‘0’)THENAOUT<=B;ELSEAOUT<="ZZZZZZZZ";ENDIF;A<=AOUT; --A為輸出ENDPROCESS;ENDARCHITECTUREART;6.1.8雙向端口進(jìn)程B設(shè)計(jì)：ABDIRARCHITECTUREARTOFBIDIRISBEGINProcess(A,B,DIR)beginif(DIR='0')thenA<=B;

B<="ZZZZZZZZ";ElseB<=A;

A<="ZZZZZZZZ";endif;endprocess;ENDARCHITECTUREART;6.1.8雙向端口單進(jìn)程描述：【例】6-15ABDIR時(shí)序電路的VHDL描述方法

（1）PROCESS+IF：

1、PROCESS

敏感表中放異步控制信號(hào)、時(shí)鐘信號(hào)；

多進(jìn)程對(duì)應(yīng)異步結(jié)構(gòu)。

2、IF：

不完整if形成觸發(fā)器結(jié)構(gòu)；

條件判斷順序?qū)?yīng)控制信號(hào)的優(yōu)先級(jí)。

（2）有限狀態(tài)機(jī)描述控制部件6.2時(shí)序邏輯電路設(shè)計(jì)常用時(shí)序部件

6.2時(shí)序邏輯電路設(shè)計(jì)觸發(fā)器；計(jì)數(shù)器；序列信號(hào)發(fā)生器；序列信號(hào)檢測(cè)器；狀態(tài)控制器

6.2.1觸發(fā)器時(shí)鐘

鎖存器、寄存器同步、異步控制復(fù)位、置位信號(hào)邊沿提取應(yīng)用

...PROCESS(CLK，D)BEGINIFCLK='1'THEN--電平觸發(fā)型寄存器

Q<=D;ENDIF;ENDPROCESS;鎖存器、寄存器

鎖存器鎖存器、寄存器

D觸發(fā)器：例6-16architectureBehavioralofd_cfqisbeginprocess(clk,d)beginifclk'eventandclk='1'then--時(shí)鐘上升沿

q<=d;endif;endprocess;endBehavioral;LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；ENTITYASYNDCFQISPORT(CLK，D，PRESET，CLR：INSTD_LOGIC；

Q：OUTSTD_LOGIC)；ENDENTITYASYNDCFQ；同步、異步控制

異步復(fù)位、置位控制D觸發(fā)器ARCHITECTUREARTOFASYNDCFQISBEGINPROCESS(CLK，PRESET，CLR)ISBEGINIF(PRESET=‘0')THEN--置位

Q<='1'；

ELSIF(CLR=‘0')THEN--復(fù)位

Q<='0'；

ELSIF(CLK'EVENTANDCLK=‘1’)THENQ<=D；

ENDIF；ENDPROCESS；ENDARCHITECTUREART；異步控制

LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；ENTITYSYNDCFQISPORT(D，CLK，RESET：INSTD_LOGIC；

Q：OUTSTD_LOGIC)；ENDENTITYSYNDCFQ；同步、異步控制

同步復(fù)位控制D觸發(fā)器ARCHITECTUREARTOFSYNDCFQISBEGINPROCESS(CLK)ISBEGINIF(CLK'EVENTANDCLK=‘1’)THENIF(RESET=‘0’)THEN Q<=‘0’；--時(shí)鐘邊沿到來(lái)且有復(fù)位信號(hào)，觸發(fā)器被復(fù)位

ELSEQ<=D；

ENDIF；ENDIF；ENDPROCESS；ENDARCHITECTUREART；同步控制

【例6-19】設(shè)計(jì)信號(hào)上升沿和下降沿提取電路。libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;entitycnt4isport(rst:instd_logic;clk:instd_logic;d:instd_logic;d_up:outstd_logic;d_down:outstd_logic );endcnt4;信號(hào)邊沿提取

architectureBehavioralofcnt4issignald1,d2:std_logic;beginprocess(clk,rst,d)beginifrst='0'then d1<='0';d2<='0';elsifclk'eventandclk='1'then

d1<=d;d2<=d1;endif;endprocess;

信號(hào)邊沿提取

d_up<=d1and(notd2);d_down<=(notd1)andd2;endBehavioral;信號(hào)邊沿提取

信號(hào)邊沿提取

計(jì)數(shù)器是在數(shù)字系統(tǒng)中使用最多的時(shí)序電路，它不僅能用于對(duì)時(shí)鐘脈沖計(jì)數(shù)，還可以用于分頻、定時(shí)、產(chǎn)生節(jié)拍脈沖和脈沖序列以及進(jìn)行數(shù)字運(yùn)算等。6.2.2計(jì)數(shù)器二進(jìn)制、非二進(jìn)制計(jì)數(shù)器同步、異步計(jì)數(shù)器序列信號(hào)發(fā)生器應(yīng)用libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;Entitycounter4isport(clk:instd_logic;cnt:outstd_logic_vector(3downto0) );endcounter4;二進(jìn)制計(jì)數(shù)器【例6-20】4位二進(jìn)制加法計(jì)數(shù)器的設(shè)計(jì)。architectureBehavioralofcounter4issignalcnt1:std_logic_vector(3downto0):="0000";beginprocess(clk)beginifclk'eventandclk='1'then

cnt1<=cnt1+1;endif;endprocess;cnt<=cnt1;endBehavioral;二進(jìn)制計(jì)數(shù)器libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitycounter12isport(rst:instd_logic;--復(fù)位輸入信號(hào)

en:instd_logic;--計(jì)數(shù)使能信號(hào)

clk:instd_logic;--輸入時(shí)鐘信號(hào)

q:outstd_logic--十二分頻輸出信號(hào)

);endcounter12;非二進(jìn)制計(jì)數(shù)器【例6-21】12分頻器architectureBehavioralofcounter12is

signalcnt1:std_logic_vector(3downto0):="0000";beginprocess(rst,clk)beginifrst='0'thencnt1<=(others=>'0');elsifclk'eventandclk='1'thenifen=’1’then

ifcnt1=11thencnt1<=(others=>'0'); else cnt1<=cnt1+1; endif;endif;endif;endprocess;

q<='1'whencnt1=11else'0';endBehavioral;非二進(jìn)制計(jì)數(shù)器libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitycnt10is port(rst:instd_logic; clk:instd_logic; cnt:bufferstd_logic_vector(3downto0) );endcnt10;BCD十進(jìn)制計(jì)數(shù)器例4-26：模值為10的計(jì)數(shù)器architectureBehavioralofcnt10isbeginprocess(clk,rst)beginifrst='0'then cnt<="0000"; elsifclk'eventandclk='1'then ifcnt=9then

cnt<="0000"; else

cnt<=cnt+1;

endif; endif;endprocess;endBehavioral;BCD十進(jìn)制計(jì)數(shù)器LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；USEIEEE.STD_LOGIC_UNSIGNED.ALL；

ENTITYCNTM60ISPORT(CI：INSTD_LOGIC；--計(jì)數(shù)控制

NRESET：INSTD_LOGIC；--異步復(fù)位控制

LOAD：INSTD_LOGIC；--置數(shù)控制

D：INSTD_LOGIC_VECTOR(7DOWNTO0)；

CLK：INSTD_LOGIC；

CO：OUTSTD_LOGIC； --進(jìn)位輸出

QH,QL：BUFFERSTD_LOGIC_VECTOR(3DOWNTO0))；

--輸出高4位、輸出低4位

ENDENTITYCNTM60；BCD六十進(jìn)制計(jì)數(shù)器模為60，具有異步復(fù)位、同步置數(shù)功能的8421BCD碼計(jì)數(shù)器。ARCHITECTUREARTOFCNTM60ISBEGINCO<=‘1’WHEN(QH="0101"ANDQL="1001"ANDCI=‘1’)ELSE'0'；

--進(jìn)位輸出的產(chǎn)生PROCESS(CLK，NRESET)ISBEGINIF(NRESET=‘0’)THEN--異步復(fù)位

QH<=“0000”；QL<=“0000”；ELSIF(CLK'EVENTANDCLK=‘1’)THEN--同步置數(shù)

IF(LOAD=‘1’)THENQH<=D(7DOWNTO4)；

QL<=D(3DOWNTO0)；

ELSIF(CI=‘1’)THEN --模60的實(shí)現(xiàn)BCD六十進(jìn)制計(jì)數(shù)器IF(QL=9)THEN--低位計(jì)數(shù)實(shí)現(xiàn)

QL<="0000"；

IF(QH=5)THEN--高位計(jì)數(shù)實(shí)現(xiàn)

QH<=“0000”；

ELSE QH<=QH+1；

ENDIF；

ELSEQL<=QL+1；

ENDIF；--ENDIFCIENDIF；--ENDIFLOAD ENDIF；ENDPROCESS；ENDARCHITECTUREART；BCD六十進(jìn)制計(jì)數(shù)器多進(jìn)程同步BCD六十進(jìn)制計(jì)數(shù)器CNT1：PROCESS(CLK，NRESET)IS--個(gè)位BEGINIF(NRESET=‘0’)THEN--異步復(fù)位 QL<=“0000”；ELSIF(CLK'EVENTANDCLK=‘1’)THEN--同步置數(shù)IF(LOAD=‘1’)THENQL<=D(3DOWNTO0)；ELSIF(CI=‘1’)THENIF(QL=9)THEN--模10計(jì)數(shù)

QL<=“0000”；

ELSEQL<=QL+1；

ENDIF；ENDIF；ENDPROCESSCNT1；CNT2：PROCESS(CLK，NRESET)IS--十位BEGINIF(NRESET=‘0’)THEN --異步復(fù)位 QH<="0000"；ELSIF(CLK'EVENTANDCLK=‘1’)THEN--同步置數(shù)IF(LOAD=‘1’)THENQH<=D(7DOWNTO4)；ELSIF(CI=‘1’)AND(QL=9)THEN IF(QH=5)THEN--模6計(jì)數(shù)

QH<=“0000”；

ELSEQH<=QH+1;ENDIF;ENDIF;ENDPROCESSCNT2;多進(jìn)程同步BCD六十進(jìn)制計(jì)數(shù)器…SIGNALCLK10：STD_LOGIC；BEGINCNT1：PROCESS(CLK)IS--個(gè)位BEGINIF(CLK'EVENTANDCLK=‘1’)THENIF(QL=9)THEN--模10計(jì)數(shù)

QL<=“0000”；

CKL10<=‘1’;ELSEQL<=QL+1；

CKL10<=‘0’;ENDIF；ENDIF；ENDPROCESSCNT1； 多進(jìn)程異步BCD六十進(jìn)制計(jì)數(shù)器CNT2：PROCESS(CLK10)IS--十位BEGINIF(CLK10'EVENTANDCLK10=‘1’)THEN IF(QH=5)THEN--模6計(jì)數(shù)

QH<=“0000”；

ELSEQH<=QH+1;ENDIF;ENDIF;ENDPROCESSCNT2;多進(jìn)程異步BCD六十進(jìn)制計(jì)數(shù)器libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityseq_genisport(clk:instd_logic;rst:instd_logic;q:outstd_logic );endseq_gen;序列信號(hào)發(fā)生器【例6-22】利用計(jì)數(shù)器方式設(shè)計(jì)產(chǎn)生序列信號(hào)“11011001”architectureBehavioralofseq_genissignald:std_logic_vector(2downto0);beginCNT:process(rst,clk)beginifrst='0'then d<="000"; elsifclk'eventandclk='1'then d<=d+1; endif;endprocessCNT;序列信號(hào)發(fā)生器【例6-23】COM:process(clk,d)begin

ifclk'eventandclk='1'thencasedis when"000"=>q<='1';when"001"=>q<='1'; when"010"=>q<='0'; when"011"=>q<=‘1'; when"100"=>q<=‘1';when"101"=>q<=‘0'; when"110"=>q<='0'; when"111"=>q<='1'; whenothers=>q<='Z'; endcase;

endif;endprocessCOM;endBehavioral;序列信號(hào)發(fā)生器序列信號(hào)發(fā)生器單向移位寄存器雙向移位寄存器6.2.3移位寄存器【例6-24】4位單向移位寄存器設(shè)計(jì)單向移位寄存器libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityreg4isport(clk:instd_logic;

din:instd_logic;q:outstd_logic_vector(3downto0) );endreg4;單向移位寄存器程序設(shè)計(jì)—實(shí)體architectureBehavioralofreg4issignalqin:std_logic_vector(3downto0);beginprocess(clk,din)beginifclk'eventandclk='1'thenqin<=qin(2downto0)&din;endif;endprocess;q<=qin;endBehavioral;單向移位寄存器程序設(shè)計(jì)—結(jié)構(gòu)體雙向移位寄存器【例6-25】8位雙向移位寄存器設(shè)計(jì)具有同步置數(shù)、同步清零、左移、右移功能：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityreg4isport(clk,rst:instd_logic;din_left:instd_logic;din_right:instd_logic;sel:instd_logic_vector(1downto0);din:instd_logic_vector(7downto0);q:outstd_logic_vector(7downto0));endreg4;雙向移位寄存器程序設(shè)計(jì)—實(shí)體architectureBehavioralofreg4issignalqin:std_logic_vector(7downto0);beginprocess(clk,sel)beginifclk'eventandclk='1'then ifrst='0'thenqin<=(others=>'0'); elsifsel="11"then qin<=din; elsifsel="01"then

qin<=qin(6downto0)&din_left;

elsifsel="10"then

qin<=din_right&qin(7downto1);endif; endif;endprocess;

q<=qin;endBehavioral;雙向移位寄存器程序設(shè)計(jì)—結(jié)構(gòu)體6.2.4狀態(tài)機(jī)設(shè)計(jì)狀態(tài)機(jī)結(jié)構(gòu)狀態(tài)機(jī)信號(hào)：

輸入、輸出；現(xiàn)態(tài)、次態(tài)；時(shí)鐘、復(fù)位。7.2.4狀態(tài)機(jī)狀態(tài)機(jī)操作(1)狀態(tài)機(jī)內(nèi)部狀態(tài)轉(zhuǎn)換（次態(tài)指定和時(shí)鐘驅(qū)動(dòng)轉(zhuǎn)移）。狀態(tài)機(jī)的下一狀態(tài)由狀態(tài)譯碼器根據(jù)當(dāng)前狀態(tài)和輸入條件決定。(2)產(chǎn)生輸出信號(hào)序列。輸出信號(hào)由輸出譯碼器根據(jù)當(dāng)前狀態(tài)和輸入條件決定。在產(chǎn)生輸出的過(guò)程中，由是否使用輸入信號(hào)可以確定狀態(tài)機(jī)的類型。兩種典型的狀態(tài)機(jī)是摩爾(MOORE)狀態(tài)機(jī)和米立(MEALY)狀態(tài)機(jī)。狀態(tài)機(jī)設(shè)計(jì)方法：雙進(jìn)程描述7.2.4狀態(tài)機(jī)狀態(tài)信號(hào)定義方法1：使用枚舉型數(shù)據(jù)類型來(lái)指定現(xiàn)態(tài)、次態(tài)的類型；

Typestatesis(s0,s1,s2,s3,s4,s5,s6,s7);

signalcurrent_sta，next_sta:states;

方法2：直接對(duì)狀態(tài)進(jìn)行編碼，定義狀態(tài)常量；signalcurrent_sta,next_sta:std_logic_vector(2downto0);

constants0:std_logic_vector(2downto0):=“000”;

…constants7:std_logic_vector(2downto0):=“111”;7.2.4狀態(tài)機(jī)應(yīng)用一：序列信號(hào)發(fā)生器【例6-26】使用狀態(tài)機(jī)方式設(shè)計(jì)序列信號(hào)發(fā)生器，輸出“11000101···”序列。7.2.4狀態(tài)機(jī)S0S1S2S3/1/1/0S7S6S5S4/0/1/0/輸出/0/1libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;Entitystate_seqisport(clk:instd_logic;rst:instd_logic;q:outstd_logic );endstate_seq;序列信號(hào)發(fā)生器程序設(shè)計(jì)—實(shí)體architectureBehavioralofstate_seqistypestateis(s0,s1,s2,s3,s4,s5,s6,s7);--定義狀態(tài)信號(hào)

signalpresent_state,next_state:state;beginREG:process(rst,clk)--時(shí)序進(jìn)程beginifrst='0'then present_state<=s0;elsifclk'eventandclk='1'then present_state<=next_state;endif;endprocessREG;序列信號(hào)發(fā)生器程序設(shè)計(jì)—結(jié)構(gòu)體COM:process(present_state)--組合進(jìn)程begincasepresent_stateis whens0=>q<='1';next_state<=s1; whens1=>q<='1';next_state<=s2; whens2=>q<='0';next_state<=s3; whens3=>q<='0';next_state<=s4; whens4=>q<='0';next_state<=s5; whens5=>q<='1';next_state<=s6; whens6=>q<='0';next_state<=s7; whens7=>q<='1';next_state<=s0; whenothers=>q<='0';next_state<=s0;endcase;endprocessCOM;endBehavioral;序列信號(hào)發(fā)生器architectureBehavioralofstate_seqistypestateis(s0,s1,s2,s3,s4,s5,s6,s7);--定義狀態(tài)信號(hào)

signalpresent_state:state;beginREG:process(rst,clk)--時(shí)序進(jìn)程beginifrst='0'then present_state<=s0;elsifclk'eventandclk='1'then

序列信號(hào)發(fā)生器（單進(jìn)程）程序設(shè)計(jì)—結(jié)構(gòu)體casepresent_stateis whens0=>q<='1';present_state<=s1; whens1=>q<='1';present_state<=s2; whens2=>q<='0';present_state<=s3; whens3=>q<='0';present_state<=s4; whens4=>q<='0';present_state<=s5; whens5=>q<='1';present_state<=s6; whens6=>q<='0';present_state<=s7; whens7=>q<='1';present_state<=s0; whenothers=>q<='0';present_state<=s0;endcase;endif;endprocessREG;endBehavioral;序列信號(hào)發(fā)生器（單進(jìn)程）應(yīng)用二：序列檢測(cè)器【例6-27】使用狀態(tài)機(jī)方式設(shè)計(jì)“11000101···”序列檢測(cè)器。7.2.4狀態(tài)機(jī)S0S1S2S31/0S7S6S5S4輸入/輸出0/01/11/00/00/00/01/0libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityseq_detectisport(clk:instd_logic;rst:instd_logic;din:instd_logic;q:outstd_logic );endseq_detect;序列檢測(cè)器程序設(shè)計(jì)—實(shí)體architectureBehavioralofseq_detectistypestateis(s0,s1,s2,s3,s4,s5,s6,s7);signalcurrent_state,next_state:state;beginREG:process(clk,rst)beginifrst='0'then current_state<=s0;elsifclk'eventandclk='1'then current_state<=next_state;endif;endprocessREG;序列檢測(cè)器程序設(shè)計(jì)—結(jié)構(gòu)體process(current_state,din)begincasecurrent_stateis whens0=>ifdin='1'thennext_state<=s1; else next_state<=s0; endif; q<='0';……whens7=>ifdin='1'thenq<=‘1'; else q<='0'; endif;

next_state<=s0;endcase;endprocess;endBehavioral;序列檢測(cè)器6.3存儲(chǔ)器設(shè)計(jì)ROMRAM6.3.1ROMROM一般用來(lái)存儲(chǔ)固定值參數(shù)，輸入信號(hào)有時(shí)鐘、地址、使能，輸出信號(hào)為存儲(chǔ)數(shù)據(jù)。以一個(gè)深度為16、數(shù)據(jù)寬度為8位的ROM存儲(chǔ)器為例介紹ROM存儲(chǔ)器的設(shè)計(jì)。7.3.1ROM【例6-28】ROM存儲(chǔ)器設(shè)計(jì)libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityrom_16_8isport(clk:instd_logic;en:instd_logic; addr:instd_logic_vector(3downto0); data:outstd_logic_vector(7downto0));endrom_16_8;7.3.1ROMarchitectureBehavioralofrom_16_8isbeginprocess(clk,en,addr)beginifclk'eventandclk='1'then ifen='1'then caseaddris when"0000"=>data<="00000001"; …… when"1111"=>data<="10000011";