實(shí)驗(yàn)4-PWM控制技術(shù)

實(shí)驗(yàn)4PWM(PulseWidthModulation)控制技術(shù)占空比〔DutyRatio，DutyCycle〕：指脈沖信號(hào)的通電時(shí)間與通電周期之比。〔高電平在一個(gè)周期之內(nèi)所占的時(shí)間比率。〕PWM是一種對(duì)模擬信號(hào)進(jìn)行數(shù)字編碼的方法。通過高分辨率計(jì)數(shù)器的使用，方波的占空比被調(diào)制用來對(duì)一個(gè)具體模擬信號(hào)的電平進(jìn)行編碼。MSP430的定時(shí)器資源：WDT，BasicTimer，Timer_A〔該系列器件均有〕，Timer_B，Timer_D，實(shí)時(shí)時(shí)鐘等。Timer_A0 Timer0_A5〔5個(gè)CCR〕Timer_A1 Timer1_A3〔3個(gè)CCR〕Timer_A2 Timer2_A3〔3個(gè)CCR〕Timer_ARegisters：TAxCTL Timer_AxControlRegisterTAxCCTL0-TAxCCTL6 Timer_A捕獲/比擬控制存放器0-6TAxR Timer_AxCounterRegisterTAxCCR0-TAxCCR6 Timer_A捕獲/比擬存放器0-6TAxEX0 Timer_A擴(kuò)展存放器0TAxIV Timer_A中斷向量存放器〔1〕TAxCTL，Timer_AxControlRegisterTASSEL bit9-bit8 Timer_AclocksourceselectID bit7-bit6 Inputdivider〔1/2/4/8〕MC bit5-bit4 ModecontrolTACLR bit2 Timer_AclearTAIE bit1 Timer_AinterruptenableTAIFG bit0 Timer_Ainterruptflag以上位存放器的復(fù)位值均為0hTAxCCTLn，Timer_AxCapture/CompareControlnRegisterCM bit15-bit14 CapturemodeCCIS bit13-bit12 Capture/compareinputselectSCS bit11 SynchronizecapturesourceSCCI bit10 Synchronizedcapture/compareinputCAP bit8 Capturemode〔0，比擬模式；1，捕獲模式〕OUTMOD bit7-bit5 OutputmodeCCIE bit4 Capture/compareinterruptenable〔0，禁止；1，使能〕CCI bit3 Capture/compareinputOUT bit2 OutputCOV bit1 CaptureoverflowflagCCIFG bit0 Capture/compareinterruptflag以上位存放器的復(fù)位值均為0hTAxR，Timer_AxCounterRegister，thecountofTimer_ATAxCCRn，Timer_ACapture/ComparenRegister比擬模式：TAxCCRn與TAxR比擬捕獲模式：滿足捕獲條件時(shí)，硬件自動(dòng)將計(jì)數(shù)器TAxR值寫入TAxCCRnTAxEX0，Timer_AxExpansion0RegisterTAIDEX bit2-bit0 Inputdividerexpansion〔1/2/3/4/5/6/7/8〕TAxIV，Timer_AxInterruptVectorRegister，bit15-bit0[由于，Timer_A的中斷，可由計(jì)數(shù)器溢出引起，也可來自捕獲/比擬器REG，因此]TAxIV用于確定Timer_A中斷請(qǐng)求的中斷源。注：OUTMOD_7，復(fù)位/置位：TAxR=TAxCCRn時(shí)，復(fù)位；TAxR=TAxCCR0時(shí)，置位。設(shè)計(jì)參考代碼當(dāng)Timer_A的計(jì)數(shù)器工作在增計(jì)數(shù)方式，輸出采用OUTNOD_7〔復(fù)位/置位〕時(shí)，可用TAxCCR0控制PWM波形的周期，用某個(gè)TAxCCRn控制占空比，這樣Timer_A就可用產(chǎn)生任意占空比的PWM波形。圖Timer_A產(chǎn)生的PWM//*******************************************************************************//MSP430F66xDemo-Timer0_A5,PWMTA1.1-2,UpMode,32kHzACLK////Description:ThisprogramgeneratestwoPWMoutputsonP1.2,1.3using//Timer1_Aconfiguredforupmode.ThevalueinCCR0,512-1,definesthePWM//periodandthevaluesinCCR1andCCR2thePWMdutycycles.Using32kHz//ACLKasTACLK,thetimerperiodis(1/32k)*512=15.625mswitha75%duty//cycleonP1.2and25%onP1.3.NormaloperatingmodeisLPM3.//ACLK=TACLK=LFXT1=32768Hz,MCLK=SMCLK=DCOCLK=32*ACLK=defaultDCO~1.045MHz.//*******************************************************************************// 這個(gè)程序產(chǎn)生兩路PWM波形輸出。CCR0中的值定義了PWM信號(hào)的周期，CCR1，CCR2中的值// 定義了PWM信號(hào)的占空比。定時(shí)使用32K的ACLK做為輸入時(shí)鐘源，時(shí)鐘周期為：15.625ms// P1.2上PWM的占空比為75%，P1.3上PWM的占空比為25%。//////MSP430F66x/////|\||//|||//--|RST|//||//|P1.2/TA0.1|-->CCR1-75%PWM//|P1.3/TA0.2|-->CCR2-25%PWM////******************************************************************************#include<msp430f6638.h>voidmain(void){//************************************************************************* WDTCTL=WDTPW+WDTHOLD; //StopWDT//BAKCTL=1Ch,BatteryBackupControl(Page123)while(BAKCTL&LOCKIO) //UnlockXT1pinsforoperation BAKCTL&=~(LOCKIO);//LoopuntilXT1faultflagiscleareddo {//UCSCTL7&=~(XT2OFFG+XT1LFOFFG+DCOFFG); //ClearXT2,XT1,DCOfaultflags UCSCTL7&=~(XT2OFFG+XT1HFOFFG+XT1LFOFFG+DCOFFG); SFRIFG1&=~OFIFG; //ClearfaultflagsinSFR }while(SFRIFG1&OFIFG); //Testoscillatorfaultflag UCSCTL6&=~(XT1OFF); //XT1On UCSCTL6|=XCAP_3; //Internalloadcap//*************************************************************************//P1.2/TA0.1(TimerTA0CCR1)/S37;P1.3/TA0.2(TimerTA0CCR2)/S36 P1DIR|=BIT2+BIT3; //P1.2andP1.3output P1SEL|=BIT2+BIT3; //P1.2andP1.3optionsselect TA0CTL=TASSEL_1+MC_1+TACLR; //ACLK,upmode,clearTAxR//TA0CCTL0=OUTMOD_0; //(default)OUTbitvalue//給TAxCCR0寫入非零值時(shí)，它將從零開始進(jìn)行遞增計(jì)數(shù) TA0CCR0=512-1; //PWMPeriodRegisterTAxCCR0 TA0CCTL1=OUTMOD_7; //CCR1reset/set TA0CCR1=384; //CCR1PWMdutycycle,384/512=0.75 TA0CCTL2=OUTMOD_7; //CCR2reset/set TA0CCR2=128