Chap10邏輯綜合與時序仿真.ppt

1、Unit 4 VLSI設(shè)計方法,Chap10 邏輯綜合與時序仿真,Unit 1 緒論Unit 2 CMOS電路設(shè)計基礎(chǔ)Unit 3 CMOS電路的邏輯設(shè)計Unit 4 VLSI設(shè)計方法 Chap8 設(shè)計模式和設(shè)計流程 Chap9 RTL設(shè)計與仿真 Chap10 邏輯綜合與時序仿真 Chap11 可測試性設(shè)計與ATPG Chap12 版圖設(shè)計與驗證,Specification Executable model RTL code Gate-level netlist Cell/interconnect level position Mask-level geometry,System (Behav

2、ioral) level RTL Gate (Logic) level Layout (Physical) Level,設(shè)計階段 （設(shè)計抽象層）,設(shè)計結(jié)果,Logic Design & Simulation : from RTL, then in Gate-Level,Logic Synthesis 得到用已有的基本邏輯單元（庫單元）互聯(lián)并滿足一定邏輯功能的邏輯構(gòu)成 Gate-Level Simulation（門級功能仿真與動態(tài)時序分析） 一般不做這一步 Formal Verification（形式驗證） STA（Static Timing Analysis，靜態(tài)時序分析）,HDL Codin

3、g for SynthesisBased on Synopsys Design Compiler,The Importance of Quality of Source Code,Codes that are functionally equivalent, but coded differently will give different synthesis results. You cannot rely solely on Design Compiler to “fix” a poorly coded design! Try to understand the “hardware” yo

4、u are describing, to give DC the best possible starting point.,Think Hardware!,Write HDL hardware descriptions Think of the topology implied by the code Do not write HDL simulation models No explicit delays No file I/O,Think Synchronous!,Synchronous designs run smoothly through synthesis, simulation

5、, test, and layout Asynchronous designs may require hand instantiation and extensive simulation to verify Isolate asynchronous logic into separately compiled blocks,Think RTL!,Writing in an RTL coding style means describing: the circuit topology the register placement the functionality between regis

6、ters DC optimizes logic between registers: It does not optimize the register placement,Synthesis of if Statements(1),The if-else construct implies multiplexing hardware,Actual circuit implementation depends on target library and Constraints,Synthesis of if Statements(2),To infer latches, use an if s

7、tatement without an else clause,Synthesis of case Statements,imply parallel mux function,Synthesis of Flip-Flops,Synthesis of Flip-Flops,SynthesisBased on Synopsys Design Compiler,0. Introduction to Synthesis 1. Pre-Synthesis Processes 2. Constraining the Design 3. Synthesizing the Design,What Is Sy

8、nthesis?,Synthesis is the transformation of an idea into a manufacturable device to carry out an intended function.,在包含眾多結(jié)構(gòu)、功能、性能均已知的邏輯單元電路的目標工藝庫的支持下 得到目標工藝庫中單元電路的連接關(guān)系（邏輯網(wǎng)絡(luò)）的最佳實現(xiàn)方案 滿足設(shè)計電路的功能要求以及速度、面積等限制條件,Synthesis Internal Flow,Synthesis Is Constraint-Driven,Synthesis Is Path-Based,0. Introduction

9、to Synthesis Pre-Synthesis Processes Technology Library for synthesis Design Hierarchy and Partition 2. Constraining the Design 3. Synthesizing the Design,Technology Library (1),工藝庫由Foundary提供，一般是.db的格式，這種格式是DC認識的一種內(nèi)部文件格式，不能由文本方式打開 .db格式可以由文本格式.lib轉(zhuǎn)化過來,Technology Library (2),During mapping, DC will:

10、 choose functionally-correct gates from this library calculate the timing of the circuit using vendor-supplied timing data for these gates target_library is a reserved variable in DC，you should set it to point to the Technology library file(s) provided by your silicon vendor,Design Hierarchy: RISC_C

11、ORE example,Design Hierarchy (Partitioning) within HDL Description,編寫HDL代碼之前（系統(tǒng)設(shè)計階段）都需要系統(tǒng)劃分，根據(jù)功能或者其他的原則將一個系統(tǒng)層次化地分成若干個模塊，這些模塊內(nèi)部再進一步細分成模塊/子模塊 Entity (VHDL) and module (Verilog) statements define hierarchical blocks. Inference of Arithmetic Circuits (+, -, *, .) can create a new level of hierarchy. Pro

12、cess (VHDL) and always (Verilog) statements do not create hierarchy,Repartitioning to Design Hierarchy for Synthesis,在DC做綜合的過程中，默認的情況下各個模塊的層次關(guān)系是保留著的。保留著的層次關(guān)系會對DC綜合造成一定的影響，比如在優(yōu)化的過程中，各個模塊的管腳必須保留，這勢必影響到模塊邊界的優(yōu)化效果,Why Partitioning/ Repartitioning,Partitioning or Repartitioning is driven by many (often co

13、mpeting) needs: Separate distinct functions Achieve workable size and complexity Manage project in team environment Design Reuse Meet physical constraints And many, many others,Poor Partitioning: so Should Eliminate Unnecessary Hierarchy,Good Partitioning(1): No Hierarchy in Combinational Paths,Good

14、 Partitioning(2): No Hierarchy in Combinational Paths,Good Partitioning(3): Partition at Register Boundaries,Example(1): Avoid Glue Logic,Example(2): Remove Glue Logic Between Blocks,Balance Block Size in Partitioning(1),Balance Block Size in Partitioning(2),Top-Level Design Partitioning,Repartition

15、ing within Design Compiler,The group and ungroup commands modify the partitions in a design. Group creates a new hierarchical block. Ungroup removes either one or all levels of hierarchy.,Group,Ungroup,0. Introduction to Synthesis 1. Pre-Synthesis Processes 2. Constraining the Design Area Constraint

16、s Timing Constraints and Time Budgeting Environmental Attributes Clock Constraints 3. Synthesizing the Design,Specifying Area Constraints,施加了一個最大面積100單位的約束 Units are those of target library, defined by the vendor: 2-input-NAND-gate transistors square mils,Specify Timing Constraints (1),Synchronous D

17、esigns: Data arrives from a clocked device Data goes to a clocked device Objective: Define the timing constraints for all paths within a design: 1. The internal (register to register) paths 2. All input paths 3. All output paths,Specify Timing Constraints (2),1. Creating a clock constrains timing pa

18、ths between registers create_clock -period 10 get_ports Clk,Specify Timing Constraints (3),2. Constraining the Input Paths set_input_delay max (input delay) clock Clk get_ports Clk,Specify Timing Constraints (4),3. Constraining Output Paths set_output_delay max (output delay) clock Clk get_ports Clk

19、,Time Budgeting (1),What if you do not know the delays on your inputs or the setup requirements of your outputs? Create a Time Budget !,Time Budgeting (2),Time Budgeting,Time Budgeting: Example Time Budgeting for MY_BLOCK Time Budgeting for X_BLOCK and Y_BLOCK,Time Budgeting (3),Constraining for Tim

20、ing: What Is Missing?,輸入輸出的電平轉(zhuǎn)換時間(transition time)由輸入外圍電路的驅(qū)動能力和輸出外圍電路的負載大小決定 電路內(nèi)部的互連線時延的估計 當外界溫度或者電路供電電壓發(fā)生變化時，時延會相應(yīng)的改變,Environmental Attributes (1),set_driving_cell: Input Drive Strength,Environmental Attributes (2),set_load: Output Capacitive Load,Environmental Attributes (3),set_wire_load_model: N

21、et Delays,A Wire Load Model (WLM) is an estimate of a nets RC parasitics based on the nets fanout: Model is created by your vendor Estimates are based on statistics from other designs the vendor has fabricated using this process Specifying WLM in Design Compiler,Environmental Attributes (4),Operatin

22、g Conditions Why? Library cells are usually characterized using “nominal” voltage and temperature. If not What? Vendors allow for synthesis of circuits which will not operate under “nominal” conditions by embedding other operating conditions in the technology libraries vendor-supplied operating cond

23、itions (vendors might deliver multiple technology libraries ),Operating Conditions To set operating conditions, enter set_operating_conditions command During synthesis, “nominal” cell and wire delays will be scaled based on the operating conditions,Clock Constraints (1),Recall Timing Constraints,Clo

24、ck Constraints (2),對時鐘網(wǎng)絡(luò)進行綜合時，需要在時鐘的各條路徑上要插入大小不一的buffer，目的是為了保證時鐘到達每個觸發(fā)器的時延盡量相等 在定義時鐘之后，都要給該時鐘設(shè)置dont_touch，告訴DC不要對時鐘網(wǎng)絡(luò)進行綜合（插入Buffer）。這是因為綜合時鐘網(wǎng)絡(luò)需要考慮單元的實際物理位置，這是前端的邏輯綜合（DC）不能完成的工作,Clock Constraints (3),Modeling Clock Skew 雖然DC無法最終綜合時鐘樹，但是可以加入一些約束讓此時的時鐘更加接近實際的工作情況 實際的時鐘達到各個觸發(fā)器的時間不是一樣的，它們之間的偏差稱為時鐘偏差(Clo

25、ck Skew)。為了反映這個偏差，我們在綜合時可以用一個命令來模擬它,Clock Constraints (4),Modeling Source Latency Clock到達模塊的端口后，要到達內(nèi)部的觸發(fā)器，也要經(jīng)過一定的延時，這個延時稱為Network Latency,0. Introduction to Synthesis 1. Pre-Synthesis Processes 2. Constraining the Design 3. Synthesizing the Design Multiple Instances How to Compile a Hierarchical Des

26、ign Timing Analysis and Report,Multiple Instances (1),Designs Instantiated More Than Once uniquify compile + dont_touch,Multiple Instances (2),uniquify vs. compile + dont_touch compile+dont_touch 由于只需對多次例化的模塊編譯一次，可以減少整個設(shè)計的編譯時間，減少內(nèi)存的使用量。在多次例化的模塊很復雜并且工作站硬件條件有限的情況下，其優(yōu)越性比較明顯。如果這個Ades是一個第三方提供的IP硬核(hard-c

27、ore)，那么也只能使用這種方法 在編譯頂層模塊時，由于Ades設(shè)置了dont_touch，這就妨礙了DC針對Ades的各個實例周圍環(huán)境的不同的進一步優(yōu)化，從而使得結(jié)果不能真實反映各個實例周圍的環(huán)境變化 Uniquify 由于把各個多例化模塊作為獨立的模塊來看，因此DC可以分別針對它們作出更好的優(yōu)化，從而得到的結(jié)果比較理想 編譯的時間稍微較長，但是對于一些不大的模塊來說，這些是可以忽略的。 一般推薦使用uniquify解決多例化模塊的綜合問題。,Compiling a Hierarchical Design (1),對一個大型設(shè)計來講，有兩種層次化編譯技術(shù) 自上而下(Top-down) 將整個

28、設(shè)計一次性讀入，施加頂層約束后直接進行編譯 無需考慮各個模塊/子模塊之間的依賴關(guān)系，也就不需要制模塊/子模塊之間的時序預算和負載預算，都由DC自動考慮 編寫腳本變得簡單，維護起來也比較方便 自下而上(Bottom-up) 先單獨編譯各個模塊/子模塊：在編譯要考慮與其它模塊之間的關(guān)系，給它們加入時序預算和負載預算，看是否滿足約束 再讀入頂層文件，施加頂層約束，將各個模塊/子模塊整合起來：頂層編譯完成后還必須看頂層約束是否滿足,Compiling a Hierarchical Design (2),Pros & Cons of Bottom-Up Compile 優(yōu)點 利用”分而治之”的策略，對于

29、大型的不可能一次編譯的設(shè)計十分有用 擺脫了Top-down方法的對工作站硬件條件的限制，使得大型設(shè)計也能在一般的機器上編譯完成 缺點 實現(xiàn)步驟比較多，尤其對各個模塊之間的時序和負載預算要求很高 Summary,Timing Analysis and Report (1),What Tool to Use? Design Compiler has a built-in static timing analyzer called DesignTime,Timing Analysis and Report (2),DesignTime Timing Reports,Logic Design & Si

30、mulation : from RTL, then in Gate-Level,Logic Synthesis 得到用已有的基本邏輯單元（庫單元）互聯(lián)并滿足一定邏輯功能的邏輯構(gòu)成 Gate-Level Simulation（門級功能仿真與動態(tài)時序分析） 一般不做這一步 Formal Verification（形式驗證） STA（Static Timing Analysis，靜態(tài)時序分析）,STA Based on Synopsys PrimeTime,What is Static Timing Analysis?,Static Timing Analysis（STA）determines if a circuit meets timing constraints without dynamic simulation Three main steps: Design is broken down into sets of timing paths The delay of each path is calculated All path delays are checked to see if timing constraints have been met,STA Step 1: Timing Paths,Step1實際是將邏輯電路網(wǎng)表轉(zhuǎn)換成拓撲圖，圖