外文翻譯---微機(jī)系統(tǒng)

中文 2330 字 THE MICROPROCESSOR SYSTEM A microprocessor system can be described at a number of different levels of complexity. The least complex from is that of a simple block diagram describing the interconnection and flow of information functional blocks and will be used to examine the operation of a microprocessor system. All microprocessor systems contain a central processing unit(CPU),program and data memory and input(I/O) devices.Fig.4-4 show a block diagram of a typical embedded microprocessor system in which each block corresponds roughly to the individual integrated circuit(chip) used in the system. The memory section contains both non-volatile read only memory(ROM) as program memory and volatile random access memory(RAM) as read/write data memory .For each type of memory there are a number of different types of devices ,such as erasable ROMs and static or dynamic RAMs, each of which is chosen for an application based on its cost and function. Four different I/O functions are shown in Fig.4-4.An analogue input channel to the microprocessor system is provided by the analogue to digital(A/D) converter and may be used to connect a device such as an analogue to digital(A/D) converter and may be used to connect a device such as an analogue sensor. An analogue output channel is provided by the digital to analogue(D/A) converter and could be used to control an output transducer such as an electric motor, The parallel I/O device provides a number of individual lines. In output mode these can be programmed to provide logic levels 1 or 0 to activate binary(on/off)devices such as lamps. In input mode it allows the microprocessor to read the state of switches and other binary devices. The serial I/O device is used to provide communications with other microprocessor systems or with an operator console used to configure the system for various operational modes. The level and power specifications of the interfacing signals of the microprocessor system are frequently incompatible with the signal specifications of the devices which are to be interfaced to it .For example, the output voltage of a D/A converter may typically be in the range 0-5 volts and be capable of supplying only a few milliamperes of current, Fig.4-4 Block diagram of a typical embedded microprocessor system while the electric motor may require a control voltage range of plus and minus 12 volts at a maximum current of 1 ampere. Consequently, additional analogue interface circuitry is often necessary to perform functions such as signal level shifting, amplification and filtering. Fig.4-4 also shows there peripheral circuits: an input control unit(ICU),a programmable counter/timer, and a direct memory access unit(DMA).All this devices are interfaced to the CPU by means of a system bus which is itself made up from an address bus and a control bus. Physically, a bus is simple a collection of parallel interconnections between to or more devices. The number of lines contained in each bus is dependent on the type of microprocessor used in the system and the function of the bus. In Fig.4-4 we assume that the address bus has sixteen lines, the data bus has eight lines ,and the control bus contains an arbitrary number of lines depending on the control functions provided by the CPU. The concepts of address and data are fundamental to the operation of a stored program computer and form a feature of all microprocessors and computers. The memory will consist of a number of memory locations capable of storing data written to them by the CPU over the data bus .Each memory location is uniquely identified to the CPU by a number called its address. The CPU controls the address and control bus lines in order to write or read information to or form the memory or I/O devices. For example, if the CPU wished to write the binary number 01010101 into a memory location which had the address 0000000000001111,the CPU would first place the address on to the address bus, then place the number 01010101 as data onto the data bus. Controls lines in the control bus would then be activated to cause the data to be loaded into the appropriate memory location. A similar procedure would be used if the CPU was then to read a memory address, except this the flow of data would be from the memory to the CPU. After the CPU had placed the address of the required memory location on to the address bus .it would indicate to the memory that it wished to read the value by activating the relevant line in the control bus .The memory would respond by placing the contents of the memory location ad data on to the data bus ,and this would then be read by the CPU. Within the system bus, the address bus is an output bus from the CPU and an input bus to the other devices. The control bus consists of a number of lines, each of which may be either a control output from the CPU or a control input to the CPU. The data bus however acts as both an input bus and an output bus depending on whether the CPU is reading or writing data.Fig.4-4 shows that all devices in the system are connected together by the data bus and this means that, potentially at least, the outputs of all the memory and I/O devices are connected. If this were in fact to happen it would cause the destruction of several or all of the connected devices, because some devices would be trying to drive the bus to a logic 1 state while others were trying to drive it to a logic 0 state2.To avoid this problem, the data bus connections of each device are capable of being placed into a third, high impedance state where the device no longer has any loading effect on the bus. This allows other devices connected to the data bus to output their data on to this bus when they are correctly enabled, which in turn means that only one device should be enabled at any one time to the data bus3.The ability of a device to be either at a logic I or at a logic 0 or in a high impedance condition in relation to the data bus is called a tristate condition, and is an essential feature of devices which share a common data bus . In the example of Fig.4-4 the data bus has eight lines, and hence the range of values which a single item of data can take is restricted to that which can be represented by 8 binary digits or bits. Eight bits are referred to as a byte, and can represent a decimal number from 0 to 255;Likewise the address bus ,consisting of sixteen lines, can represent an address number in the range 0 to 65535.This number is usually abbreviated to the binary equivalent of the decimal number and expressed as 64K,where K is equal to 1024 in the binary number system. To the CPU, the system appears as a series of 64K consecutive memory locations, each capable of storing an 8 bit binary value. The CPU will contain a number of registers which are used to manipulate the data and its addresses. In the example chosen, these data registers will be 8 bit registers and all data manipulations will be performed on 8 bit quantities. The CPU is therefore referred to as an 8 bit CPU, However, registers which support address manipulations need to be 16 bit registers because of the 16 bit address bus. The size of the address bus is independent of the size of the data bus ,so that 16 bit or 32 bit CPUs may typically have a 16 bit,24 bit or 32 bit address bus. It is normal when working with microprocessors to represent binary numbers as hexadecimal (base 16) values, because a single hexadecimal hex)digit corresponds to a group of four consecutive binary The hexadecimal number is easier to read and write than its binary equivalent, and it requires only simple mental calculation in order to translate from hexadecimal to binary and back again. Hexadecimal numbers and digits are identified in the text by prefixing them with Ox, which is the convention adopted in the C programming language. For example, the 16 bit binary number 1111110100111001 would be written in hexadecimal form as 0xFD39. It is not necessary for the hardware designer to make use of the entire address range of the CPU, and the physical memory required can be implemented anywhere within the address space of the CPU. In addition, the I/O devices will contain registers through which the IO devices may be configured, and which provide addresses through which the CPU can read and write data into and out of the system. These registers appear to the CPU. as normal memory location. And so occupy parts of the address space. The arrangement of the memory and I/O addresses within the address space is described by the memory map of the system, an example of which is given in Fig.4-5a. The memory map will be designed to meet the requirements of the application, and will be used by the hardware designer to partition the address space so that the address range of the memory devices in the system corresponds to the address range specified by the memory map. This is achieved by means of the address decoder. Shown in Fig.19-1,this uses lines from the address bus as its input and produces individual chip select signals for each chip which contributes to the memory map of the system.Fig.4-5a shows that the particular system under consideration should have RAM from memory location 0x1000to memory location 0x1FFF.This address range represents 4K bytes (4096) of memory, requiring the lower twelve address lines of the address bus ,All-A0,to be connected to a 4K RAM device. The remaining four upper address lines,A15-A12,are taken to the address decoder which outputs a chip select signal to the RAM whenever the lines A15-A12 have the value 0001.The address decoder therefore implements the Boolean equation RAM enable =A.15 A.14 A13.A12=A15+A14+A13+A12 (4-4) as in Fig.4-5b. From.Direction Editor Zhangyue. China machine press.1.2003 參考譯文 ： 微機(jī)系統(tǒng) 微機(jī)系統(tǒng)可在許多復(fù)雜的層面上進(jìn)行描述。最簡(jiǎn)單的形式是用簡(jiǎn)單的方塊圖來(lái)描述內(nèi)部的連接以及各功能塊間的信息流，并用來(lái)分析微機(jī)系統(tǒng)的工作情況。 所有微機(jī)系統(tǒng)包含一個(gè)中央處理單元（ CPU）、程序和數(shù)據(jù)存儲(chǔ)器以及輸入、輸出（ I/O）設(shè)備。圖 4-4 表示了一個(gè)典型的嵌入式微機(jī)系統(tǒng)的方框圖，該圖中每個(gè)方塊大致上對(duì)應(yīng)于該系統(tǒng)中所用的單個(gè)集成電路（芯片）。 存儲(chǔ)器部分包含了用作程序存儲(chǔ)器的掉電不易失信息的只讀存儲(chǔ)器（ ROM）和用作讀 /寫的掉電易失的隨機(jī)訪問(wèn)數(shù)據(jù)存儲(chǔ)器（ RAM），每種存儲(chǔ)器都有許多不同類型的元件，如可擦寫的 ROM 以及靜態(tài)或動(dòng)態(tài) RAM，應(yīng)用時(shí)，根據(jù)價(jià)格、功能來(lái)選擇。 圖 4-4 表示四種不同的 I/O 功能，微機(jī)系統(tǒng)的模擬信道由模數(shù)（ A/D）轉(zhuǎn)換提供，可以連 接如模擬輸入傳感器這樣的器件。模擬輸入信道由數(shù)模（ D/A）轉(zhuǎn)換器提供，可以用于控制像電動(dòng)機(jī)這樣的動(dòng)力輸出轉(zhuǎn)換器。并行 I/O 元件提供許多獨(dú)立的輸入 /輸出端口線，在輸出方式下，這些端口可以通過(guò)編程提供邏輯電平 1或 0來(lái)驅(qū)動(dòng)二進(jìn)制（開 /關(guān)）設(shè)備如燈泡。在 輸入方式下，微處理器可允許讀入開關(guān)及其他的二進(jìn)制設(shè)備的狀態(tài)。串行 I/O設(shè)備用于與其他的微機(jī)系統(tǒng)或不同操作模式的操作控制臺(tái)之間進(jìn)行通信。 微機(jī)系統(tǒng)接口信號(hào)的電平和功率大小，常常與連接的元器件不匹配，例如，一個(gè) D/A轉(zhuǎn)換器典型的輸出電壓是 0 5V ，并僅能提供毫安培級(jí) 電流，而電動(dòng)機(jī)可能要求的控制電壓范圍為 -12V +12V，最大電流 1A。為此需相應(yīng)的增加模擬接口電路實(shí)現(xiàn)信號(hào)電平轉(zhuǎn)換、放大和濾波。圖 4-4中還表示了三個(gè)外圍電路：中斷控制單元（ ICU）、可編程計(jì)數(shù) /定時(shí)器以及直接存儲(chǔ)器訪問(wèn)單元（ DMA）。 所有這些元件都通過(guò)系統(tǒng)總線和 CPU 接口。系統(tǒng)總線由地址總線、數(shù)據(jù)總線和控制總線構(gòu)成。實(shí)際上，總線只是兩個(gè)元件間并行連接線的集合。每個(gè)總線包含的引線由系統(tǒng)使用的微處理器的型號(hào)以及總線的功能來(lái)確定，如圖 4-4所示，我們假設(shè)地址總線為 16根，數(shù)據(jù)總線為 8 根，控制總線數(shù)目不確定 ，這要由 CPU提供的功能而定。 地址和數(shù)據(jù)是運(yùn)行計(jì)算機(jī)所儲(chǔ)存的程序、形成所有微處理器和計(jì)算機(jī)特征的基礎(chǔ)。存儲(chǔ)器由許多能由 CPU通過(guò)數(shù)據(jù)總線寫入數(shù)據(jù)的存儲(chǔ)單元構(gòu)成。每個(gè)存儲(chǔ)單元具體位置由 CPU 用地址來(lái)唯一標(biāo)識(shí)。為了從存儲(chǔ)器或 I/O口設(shè)備中寫或讀信息， CPU控制著地址和控制總線，如 CPU希望將二進(jìn)制信息 01010101 寫入地址為0000000000001111 的存儲(chǔ)單元， CPU 首先將該地址送到地址總線上，然后將01010101作為數(shù)據(jù)送到數(shù)據(jù)總線上，控制總線中的控制線激活，啟動(dòng)數(shù)字寫入適當(dāng)?shù)拇鎯?chǔ)單元。相類似的情 況用于 CPU只讀存儲(chǔ)單元的地址的過(guò)程，這時(shí)數(shù)據(jù)流不是從存儲(chǔ)器到 CPU，那么在 CPU 將要求的存儲(chǔ)單元的地址送到地址總線上后，CPU通過(guò)啟動(dòng)控制總線相關(guān)的控制線，指示存儲(chǔ)器要讀數(shù)據(jù)，存儲(chǔ)器則做出反應(yīng)，將該存儲(chǔ)單元的內(nèi)容當(dāng)作數(shù)據(jù)，送上數(shù)據(jù)總線，然后 CPU讀取到該數(shù)據(jù)。 在系統(tǒng)總線中，地址總線對(duì) CPU來(lái)說(shuō)是輸出總線，但對(duì)其他設(shè)備是輸入總線，控制總線包含許多線，它們或者是 CPU輸出控制線，或者是輸入控制線。數(shù)據(jù)總線既當(dāng)作輸入總線，又作輸出總線，這要看 CPU 是讀還是寫數(shù)據(jù)，圖 4-4，表示了系統(tǒng)中所有元件都通過(guò)數(shù)據(jù)總線連 在一起，這意味著，最低限度上存儲(chǔ)器和 I/O設(shè)備的 輸出是連在一起的。如果實(shí)際情況是這樣，則將引起所有連接的元件中幾個(gè)或全部元件被破壞，因?yàn)橐恍┰骷⒃噲D驅(qū)動(dòng)總線到邏輯 1 狀態(tài)，而其他一些則試圖驅(qū)動(dòng)其為 0狀態(tài)。為了避免這個(gè)問(wèn)題，連接到每個(gè)元件的數(shù)據(jù)總線有