用Verilog--HDL語言編寫的電子秒表PPT演示課件

1、電子秒表,Verilog HDL語言,1,本設(shè)計是用Verilog HDL語言編寫的電子秒表，精度為0.01秒，用兩個按鍵來操作秒表（開始/暫停按鍵和重置按鍵），并用四段數(shù)碼管顯示。 程序中的數(shù)碼管驅(qū)動模塊是根據(jù)BASYS 2開發(fā)板數(shù)碼管電路編寫的,2,代碼如下: /總模塊 module miao_biao(rest,clk,a_to_g,A_TO_D,kon,clk001 ); input wire rest; /復(fù)位 input wire clk; /50M時鐘 output wire clk001; /輸出0.01S的脈沖 wire 3:0q0; /每一位上的數(shù)據(jù),公四位 wire 3:

2、0q1; wire 3:0q2; wire 3:0q3; wire Q0; /每一位計到0后，Q變?yōu)?，作為下一片的脈沖信號 wire Q1; wire Q2; output wire 6:0a_to_g; output wire 3:0A_TO_D; input wire kon; Wire clk001out; /以上是各個網(wǎng)絡(luò)的定義，clk001可以不用當(dāng)做輸出,3,以下是各個模塊的連接，以及各個模塊的調(diào)用 assign Q0=(q00|q01|q02|q03); assign Q1=(q10|q11|q12|q13); assign Q2=(q20|q21|q22|q23); jian

3、_kong jian_kong0(rest,kon,clk001,clk001out); cp_001s cp_001s0(rest,clk,clk001); count4 count4_0(clk001out,rest,q0); count4 count4_1(Q0,rest,q1); count4 count4_2(Q1,rest,q2); count4 count4_3(Q2,rest,q3); shumaguan shumaguan0(a_to_g,A_TO_D,clk,q3,q2,q1,q0); Endmodule /到此總模塊結(jié)束,4,module count4(a,clr,q);

4、 /計數(shù)器，從9計到0 input wire a; input wire clr; output reg 3:0q; always(posedge a or posedge clr) begin if(clr=1) q=0; else if(q=9) q=0; else q=q+1; end endmodule /該模塊的十進制計數(shù)器，每一位的數(shù)據(jù)由一個該計數(shù)器提供,5,Module shumaguan(a_to_g,A_TO_D,clk,qian,bai,shi,ge);/數(shù)碼管驅(qū)動 output reg 6:0a_to_g; output reg 3:0A_TO_D; input wire

5、 clk; input wire 3:0qian; input wire 3:0bai; input wire 3:0shi; input wire 3:0ge; reg 3:0duan; reg 1:0wei; reg a; reg 16:0q; always(posedge clk) begin if(q=49999) begin q=0; a=a; end else q=q+1; end,6,always(*)/7位段譯碼 case(duan) 0:a_to_g=7b0000001; 1:a_to_g=7b1001111; 2:a_to_g=7b0010010; 3:a_to_g=7b0

6、000110; 4:a_to_g=7b1001100; 5:a_to_g=7b0100100; 6:a_to_g=7b0100000; 7:a_to_g=7b0001111; 8:a_to_g=7b0000000; 9:a_to_g=7b0000100; default:a_to_g=7b0000001; endcase,7,always(*)/4位位選譯碼 case(wei) 3:begin A_TO_D=4b1110; duan=qian; end 2:begin A_TO_D=4b1101; duan=bai; end 1:begin A_TO_D=4b1011; duan=shi; e

7、nd 0:begin A_TO_D=4b0111; duan=ge; end default:A_TO_D=4b1110; endcase always(posedge a)/四個狀態(tài)循環(huán) if(wei=3) wei=0; else wei=wei+1; endmodule /到此數(shù)碼管驅(qū)動模塊結(jié)束,8,module cp_001s(rest,clk,a /產(chǎn)生0.01秒的脈沖，用來驅(qū)動計時 ); input rest; input clk; output reg a; reg 20:0q; always(posedge clk or posedge rest) begin if(rest=1

8、) begin q=0; a=0; end else if(q=249999) begin q=0; a=a; end else q=q+1; end endmodule,9,module jian_kong(rest,kon,clk001,clk001out);/開始與暫停按鍵的控制電路 input rest; input kon; input clk001; output clk001out; wire k; wire d; assign d=k; assign clk001out=k end endmodule /到此程序全部結(jié)實,10,在BASYS 2開發(fā)板上的管腳配置，最后一句不能缺

9、少 /按鍵G12為重置按鍵，按鍵C11為開始/暫停按鍵 # PlanAhead Generated physical constraints NET A_TO_D3 LOC = F12; NET A_TO_D2 LOC = J12; NET A_TO_D1 LOC = M13; NET A_TO_D0 LOC = K14; NET a_to_g6 LOC = L14; NET a_to_g5 LOC = H12; NET a_to_g4 LOC = N14; NET a_to_g3 LOC = N11; NET a_to_g2 LOC = P12; NET a_to_g1 LOC = L13;