電子時(shí)鐘設(shè)計(jì)(6)

1、電子時(shí)鐘設(shè)計(jì)基本功能要求：設(shè)計(jì)一個(gè)電子時(shí)鐘，要求可以顯示時(shí)、分、秒，用戶可以通過按鍵來設(shè)置時(shí)間。擴(kuò)展功能要求：秒表功能，鬧鐘功能，調(diào)整數(shù)碼管的亮度。試驗(yàn)箱設(shè)置：1、 選擇模式7（見附圖1）;2、 數(shù)碼管8左邊的跳線選擇close(數(shù)碼管連接關(guān)系看課本406頁圖f-8);整體原理圖：管腳分配圖：本設(shè)計(jì)的原理圖：報(bào)告具體內(nèi)容：1 設(shè)計(jì)目的設(shè)計(jì)一個(gè)電子時(shí)鐘，可以顯示時(shí)、分、秒，用戶可以設(shè)置時(shí)間。擴(kuò)展功能為秒表功能，鬧鐘功能，調(diào)整數(shù)碼管的亮度。2 設(shè)計(jì)內(nèi)容1. 整體功能分模塊設(shè)置調(diào)表，跑表，鬧鐘，speaker，秒表，走表模塊設(shè)置，最后用一個(gè)三選一選擇器對各模塊進(jìn)行選擇，最后輸入到掃描模塊中進(jìn)行輸出。

2、調(diào)表模塊：1.通過鍵1鍵4對分秒時(shí)進(jìn)行位選擇和位加，將調(diào)表的輸出分別接到跑表和模式選擇中，接到跑表中是設(shè)置完時(shí)間后可以繼續(xù)計(jì)時(shí)輸出，接到模式選擇中，可以通過模式2輸出調(diào)表設(shè)置的時(shí)間。鬧鐘設(shè)置：同設(shè)置模塊，鍵1鍵4是對位選跟位加，而鬧鐘一定要接到speaker中，與輸入到speaker中的跑表對比，當(dāng)走表走到設(shè)置的時(shí)間時(shí)，speaker會發(fā)出響聲。speaker：將speaker的輸出接到板子上的speaker中，當(dāng)一定要接一個(gè)clk輸出，speaker才能發(fā)出震動輸出響聲。跑表模塊：用鍵1 來給跑表覆初值，通過輸入1hz的時(shí)鐘來加數(shù)，正常走表的輸出要接在模式選擇上，通過模式1來進(jìn)行選擇輸出走表

3、功能。秒表功能：語言跟走表相似，但開始是，要先對秒表用信號覆初值為0，通過鍵1來清零，秒表的輸出要接在模式選擇上，通過模式3對秒表進(jìn)行輸出。模式選擇：模式選擇的實(shí)現(xiàn)是通過一個(gè)三選一選擇器對各功能進(jìn)行選擇，將輸出接到位掃描器上，通過位選和段選來輸出。掃描輸出：通過對左側(cè)的段選輸入對數(shù)碼管的各段進(jìn)行顯示，通過對右側(cè)各位進(jìn)行選通來達(dá)到位選擇輸出的目的，用10000hz的頻率來刷頻就不會看到輸出時(shí)輸出的轉(zhuǎn)換，亮度調(diào)節(jié)是對通過改變選通位選信號的不同占空比來達(dá)到調(diào)節(jié)亮度的目的，鍵5 是用作不同的占空比輸出，在調(diào)節(jié)占空比時(shí)是對輸入信號低位和高位進(jìn)行占空比調(diào)節(jié)，具體見程序代碼中。三 電子鐘的整體vhdl 語言

4、描述分頻器的vhdl語言library ieee;use ieee.std_logic_1164.all; -分頻use ieee.std_logic_unsigned.all;entity fenpin isport( clk:in std_logic; clkend_100:out std_logic; clkend_10000:out std_logic; clkend_1:out std_logic); end;architecture behv of fenpin issignal clk1_tmp:std_logic;signal clk100_tmp:std_logic;sign

5、al clk10000_tmp:std_logic;signal cnt5000000:integer range 0 to 5000000;signal cnt50000:integer range 0 to 50000;signal cnt5000:integer range 0 to 500;beginhz1: process(clk) begin -輸出1hz頻率，作為跑表時(shí)鐘 if clkevent and clk=1 then if cnt50000004999999 then cnt5000000=cnt5000000+1; else cnt5000000=0; clk1_tmp

6、=not clk1_tmp ; end if; end if;end process;hz100: process(clk) begin if clkevent and clk=1 then -輸出100hz頻率，作為秒表時(shí)鐘輸入 if cnt5000049999 then cnt50000=cnt50000+1; else cnt50000=0; clk100_tmp=not clk100_tmp ; end if; end if;end process;hz1000: process(clk) -輸出1000hz頻率，作為掃描輸出時(shí)鐘 begin if clkevent and clk=1

7、 then if cnt5000499 then cnt5000=cnt5000+1; else cnt5000=0; clk10000_tmp=not clk10000_tmp ; end if; end if;end process; clkend_1=clk1_tmp; clkend_100=clk100_tmp; clkend_10000speakerlibrary ieee; -鬧鐘對時(shí)輸出響聲use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity speaker isport ( clk_100: in

8、std_logic; shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9;-跑表輸入與鬧鐘設(shè)置時(shí)間輸入來對比輸出響聲 shishi,shige,fenshi,fenge,miaoshi,miaoge:in integer range 0 to 9; speaker_1 : out std_logic); end entity;architecture bhv of speaker isbeginprocess(clk_100,shishi,shige,fenshi,fenge,miaoshi,miaoge

9、,shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2) begin if shishi2=shishi and shige2=shige and fenshi2=fenshi and fenge2=fenge and miaoshi2=miaoshi and miaoge2=miaoge then -校對時(shí)間，時(shí)間相同時(shí)輸出響聲 speaker_1= clk_100; else speaker_1 5 then set= 0; else set if miaoge1 =9 then miaoge1=0; else miaoge1 if miaoshi1

10、 =5 then miaoshi1=0; else miaoshi1 if fenge1 =9 then fenge1=0; else fenge1 if fenshi1 =5 then fenshi1=0; else fenshi1 if shige1 =9 then shige1=0; else shige1 if shishi1 =2 then shishi1=0; else shishi1 null ; end case;end if; end process; miaoge=miaoge1; miaoshi=miaoshi1; fenge=fenge1; fenshi=fenshi1

11、; shige=shige1; shishi 5 then set= 0; else set if miaoge1 =9 then miaoge1=0; else miaoge1 if miaoshi1 =5 then miaoshi1=0; else miaoshi1 if fenge1 =9 then fenge1=0; else fenge1 if fenshi1 =5 then fenshi1=0; else fenshi1 if shige1 =9 then shige1=0; else shige1 if shishi1 =2 then shishi1=0; else shishi

12、1 null ; end case;end if; end process; miaoge=miaoge1; miaoshi=miaoshi1; fenge=fenge1; fenshi=fenshi1; shige=shige1; shishi=shishi1;end bhv;走表的vhdl語言library ieee; -跑表use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity paobiao isport(clk:in std_logic; jian1:in std_logic; shishi1,shige1

13、,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9; -跑表初始輸入 shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:out integer range 0 to 9); -跑表輸出end entity;architecture bhv of paobiao issignal shi,fen,miao:integer range 0 to 100;beginprocess(clk,jian1,shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1)

14、begin if jian1=1 thenshi=shishi1*10+shige1; -將表的初始時(shí)間賦到信號中fen=fenshi1*10+fenge1;miao=miaoshi1*10+miaoge1;elsif clkevent and clk=1 then if miao=59 then miao=0; -對通過加法器來對分時(shí)秒依次相加 fen59 then fen=0; shi23 then shi=0; else miao=miao+1; end if; else null; end if;end process;miaoge2=miao rem 10; -用rem和除號對個(gè)位和

15、十位進(jìn)行取余和取模miaoshi2=miao/10;fenge2=fen rem 10;fenshi2=fen/10;shige2=shi rem 10;shishi2=shi/10;end; 秒表的vhdl語言library ieee; -秒表use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity miaobiao is -鍵1作為復(fù)位端輸入port(clk_100:in std_logic; -秒表要用100hz頻率 jian1:in std_logic; haomiaoshi2,haomiaoge2,fensh

16、i2,fenge2,miaoshi2, miaoge2:out integer range 0 to 9);end entity;architecture bhv of miaobiao issignal haomiaoshi1,haomiaoge1,fenshi1,fenge1， miaoshi1,miaoge1 :integer range 0 to 9 ;signal haomiao,fen,miao:integer range 0 to 100;beginhaomiaoshi1=0;haomiaoge1 =0; -給秒表賦初值為0fenshi1=0;fenshi1=0;miaoshi1

17、=0;miaoge1=0; process(clk_100,jian1,haomiaoshi1,haomiaoge1,fenshi1,fenge1,miaoshi1,miaoge1) beginif clk_100event and clk_100=1 then if jian1=1 then -同跑表功能 haomiao=haomiaoshi1*10+haomiaoge1; fen=fenshi1*10+fenge1; miao=miaoshi1*10+miaoge1; elsif haomiao=99 then haomiao=0; miao59 then miao=0; fen59 th

18、en fen=0; else haomiao= haomiao+1; end if; end if; end process;haomiaoge2=haomiao rem 10;haomiaoshi2=haomiao/10;miaoge2=miao rem 10;miaoshi2=miao/10;fenge2=fen rem 10;fenshi23 then moshi_1 = 0; else moshi_1 a0=pshishi1;a1=pshige1;a3=pfenshi1;a4=pfenge1; a6=pmiaoshi1;a7 a0=sshishi2;a1=sshige2;a3=sfen

19、shi2;a4=sfenge2; a6=smiaoshi2;a7 a0=fenshi;a1=fenge;a3=miaoshi;a4=miaoge; a6=haomiaoshi;a7null; end case; end process; end bhv; 掃描輸出加亮度顯示vhdl語言library ieee; -掃描顯示use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity saomiao is port( clk_1000:in std_logic; jian5:in std_logic; a0,a1,a3,a4

20、,a6,a7:in integer range 0 to 9; dx:out std_logic_vector(6 downto 0); -位控制位輸出 wx:out std_logic_vector(7 downto 0); -段控制位輸出end entity;architecture bhv of saomiao is signal cnt32 :std_logic_vector(4 downto 0); signal a :integer range 0 to 15; signal cnt3:integer range 0 to 3; signal cnt4:integer range

21、0 to 3; signal count: std_logic;beginb1: process(cnt32,a0,a1,a3,a4,a6,a7) begin case cnt32(4 downto 2) is - 段選輸出，count為不同占空比輸入 when 000 = wx= 0000000&(count);a wx= 000000&(count)&0;a wx= 00000&(count)&00;a wx= 0000&(count)&000;a wx= 000&(count)&0000;a wx= 00&(count)&00000;a wx= 0&(count)&000000;a wx

22、= (count)&0000000;a null; end case; end process ;b2:process(clk_10000) -加法器來控制段選輸出 begin if clk_10000event and clk_10000 =1 then cnt32 dx dx dx dx dx dx dx dx dx dx dx dx dx dx dx dx null; end case; end process ;b4:process (jian5) - 鍵5 作為信號端對不同亮度進(jìn)行選擇輸出 begin if jian5event and jian5=1 then if cnt3 3

23、then cnt3= 0; else cnt3=cnt3+1;end if; end if;end process; b5:process (clk_10000) begin if clk_10000event and clk_10000=1 then if cnt4 =3 then cnt4= 0; else cnt4 if cnt4=0 then count= 1; -占空比1：0=1：3 else count if cnt42 then -占空比1：0=2：2 count=1; else count if cnt43 then -占空比1：0=3：1待添加的隱藏文字內(nèi)容3 count=1; else count if cnt44 then -占空比1：0=4：0 count=1; else count jian1,jian4=jian4, shishi=shishinsp,shige=shigensp, fenshi=fenshinsp, -鬧鐘例化，鬧鐘輸出接