51系列單片機(jī)外文翻譯電子畢業(yè)設(shè)計(jì)

1、一篇關(guān)于單片機(jī)的英文文獻(xiàn)(上) validation and testing of design hardening for single event effects using the 8051 microcontrollerabstract with the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. in this paper

2、, we will discuss the implications of validating these methods for the single event effects (see) in the space environment. topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). finally, an 8051 microcontr

3、oller core from nasa institute of advanced microelectronics (iae) cmos ultra low power radiation tolerant (culprit) design is evaluated for see mitigative techniques against two commercial 8051 devices. index terms single event effects, hardened-by-design, microcontroller, radiation effects.i. intro

4、ductionnasa constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources 1,2. with a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind comm

5、ercial state-ofthe-art technologies, nasas performance of this task is quite challenging. one method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. this is often called hardened-by-design (hbd).building custom-type

6、hbd devices using design libraries and automated design tools may provide nasa the solution it needs to meet stringent science performance specifications in a timely, cost-effective, and reliable manner. however, one question still exists: traditional radiation-hardened devices have lot and/or wafer

7、 radiation qualification tests performed; what types of tests are required for hbd validation?ii. testing hbd devices considerationstest methodologies in the united states exist to qualify individual devices through standards and organizations such as astm, jedec, and mil-std- 883. typically, tid (c

8、o-60) and see (heavy ion and/or proton) are required for device validation. so what is unique to hbd devices?as opposed to a “regular” commercial-off-the-shelf (cots) device or application specific integrated circuit (asic) where no hardening has been performed, one needs to determine how validated

9、is the design library as opposed to determining the device hardness. that is, by using test chips, can we “qualify” a future device using the same library?consider if vendor a has designed a new hbd library portable to foundries b and c. a test chip is designed, tested, and deemed acceptable. nine m

10、onths later a nasa flight project enters the mix by designing a new device using vendor as library. does this device require complete radiation qualification testing? to answer this, other questions must be asked.how complete was the test chip? was there sufficient statistical coverage of all librar

11、y elements to validate each cell? if the new nasa design uses a partially or insufficiently characterized portion of the design library, full testing might be required. of course, if part of the hbd was relying on inherent radiation hardness of a process, some of the tests (like sel in the earlier e

12、xample) may be waived. other considerations include speed of operation and operating voltage. for example, if the test chip was tested statically for see at a power supply voltage of 3.3v, is the data applicable to a 100 mhz operating frequency at 2.5v? dynamic considerations (i.e., nonstatic operat

13、ion) include the propagated effects of single event transients (sets). these can be a greater concern at higher frequencies.the point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the

14、characteristics of the foundry must be known. if all these are applicable or have been validated by the test chip, then no testing may be necessary. a task within nasas electronic parts and packaging (nepp) program was performed to explore these types of considerations.iii. hbd technology evaluation

15、 using the 8051 microcontrollerwith their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in nasa and dod system designs. there are existing nasa and dod programs that are doing technology development to provide hbd. microcontrollers are one such veh

16、icle that is being investigated to quantify the radiation hardness improvement. examples of these programs are the 8051 microcontroller being developed by mission research corporation (mrc) and the iae (the focus of this study). as these hbd technologies become available, validation of the technolog

17、y, in the natural space radiation environment, for nasas use in spaceflight systems is required.the 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. there are numerous commercial vendors that supply this c

18、ontroller or have it integrated into some type of system-on-a-chip structure. both mrc and iae chose this device to demonstrate two distinctly different technologies for hardening. the mrc example of this is to use temporal latches that require specific timing to ensure that single event effects are

19、 minimized. the iae technology uses ultra low power, and layout and architecture hbd design rules to achieve their results. these are fundamentally different than the approach by aeroflex-united technologies microelectronics center (utmc), the commercial vendor of a radiation hardened 8051, that bui

20、lt their 8051 microcontroller using radiation hardened processes. this broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation.the objective of this work is the technology evaluation of the culprit process 3 from iae. the process

21、 has been baselined against two other processes, the standard 8051 commercial device from intel and a version using state-of-the-art processing from dallas semiconductor. by performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.in the perform

22、ance of the technology evaluation, this task developed hardware and software for testing microcontrollers. a thorough process was done to optimize the test process to obtain as complete an evaluation as possible. this included taking advantage of the available hardware and writing software that exer

23、cised the microcontroller such that all substructures of the processor were evaluated. this process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future.iv. test devicesthree devi

24、ces were used in this test evaluation. the first is the nasa culprit device, which is the primary device to be evaluated. the other two devices are two versions of a commercial 8051, manufactured by intel and dallas semiconductor, respectively.the intel devices are the romless, cmos version of the c

25、lassic 8052 mcs-51 microcontroller. they are rated for operation at +5v, over a temperature range of 0 to 70 c and at a clock speeds of 3.5 mhz to 24 mhz. they are manufactured in intels p629.0 chmos iii-e process.the dallas semiconductor devices are similar in that they are romless 8052 microcontro

26、llers, but they are enhanced in various ways. they are rated for operation from 4.25 to 5.5 volts over 0 to 70 c at clock speeds up to 25 mhz. they have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. in addition, the core is redesigned so that the machine cycle i