基于MIPS指令單周期微控制器設(shè)計(jì) 哈工大

1、課程設(shè)計(jì)說明書（論文）課程名稱： 數(shù)字集成系統(tǒng)課程設(shè)計(jì) 設(shè)計(jì)題目： 基于MIPS指令的單周期微控制器設(shè)計(jì) 院 系： 航天學(xué)院 微電子科學(xué)與技術(shù)系 班 級(jí)： 設(shè) 計(jì) 者： 學(xué) 號(hào)： 指導(dǎo)教師： 設(shè)計(jì)時(shí)間： 2015年7月27日-2015年8月7日 姓 名： 院 （系）： 專 業(yè)： 班 號(hào)： 任務(wù)起至日期： 2015 年 7 月 27 日 至 2015 年 8 月 7 日 課程設(shè)計(jì)題目：基于MIPS指令的單周期微控制器設(shè)計(jì)已知技術(shù)參數(shù)和設(shè)計(jì)要求：Load/store，算術(shù)邏輯運(yùn)算和流程控制是RISC的主要組成部分，本設(shè)計(jì)以MIPS指令子集為例，研究RISC的基本原理與硬件建模。（1） load/s

2、tore設(shè)計(jì)設(shè)計(jì)要求：參考計(jì)算機(jī)組成與設(shè)計(jì)硬件/軟件接口，進(jìn)行模塊劃分和設(shè)計(jì)微控制器整體結(jié)構(gòu)，設(shè)計(jì)支持load、store指令的數(shù)據(jù)通路，并比較各種實(shí)現(xiàn)的效率、面積和速度。（2） 算術(shù)邏輯運(yùn)算設(shè)計(jì)設(shè)計(jì)要求：設(shè)計(jì)支持add、sub、multi、or等指令的數(shù)據(jù)通路。（3） 流程控制設(shè)計(jì)設(shè)計(jì)要求：設(shè)計(jì)支持branch、jump等指令的數(shù)據(jù)通路。（4） 基于MIPS指令的單周期微控制器設(shè)計(jì)設(shè)計(jì)要求：同組同學(xué)共同完成具有10條左右指令的單周期微控制器設(shè)計(jì)?；疽螅?）確定設(shè)計(jì)采用的結(jié)構(gòu)2）劃分所確定的結(jié)構(gòu)，畫出模塊圖，確定模塊間的連接關(guān)系，端口方向及寬度3）確定設(shè)計(jì)的驗(yàn)證方案，驗(yàn)證點(diǎn)及驗(yàn)證向量4）完

3、成設(shè)計(jì)的RTL建模及測(cè)試平臺(tái)建模5）完成設(shè)計(jì)的驗(yàn)證、邏輯綜合，給出設(shè)計(jì)的評(píng)價(jià)（面積、速度）6）完成設(shè)計(jì)報(bào)告工作量：本課程設(shè)計(jì)按照每4人一組分工協(xié)作完成。每位成員完成設(shè)計(jì)要求中的（1）（3）任務(wù)之一，作為獨(dú)立完成項(xiàng)，在完成個(gè)人項(xiàng)目基礎(chǔ)上共同完成設(shè)計(jì)要求中的第（4）項(xiàng)。熟悉開發(fā)環(huán)境、學(xué)習(xí)EDA工具使用：10學(xué)時(shí)分析題目、確定設(shè)計(jì)方案：5學(xué)時(shí)設(shè)計(jì)、驗(yàn)證、綜合以及結(jié)果分析、整理數(shù)據(jù)：25學(xué)時(shí)工作計(jì)劃安排： 2015.7.272015.7.28 學(xué)習(xí)modelsim、DesignCompiler使用方法 2015.7.292015.7.30 分析設(shè)計(jì)題目，確定結(jié)構(gòu)及模塊劃分 2015.7.312015.

4、8.6 完成設(shè)計(jì)、驗(yàn)證、綜合與性能分析 2015.8.7 提交課程設(shè)計(jì)報(bào)告 同組設(shè)計(jì)者及分工： 指導(dǎo)教師簽字_ 年 月 日 教研室主任意見： 教研室主任簽字_ 年 月 日*注：此任務(wù)書由課程設(shè)計(jì)指導(dǎo)教師填寫。一、 功能描述基于MIPS指令的單周期微控制器設(shè)計(jì)：l_w和s_w指令的實(shí)現(xiàn)：控制器實(shí)現(xiàn)支持load word(lw)、store word(sw)指令的MIPS單周期數(shù)據(jù)通路： l_w：寄存器rs中的數(shù)據(jù)和立即數(shù)imm相加，得到存儲(chǔ)器地址，用這個(gè)地址訪問存儲(chǔ)器，把得到的存儲(chǔ)器數(shù)據(jù)寫入寄存器rt中。把PC + 4寫入PC。 s_w：寄存器rs中的數(shù)據(jù)和立即數(shù)imm相加，得到存儲(chǔ)器地址，把寄

5、存器rt中的數(shù)據(jù)寫入這個(gè)地址的存儲(chǔ)器中。把PC + 4寫入PC。二、 設(shè)計(jì)方案：1. 整體框圖：2. 模塊劃分：下圖中，各個(gè)大模塊中還包含：立即數(shù)符號(hào)位擴(kuò)展，寄存器堆，存儲(chǔ)器，ALU，指令寄存器，PC，控制部件3. 模塊連接框圖：4. 總體設(shè)計(jì)思想：我設(shè)計(jì)的部分主要包三四部分，分別為：指令寄存器、寄存器堆、和存儲(chǔ)器，額外還有一個(gè)Alu，即加法器和一個(gè)pc，即程序計(jì)數(shù)器，是借助同組同學(xué)編譯的程序。存取指令需要兩個(gè)狀態(tài)單元，計(jì)算下一個(gè)指令地址需要一個(gè)加法器，兩個(gè)狀態(tài)單元分別是指令寄存器和程序寄存器。指令寄存器是制度的，任意時(shí)刻的輸出都反映了輸入的地址的內(nèi)容，而不需要讀控制信號(hào)。程序計(jì)數(shù)器是一個(gè)32

6、位的寄存器，讓在每個(gè)時(shí)鐘周期末都會(huì)被寫入。加法器被設(shè)計(jì)為只進(jìn)行加法運(yùn)算的ALU，他將輸入的倆個(gè)32位數(shù)相加將結(jié)果輸出。Mips指令執(zhí)行時(shí)，首先需要的是指令存儲(chǔ)器，用來存儲(chǔ)指令，并根據(jù)所給地址提供指令，指令地址存放在pc中，pc的設(shè)計(jì)還需要一個(gè)加法器來指向下一個(gè)指令的地址。在執(zhí)行R型指令時(shí)，讀兩個(gè)寄存器，對(duì)他們中的內(nèi)容進(jìn)行Alu操作，再寫出結(jié)果。處理器的32個(gè)寄存器組成一個(gè)寄存器堆的結(jié)構(gòu)，即register。在讀取指令的時(shí)候，一般形式為：op rs rt imm，此時(shí)需要將一個(gè)16位的立即數(shù)帶符號(hào)擴(kuò)充為32位，然后和rs地址內(nèi)的內(nèi)容通過Alu加法器相加，如果是讀取指令即load word ,即得

7、出的是存儲(chǔ)器地址，將得出的存儲(chǔ)器地址內(nèi)的內(nèi)容寫入rt所指的寄存器地址處，如果是存儲(chǔ)指令即store word，即得出的存儲(chǔ)器地址用來寫入rt地址內(nèi)的所存內(nèi)容。5. PC程序計(jì)數(shù)器：6. L_w電路圖：7. L_w的設(shè)計(jì)思想： sw rt, imm(rs) ; memoryrs+(sign)imm read_file -format verilog /home/homeO5/user1/dbf4/alu.v /home/homeO5/user1/dbf4/control.v /home/homeO5/user1/dbf4/cpu_top.v /home/homeO5/user1/dbf4/l_s

8、.v /home/homeO5/user1/dbf4/pc.v /home/homeO5/user1/dbf4/regfile.vLoading verilog files: /home/homeO5/user1/dbf4/alu.v /home/homeO5/user1/dbf4/control.v /home/homeO5/user1/dbf4/cpu_top.v /home/homeO5/user1/dbf4/l_s.v /home/homeO5/user1/dbf4/pc.v /home/homeO5/user1/dbf4/regfile.v Detecting input file

9、type automatically (-rtl or -netlist).Running DC verilog readerReading with Presto HDL Compiler (equivalent to -rtl option).Running PRESTO HDLCCompiling source file /home/homeO5/user1/dbf4/alu.vCompiling source file /home/homeO5/user1/dbf4/control.vWarning: /home/homeO5/user1/dbf4/alu.v:13: The stat

10、ements in initial blocks are ignored. (VER-281)Warning: /home/homeO5/user1/dbf4/control.v:7: Port aluc is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/control.v:8: Port pcsource is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/control.v:29: the undeclared symbol i_lw assum

11、ed to have the default net type, which is wire. (VER-936)Warning: /home/homeO5/user1/dbf4/control.v:30: the undeclared symbol i_sw assumed to have the default net type, which is wire. (VER-936)Compiling source file /home/homeO5/user1/dbf4/cpu_top.vWarning: /home/homeO5/user1/dbf4/cpu_top.v:16: the u

12、ndeclared symbol wmem assumed to have the default net type, which is wire. (VER-936)Warning: /home/homeO5/user1/dbf4/cpu_top.v:23: The statements in initial blocks are ignored. (VER-281)Compiling source file /home/homeO5/user1/dbf4/l_s.vWarning: /home/homeO5/user1/dbf4/cpu_top.v:61: The statements i

13、n initial blocks are ignored. (VER-281)Warning: /home/homeO5/user1/dbf4/l_s.v:11: The statements in initial blocks are ignored. (VER-281)Compiling source file /home/homeO5/user1/dbf4/pc.vWarning: /home/homeO5/user1/dbf4/pc.v:4: Port pcin is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/

14、pc.v:5: Port pc4 is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/pc.v:8: The statements in initial blocks are ignored. (VER-281)Warning: /home/homeO5/user1/dbf4/pc.v:17: Port pc_in is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/pc.v:17: Port qa is implicitly typed (VER-9

15、87)Warning: /home/homeO5/user1/dbf4/pc.v:18: Port imm1 is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/pc.v:19: Port imm2 is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/pc.v:21: Port pc_out is implicitly typed (VER-987)Warning: /home/homeO5/user1/dbf4/pc.v:22: Port selec

16、t is implicitly typed (VER-987)Compiling source file /home/homeO5/user1/dbf4/regfile.vWarning: /home/homeO5/user1/dbf4/regfile.v:13: The statements in initial blocks are ignored. (VER-281)Statistics for case statements in always block at line 13 in file /home/homeO5/user1/dbf4/alu.v=| Line | full/ p

17、arallel |=| 23 | auto/auto |=Warning: /home/homeO5/user1/dbf4/l_s.v:11: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Warning: /home/homeO5/user1/dbf4/l_s.v:14: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Inf

18、erred memory devices in process in routine DataMem line 12 in file /home/homeO5/user1/dbf4/l_s.v.=| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |=| register_reg | Latch | 32 | Y | N | N | N | - | - | - | register_reg | Latch | 32 | Y | N | N | N | - | - | - |=Statistics for MUX_

19、OPs=| block name/line | Inputs | Outputs | # sel inputs | MB |=| DataMem/11 | 256 | 32 | 8 | N |=Warning: /home/homeO5/user1/dbf4/l_s.v:158: do20:16 is being read, but does not appear in the sensitivity list of the block. (ELAB-292)Warning: /home/homeO5/user1/dbf4/l_s.v:159: do15:11 is being read, b

20、ut does not appear in the sensitivity list of the block. (ELAB-292)Statistics for case statements in always block at line 154 in file /home/homeO5/user1/dbf4/l_s.v=| Line | full/ parallel |=| 157 | auto/auto |=Warning: /home/homeO5/user1/dbf4/l_s.v:144: Potential simulation-synthesis mismatch if ind

21、ex exceeds size of array register. (ELAB-349)Warning: /home/homeO5/user1/dbf4/l_s.v:145: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Warning: /home/homeO5/user1/dbf4/l_s.v:146: Potential simulation-synthesis mismatch if index exceeds size of array regis

22、ter. (ELAB-349)Warning: /home/homeO5/user1/dbf4/l_s.v:147: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Statistics for MUX_OPs=| block name/line | Inputs | Outputs | # sel inputs | MB |=| InstMem/144 | 128 | 1 | 7 | N |=Inferred memory devices in process

23、 in routine pc line 8 in file /home/homeO5/user1/dbf4/pc.v.=| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |=| pc4_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |=Warning: /home/homeO5/user1/dbf4/pc.v:34: qa is being read, but does not appear in the sensitivity list of the blo

24、ck. (ELAB-292)Statistics for case statements in always block at line 30 in file /home/homeO5/user1/dbf4/pc.v=| Line | full/ parallel |=| 31 | auto/auto |=Warning: /home/homeO5/user1/dbf4/regfile.v:13: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Warning:

25、 /home/homeO5/user1/dbf4/regfile.v:14: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Warning: /home/homeO5/user1/dbf4/regfile.v:19: Potential simulation-synthesis mismatch if index exceeds size of array register. (ELAB-349)Inferred memory devices in proce

26、ss in routine regfile line 16 in file /home/homeO5/user1/dbf4/regfile.v.=| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |=| register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y |

27、N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y |

28、N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y |

29、N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y |

30、N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y |

31、N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y |

32、N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N | register_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |=Statistics for MUX_OPs=| block name/line | Inputs | Outputs | # sel inputs | MB |=| regfile/13 |

33、 32 | 32 | 5 | N | regfile/14 | 32 | 32 | 5 | N |=Presto compilation completed successfully.Current design is now /home/homeO5/user1/dbf4/alu.db:aluWarning: Overwriting design file /home/homeO5/user1/dbf4/DataMem.db. (DDB-24)Warning: Overwriting design file /home/homeO5/user1/dbf4/InstMem.db. (DDB-2

34、4)Loaded 11 designs.Current design is alu.design_vision Current design is alu.10.功能綜合：Report : areaDesign : cpu_topVersion: C-2009.06Date : Fri Aug 7 08:43:23 2015*Library(s) Used: typical (File: /export/homeO5/libs/smic18/std_cell/2005q4v1/aci/sc-x/synopsys/typical.db)Number of ports: 1Number of ne

35、ts: 368Number of cells: 10Number of references: 10Combinational area: 144196.113892Noncombinational area: 377346.823853Net Interconnect area: undefined (No wire load specified)Total cell area: 521542.937745Total area: undefinedReport : timing -path full -delay max -max_paths 1Design : cpu_topVersion: