數(shù)字電路設(shè)計(jì)課件第10講數(shù)字電路中的時(shí)序問題

1、ee141 digital integrated circuits2ndtiming issues1ee141 digital integrated circuits2ndtiming issues2combina t io n allogicr1r2cincoutoutinclkee141 digital integrated circuits2ndtiming issues3ee141 digital integrated circuits2ndtiming issues4dclkqdqclktc-qtholdpwmtsutd-qdelays can be different for ri

2、sing and falling data transitionstee141 digital integrated circuits2ndtiming issues5dclkqdqclktc-qtholdttsudelays can be different for rising and falling data transitionsee141 digital integrated circuits2ndtiming issues6ee141 digital integrated circuits2ndtiming issues7ee141 digital integrated circu

3、its2ndtiming issues8243power s u p p l yinterco n n e c t5 tempera t u r e6 capacit iv e loa d7 couplin g t o ad jacen t lines1 clock g e n e r ati ondevicessources of clock uncertaintyee141 digital integrated circuits2ndtiming issues9r1in(a) pos it i v e s kewcombina t io n allogicdqtclk1clkdelaytc

4、lk2r2dqcombina t io n allogictclk3r3 dqdelayr1in(b) neg a t i v e s kewcombina t io n allogicdqtclk1delaytclk2r2dqcombina t io n allogictclk3r3 dqdelayclkee141 digital integrated circuits2ndtiming issues10clk1clk2tclkdtclk+d+ thd2143launching edge arrives before the receiving edgeee141 digital integ

5、rated circuits2ndtiming issues11clk1clk2tclkdtclk +d2143receiving edge arrives before the launching edge競爭現(xiàn)象永遠(yuǎn)不可能出現(xiàn)競爭現(xiàn)象永遠(yuǎn)不可能出現(xiàn)但是影響電路性能但是影響電路性能ee141 digital integrated circuits2ndtiming issues12regregreg.reglogoutinclock distributionpositive skewnegative skewdata and clock routing設(shè)計(jì)一個偏差小的時(shí)鐘網(wǎng)絡(luò)是非常重要的設(shè)計(jì)

6、一個偏差小的時(shí)鐘網(wǎng)絡(luò)是非常重要的！ee141 digital integrated circuits2ndtiming issues13ee141 digital integrated circuits2ndtiming issues14q時(shí)鐘抖動是指在芯片上的某一個給定點(diǎn)上時(shí)鐘周時(shí)鐘抖動是指在芯片上的某一個給定點(diǎn)上時(shí)鐘周期發(fā)生暫時(shí)性的變化，即時(shí)鐘周期在每個不同的期發(fā)生暫時(shí)性的變化，即時(shí)鐘周期在每個不同的周期上可以縮短或加長。周期上可以縮短或加長。q時(shí)鐘抖動是嚴(yán)格衡量時(shí)鐘暫時(shí)不確定性的一項(xiàng)指時(shí)鐘抖動是嚴(yán)格衡量時(shí)鐘暫時(shí)不確定性的一項(xiàng)指標(biāo)，并且經(jīng)常針對某一給定點(diǎn)進(jìn)行說明。標(biāo)，并且經(jīng)常針對某一給定點(diǎn)

7、進(jìn)行說明。q抖動可以使用許多方法來衡量和表征，它是一個抖動可以使用許多方法來衡量和表征，它是一個平均值為零的隨機(jī)變量平均值為零的隨機(jī)變量ee141 digital integrated circuits2ndtiming issues15clk-tjittertclktjitterclk incombinationallogic tc-q , tc-q, cdtlogictlogic, cdtsu, tholdregstjitter最壞情況下，周期至周期抖動絕對值等最壞情況下，周期至周期抖動絕對值等于絕對抖動的于絕對抖動的2 2倍倍（2tjitter）ee141 digital integra

8、ted circuits2ndtiming issues16時(shí)鐘抖動直接降低了一個時(shí)序電路的性能。時(shí)鐘抖動直接降低了一個時(shí)序電路的性能。如果性能是一個電路的關(guān)鍵因素，應(yīng)該嚴(yán)格如果性能是一個電路的關(guān)鍵因素，應(yīng)該嚴(yán)格把抖動限定在一定的范圍內(nèi)。把抖動限定在一定的范圍內(nèi)。ee141 digital integrated circuits2ndtiming issues17ee141 digital integrated circuits2ndtiming issues18clock skew 0clock skew 0時(shí)的維持時(shí)間約束條件：時(shí)的維持時(shí)間約束條件：clock skew0clock ske

9、w0時(shí)的約束條件：時(shí)的約束條件：ee141 digital integrated circuits2ndtiming issues19時(shí)序分析結(jié)果與前面分析的情況一致時(shí)序分析結(jié)果與前面分析的情況一致負(fù)偏差會降低性能負(fù)偏差會降低性能ee141 digital integrated circuits2ndtiming issues20clkclock is distributed in a tree-like fashionh-treeee141 digital integrated circuits2ndtiming issues21restle98ee141 digital integrate

10、d circuits2ndtiming issues22driverdriverdriverdrivergclkgclkgclkgclkno rc-matchinglarge poweree141 digital integrated circuits2ndtiming issues23clock frequency: 300 mhz - 9.3 million transistorstotal clock load: 3.75 nfpower in clock distribution network : 20 w (out of 50)uses two level clock distri

11、bution: single 6-stage driver at center of chip secondary buffers drive left and right sideclock grid in metal3 and metal4total driver size: 58 cm!ee141 digital integrated circuits2ndtiming issues24q2 phase single wire clock, distributed globallyq2 distributed driver channels reduced rc delay/skew i

12、mproved thermal distribution 3.75nf clock load 58 cm final driver widthqlocal inverters for latchingqconditional clocks in caches to reduce powerqmore complex race checkingqdevice variationtrise = 0.35ns tskew = 150pstcycle= 3.3nsclock waveformlocation of clockdriver on diepre-driverfinal driversee1

13、41 digital integrated circuits2ndtiming issues25clock driversee141 digital integrated circuits2ndtiming issues26ee141 digital integrated circuits2ndtiming issues27q2 phase, with multiple conditional buffered clocks2.8 nf clock load40 cm final driver widthqlocal clocks can be gated “off” to save powe

14、rqreduced load/skewqreduced thermal issuesqmultiple clocks complicate race checkingtrise = 0.35nstskew = 50pstcycle= 1.67nsglobal clock waveformpllee141 digital integrated circuits2ndtiming issues28ee141 digital integrated circuits2ndtiming issues29gclk skew(at vdd/2 crossings)ps5101520253035404550e

15、e141 digital integrated circuits2ndtiming issues30ee141 digital integrated circuits2ndtiming issues31q為使偏差最小，可以采用為使偏差最小，可以采用h h樹或者更為一般的布樹或者更為一般的布線匹配的樹結(jié)構(gòu)，使從中央時(shí)鐘分配源到單個鐘線匹配的樹結(jié)構(gòu)，使從中央時(shí)鐘分配源到單個鐘控元件的時(shí)鐘路徑均衡。在采用時(shí)鐘樹布線時(shí)，控元件的時(shí)鐘路徑均衡。在采用時(shí)鐘樹布線時(shí)，必須使包括導(dǎo)線和晶體管負(fù)載在內(nèi)的每條路徑時(shí)必須使包括導(dǎo)線和晶體管負(fù)載在內(nèi)的每條路徑時(shí)鐘負(fù)載相等。鐘負(fù)載相等。q采用局部時(shí)鐘網(wǎng)絡(luò)（而不是樹型布線

16、）可以減小采用局部時(shí)鐘網(wǎng)絡(luò)（而不是樹型布線）可以減小時(shí)鐘偏斜，但代價(jià)是增加了電容負(fù)載和功耗時(shí)鐘偏斜，但代價(jià)是增加了電容負(fù)載和功耗。ee141 digital integrated circuits2ndtiming issues32q如果與數(shù)據(jù)相關(guān)的時(shí)鐘負(fù)載變化引起了如果與數(shù)據(jù)相關(guān)的時(shí)鐘負(fù)載變化引起了顯著的抖動，就應(yīng)當(dāng)使用時(shí)鐘負(fù)載不受顯著的抖動，就應(yīng)當(dāng)使用時(shí)鐘負(fù)載不受數(shù)據(jù)影響的差分寄存器。數(shù)據(jù)影響的差分寄存器。q數(shù)據(jù)如果沿一個方向流動，可以使數(shù)據(jù)數(shù)據(jù)如果沿一個方向流動，可以使數(shù)據(jù)和時(shí)鐘按相反方向布線。這樣可以消除和時(shí)鐘按相反方向布線。這樣可以消除競爭，代價(jià)是性能有所降低競爭，代價(jià)是性能有所降低

17、. .ee141 digital integrated circuits2ndtiming issues33q通過將時(shí)鐘線與相鄰信號線屏蔽，可以避免與通過將時(shí)鐘線與相鄰信號線屏蔽，可以避免與數(shù)據(jù)相關(guān)的噪聲。把電源線（數(shù)據(jù)相關(guān)的噪聲。把電源線（vddvdd或或gndgnd）放在）放在時(shí)鐘線的旁邊可以減少或避免與相鄰信號網(wǎng)絡(luò)時(shí)鐘線的旁邊可以減少或避免與相鄰信號網(wǎng)絡(luò)的耦合。的耦合。q由于層間絕緣電介質(zhì)厚度不均造成互連電容的由于層間絕緣電介質(zhì)厚度不均造成互連電容的變化可以通過采用虛設(shè)填料來大大減少。虛設(shè)變化可以通過采用虛設(shè)填料來大大減少。虛設(shè)填料的是使用非常普遍，它通過提高絕緣層的填料的是使用非常普遍

18、，它通過提高絕緣層的一致性來減少時(shí)鐘偏差。系統(tǒng)性的偏差應(yīng)通過一致性來減少時(shí)鐘偏差。系統(tǒng)性的偏差應(yīng)通過模擬并予以彌補(bǔ)模擬并予以彌補(bǔ)。ee141 digital integrated circuits2ndtiming issues34q芯片上各處溫度不均勻會引起時(shí)鐘緩沖延時(shí)的芯片上各處溫度不均勻會引起時(shí)鐘緩沖延時(shí)的變化，采用基于延時(shí)鎖定環(huán)（變化，采用基于延時(shí)鎖定環(huán)（delay-locked loop)delay-locked loop)的的反饋電路可以彌補(bǔ)溫度偏差問題。反饋電路可以彌補(bǔ)溫度偏差問題。q電源供電不穩(wěn)是引起抖動的重要原因，因?yàn)檫@電源供電不穩(wěn)是引起抖動的重要原因，因?yàn)檫@會使經(jīng)過時(shí)鐘緩沖器的延時(shí)在周期與周期之間會使經(jīng)過時(shí)鐘緩沖器的延時(shí)在周期與周期之間不同。通過加入片上去耦電容可以