畢業(yè)設(shè)計(jì)論文 外文文獻(xiàn)翻譯 單片機(jī)類 AT89C2051 中英文對(duì)照

1、at89c2051author:yuan zhenming,zhang liang,zhan guohua;from: http:/www.webct.comat89c2051 is made in the atmel corporation, which is the low-voltage, high-performance cmos8-bit microcontroller,tablets containing repeated 2k bytes of program memory erasable read-only (perom) and random 128bytes data m

2、emory (ram), device using atmel's high density, non-volatile memory technology, compatible with the standard of mcs-51 instruction set, built-chip 8-bit general-purpose central processing unit and repeatedly write the flash memory, which can effectively reduce the development costs. at89c2051 fe

3、atures a powerful single-chip can provide cost-effective in many applications.main features:compatible the mcs51 command system;contains the 2kb memory re-programming flash (1000);2.7 6v voltage range;the whole static work: 0hz 24khz;secrets 2 program memory lock128 × 8-bit internal ram15 progr

4、ammable i / o linestwo 16-bit timer / counter6 interrupt sources, two external interrupt sourcesprogrammable serial channelhigh precision voltage comparator （p1.0，p1.1，p3.6）；have the output port of the led direct drive low-power idle and power-down mode the pin picture of at89c2051picture one the pi

5、n of at89c2051at89c2051s functional description:vcc: power supply voltagegnd: land p1 port: p1 mouth is a group of 8-bit bi-directional i / o interface, p1.2 p1.7 provide internal pull-up resistor,p1.0 and p1.1 internal supreme pull-up resistor. p1 mouth output buffer can absorb the current 20ma and

6、 direct-drive led.when programming and calibration, p1 mouth as the eighth address receive.p3 mouth: p3 port p3.0 p3.5, p3.7 is the internal pull-up resistor with the seven bi-directional i / o interface. did not bring out the p3.6，it as a generic i / o port, but can not visit. can be used as a fixe

7、d-chip input comparator output signal. when p3 write 1, they were highed the internal pull-up resistor can be raised as an input port.p3 port special function as shown in table 1:table 1 p3 mouths special features引腳功能特性p3.0rxd （串行輸入口)p3.1txd （串行輸出口）p3.2 (外中斷0)p3.3 (外中斷1)p3.4t0 (定時(shí)/計(jì)數(shù)器0外部輸入)p3.5t1 （定

8、時(shí)/計(jì)數(shù)器1外部輸入）rst：reset output. when the oscillator device reset, rst pin to maintain the high level of two machine cycle time.xtal1: the rp-oscillator amplifier and internal clock generator input.timeroverview of the timer 89c2051 single-chip-chip has two 16-bit timer / counter, that is the timer 0 (t

9、0) and timer 1 (t1). they all have from time to time and event count function, can be used for timing control, delay of external events, such as counting and testing occasions. timers t0 and t1 two 16-bit timers in fact is 16-bit counter plus 1. among them, t0 compositioned by the two 8-bit special

10、function registers th0 and tl0; t1 posed by the th1 and tl1. these functions were controled by the special function registers tmod and tcon when set to the work in the timing, through the pin count of the external pulse signal. when the input pulse signal generated by the falling edge of 1-0, the va

11、lue of timer plus 1. at of every machine cycle during the s5p2 sampling pin t0 and t1 the input level, if a machine cycle before sample value of 1, the next machine cycle sampling value is 0, the counter plus 1. since then during s3p1 of the machine cycle, new value will into the counter.so detectio

12、n of a 1-0 transition of the two machine cycles,so the maximum count frequency of oscillation frequency of 1 / 24. in addition to the option of work from time to time or count,each timer / counter have four kinds of work mode, that is, each of timer circuit kinds of four constitute a structural mode

13、ltwo low-power modeidle modein idle mode, cpu to maintain sleep and all-chip peripherals remain active, this way generated in software, at this point, chip ram and all the contents of special function registers remain unchanged. idle mode was terminated by any interrupt request permission to or hard

14、ware reset.p1.0 and p1.1 ,in the non-use of external pull-up resistor on the case should be set to "0", or in the use of pull-up resistor is set to "1."it should be noted that: when uses of hardware reset termination idle mode, at89c2051 is usually stopped from the program until

15、the internal reset control of the two machine cycles before the restore procedure service. in this case the hardware within the prohibition of the reading and writing of internal ram, however, to allow access to ports, to eliminate the hardware reset in the idle mode of port accidents may write, in

16、principle, to enter the idle mode of instruction should not be under the command of a pin or an external memory port for a visit.power-down modein power-down mode, the oscillator to stop working, enter the power-down mode ,instructions, who was the last one, the implementation of the directive, chip

17、 ram and all the contents of special function registers the termination of the previous power-down mode be frozen. to withdraw from power-down mode is the only way to reset the hardware, reset will redefine all the special function registers but does not change the contents of ram before the the vcc

18、 work returned to normal levels shall be null and void and must be reset to maintain a certain period of time in order to restart and oscillator stabilityp1.0 and p1.1 in the non-use of external pull-up resistor on the case should be set to "0", or in the use of pull-up resistor is set to

19、"1."oscillatoroscillator connected clientxtal1: rp-oscillator amplifier and internal clock generator inputxtal2: rp-oscillator amplifier outputcharacteristics of oscillator xtal1, xtal2 ware the rp-chip oscillator amplifier inputs and outputs, quartz crystal can be composed of the clock os

20、cillator or ceramic oscillator, for more information from the external input clock driver at89c2051, xtal1 input clock signal from, xtal2 should be left vacant.as the input to the internal circuit is a 2-flip-flop, therefore, the external clock signal input without special requirements, however, it

21、must comply with the maximum level and minimum norms and timingat89c2051作者：yuan zhenming, zhang liang, zhan guohua；來(lái)自：http:/www.webct.comat89c2051是美國(guó)atmel公司生產(chǎn)的低電壓、高性能cmos8位單片機(jī)，片內(nèi)含2k bytes的可反復(fù)擦寫的只讀程序存儲(chǔ)器（perom）和128bytes的隨機(jī)數(shù)據(jù)存儲(chǔ)器（ram），器件采用atmel公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)mcs-51指令系統(tǒng)，片內(nèi)置通用8位中央處理器和可反復(fù)擦寫的flash存儲(chǔ)器

22、，可有效地降低開(kāi)發(fā)成本。功能強(qiáng)大at89c2051單片機(jī)可提供許多高性價(jià)比的應(yīng)用場(chǎng)合。3.2主要功能特性： *兼容mcs51指令系統(tǒng)；*2kb可重編程flash存儲(chǔ)器（1000次）；*2.76v電壓范圍；*全靜態(tài)工作：0hz24khz；*2級(jí)程序存儲(chǔ)器保密鎖定；* 128×8位內(nèi)部ram；*15條可編程i/o線； *兩個(gè)16位定時(shí)器/計(jì)數(shù)器；*6個(gè)中斷源，兩個(gè)外部中斷源；*可編程串行通道；*高精度電壓比較器（p1.0，p1.1，p3.6）； *直接驅(qū)動(dòng)led的輸出端口；*低功耗空閑和掉電模式at89c2051的管腳引腳圖如圖2所示。 圖1 at89c2051封裝管腳引腳圖at89c2

23、051引腳功能說(shuō)明：vcc：電源電壓gnd：地p1口：p1口是一組8位雙向i/o接口，p1.2p1.7提供內(nèi)部上拉電阻，p1.0和p1.1內(nèi)部無(wú)上拉電阻。p1口輸出緩沖器可吸收20ma的電流并可直接驅(qū)動(dòng)led。編程和校驗(yàn)時(shí)， p1口作為第八位地址接收。p3口：p3口的p3.0p3.5、p3.7是帶有內(nèi)部上拉電阻的7個(gè)雙向i/o接口。p3.6沒(méi)有引出，它作為一個(gè)通用的i/o口，但是不可訪問(wèn)?？勺鳛楣潭ㄝ斎氲钠瑑?nèi)比較器的輸出信號(hào)。當(dāng)p3口寫入1時(shí)，它們被內(nèi)部的上拉電阻拉高并可作為輸入端口。p3口的特殊功能如表1所示：rst：復(fù)位輸出。當(dāng)振蕩器復(fù)位器件時(shí)，要保持rst腳兩個(gè)機(jī)器周期的高電平時(shí)間。xt

24、al1：振蕩器的反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。xtal2：振蕩器反相放大器的輸出端。表1 p3口的特殊功能引腳功能特性p3.0rxd （串行輸入口)p3.1txd （串行輸出口）p3.2 (外中斷0)p3.3 (外中斷1)p3.4t0 (定時(shí)/計(jì)數(shù)器0外部輸入)p3.5t1 （定時(shí)/計(jì)數(shù)器1外部輸入）定時(shí)器定時(shí)器概述89c2051單片機(jī)片內(nèi)有兩個(gè)16位定時(shí)器/計(jì)數(shù)器，即定時(shí)器0（t0）和定時(shí)器1（t1）。它們都有定時(shí)和事件計(jì)數(shù)功能，可用于定時(shí)控制、延時(shí)、對(duì)外部事件計(jì)數(shù)和檢測(cè)等場(chǎng)合。定時(shí)器t0和t1兩個(gè)16位定時(shí)器實(shí)際上都是16位加1計(jì)數(shù)器。其中，t0由兩個(gè)8位特殊功能寄存器th0和tl0構(gòu)成；t1由th1和tl1構(gòu)成。這些功能都由特殊功能寄存器tmod和tcon所控制。 設(shè)置為定時(shí)工作方式時(shí)，定時(shí)器計(jì)數(shù)at89c2051片內(nèi)振蕩器輸出的經(jīng)12分頻后的脈沖，即每個(gè)機(jī)器周期使定時(shí)器的數(shù)值加1直至計(jì)滿溢出。當(dāng)at89c205采用12mhz晶振時(shí)，一個(gè)機(jī)器周期為1µs,計(jì)數(shù)頻率為1mhz。設(shè)置為計(jì)數(shù)工作方式時(shí)，通過(guò)引腳對(duì)外部脈沖信號(hào)計(jì)數(shù)。當(dāng)輸入脈沖信號(hào)產(chǎn)生由1至0的下降沿時(shí)，定時(shí)器的值加1。在每個(gè)機(jī)器周期的s5p2期間采樣t0和t1引腳的輸入電平，若前一個(gè)機(jī)器周期采樣值為1，下一個(gè)機(jī)器周期采樣值為0，則計(jì)數(shù)器加1。此后的機(jī)器周期s3p1期間，新的數(shù)值裝入計(jì)數(shù)器。所以，檢