VHDL各種計(jì)數(shù)器程序

1、1. 具有clk, q端口的簡(jiǎn)單加法計(jì)數(shù)器，要程序和最后的rtl圖;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 isport ( clk : in std.logic;q : out integer range 15 downto 0);end;architecture behav of cnt4 issignal d,q1 : integer range 15 downto 0;beginprocess (clk)beginif clk'event and c

2、lk=f vthen qiv二d;end if;end process;d<=qi + 1;q<=q1；end behav;2. 具有異步清零aclr, clk, q端口的加法計(jì)數(shù)器，要程序和最后的rtl圖;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 isport ( clk,aclr :in std_logic;q : out std_logic_vector( 15 downto 0);end ;architecture behav of cnt4 is

3、signal qi : std_logic_vector( 15 downto 0);beginprocess (clk,aclr)beginif aclr=,o, thenqlv=(others二>o);elsif clk event and clk二t then q1<=q1 + 1;end if;end process;q<=q1；end behav;q15.o3. 具有同步清零sell, clk, q端口的加法計(jì)數(shù)器，要程序和最后的rtl圖;library ieee;use ieee.std_logic_1164.all ;use ieee.std_logic_uns

4、igned.all;entity cnt4 isport ( clk,sclr :in std_log1c;q : out std_logic_vector( 15 downto 0);end ;architecture behav of cnt4 issignal qi : std_logic_vector( 15 downto 0);beginprocess (clk,sclr)beginif clk'event and clk二t thenifsclr 二 tthenqi "(others二>o);elseq1<=q1 + 1;end if;end if;e

5、nd process;q<=q1;aririnmux21q115.0lqf15.0lend behav;clk >sclri >4. 具有異步置位apre, clk, q端口的加法計(jì)數(shù)器，要程序和最后的rtl圖;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 isport(clk :in std.logic;apre:in std_logic;q :out std_l0gic_vect0r(3 downto 0);end;architecture beha

6、v of cnt4 issignal qi :std_logic_vector(3 downto 0);beginprocess(clk,apre)beginif apre 二 tthenqlv=”0001”；elsif clk'event and clk=t thenqk=q1 + 1;end if;end process;addo5. 具有同步置位spre, clk, q端口的加法計(jì)數(shù)器，要程序和最后的rtl圖;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 i

7、sport(clk :in std.logic;spre:in std_logic;q :out std_l0gic_vect0r(3 downto 0);end;architecture behav of cnt4 issignal qi :std_logic_vector(3 downto 0);beginprocess(clk,spre)beginif clkfevent and clk二t thenif spre二tthenqlv=”0001”;elseqk=q1+1;end if;end if;end process;q3.o6. 具有異步清零aclr,異步置位apre, clk,

8、q端口的加法計(jì)數(shù)器，要程序和最后的rtl 圖；library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 isport(clk :in std.logic;aclr:in std_logic;apre:in std_logic;q :out std_l0gic_vect0r(3 downto 0);end;architecture behav of cnt4 issignal qi :std_l0gic_vect0r(3 downto 0);beginprocess(clk,apre,

9、aclr)beginifaclr 二 tthenqlvioooo”；elseifapre二tthenqi<=,ooor,；elsif clk event and clk二t thenq1<=q1 + 1;end if;end if;end process;q<=q1；end behav;7. 具有同步使能enb, clk, q端口的加法計(jì)數(shù)器，要程序和最后的rtl圖;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 isp0rt(clk :in std_lo

10、gic;enb :in std.logic;q :out std_l0gic_vect0r(3 downto 0);end;architecture behav of cnt4 issignal qi :std_logic_vector(3 downto 0);beginprocess(clk,enb)beginif clkevent and clk=r v thenif enb 二 t thenq1<=q1 + 1;end if;end if;end process;q<=q1；end behav;8. 具有異步清零aclr,異步置位apre,同步使能enb, clk, q端口的

11、加法計(jì)數(shù)器，要程 序和最后的rtl圖；library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 isport(clk :in std_l0gic;aclr:in std_l0gic;enb :in std_l0gic;apre:in std_logic;q :out std_logic_vector(3 downto 0);end;architecture behav of cnt4 issignal qi :std_l0gic_vect0r(3 downto 0);beginprocess(clk,apre,aclr,en