數(shù)字邏輯教學課件 vhdl3

1、5.5.3 vhdl語言的描述風格語言的描述風格三種描述風格：三種描述風格： 行為描述：行為描述：使用功能描述使用功能描述 數(shù)據(jù)流（寄存器傳輸）：數(shù)據(jù)流（寄存器傳輸）：使用布爾代數(shù)式描述使用布爾代數(shù)式描述 結構描述：結構描述：模塊間的連接關系描述模塊間的連接關系描述 5.5.4 基本邏輯電路的基本邏輯電路的vhdl設計設計一、組合電路一、組合電路 原則原則1 1：在在processprocess中用到的所有輸入信號都出現(xiàn)在敏中用到的所有輸入信號都出現(xiàn)在敏感信號列表中；感信號列表中；原則原則2 2：電路的真值表必須在代碼中完整的反映出來。電路的真值表必須在代碼中完整的反映出來。( (否則會生成鎖

2、存器否則會生成鎖存器) )1.1.三態(tài)門及總線緩沖器三態(tài)門及總線緩沖器指定大寫指定大寫“ “z”z”表示高阻態(tài)表示高阻態(tài) a = z ;a = z ; a_bus = “zzzzzzzz” ; a_bus = “zzzzzzzz” ; library library ieee; ieee; use use ieee.std_logic_1164. ieee.std_logic_1164.allall; ; entity entity tri_gate tri_gate isis port ( din, en: port ( din, en: inin std_logic; std_logic;

3、 dout: dout: outout std_logic ); std_logic ); end end tri_gate; tri_gate; architecturearchitecture art art ofof tri_gate tri_gate isis begin begin processprocess (din,en) (din,en) beginbegin ifif (en= 0) (en= 0) thenthen dout = din dout = din； elseelse dout=z; dout=z; end ifend if； endend process pr

4、ocessendend art; art;dinenendout8 8位數(shù)據(jù)總線？位數(shù)據(jù)總線？2. 8:3優(yōu)先編碼器優(yōu)先編碼器g gs slibrary ieee;use ieee.std_logic_1164.all;entity priencoder isport (din:in std_logic_vector(7 downto 0); ei:in std_logic; yout:out std_logic_vector(2 downto 0); eo,gs:out std_logic);end priencoder;architecture cod74148 of priencoder

5、 isbegin process(ei,din) begin if(ei=1)then yout = 111; eo = 1; gs = 1; else if (din(7)=0)then yout = 000; eo = 1 ; gs = 0 ; elsif (din(6)=0)then yout = 001; eo = 1 ; gs = 0 ; elsif (din(5)=0)then yout = 010; eo = 1 ; elsif (din(0)=0)then yout = 111; eo = 1 ; gs = 0 ; else yout = 111; eo = 0 ; gs =

6、1 ; end if; end if; end process;end cod74148;觸發(fā)器、寄存器、計數(shù)器、分頻器、節(jié)拍發(fā)生器、觸發(fā)器、寄存器、計數(shù)器、分頻器、節(jié)拍發(fā)生器、狀態(tài)機等。狀態(tài)機等。二、二、 時序邏輯電路設計時序邏輯電路設計時鐘上升沿：時鐘上升沿： （clockevent and clock = 1）時鐘下降沿：時鐘下降沿： （clockevent and clock = 0）進程的敏感信號是時鐘信號，在進程內(nèi)部用進程的敏感信號是時鐘信號，在進程內(nèi)部用if if 語句語句描述時鐘的邊沿條件。描述時鐘的邊沿條件。敏感信號表的特點：敏感信號表的特點： 1) 1) 敏感信號表中只有時

7、鐘信號同步復位等。敏感信號表中只有時鐘信號同步復位等。 如：如： process process ( (clkclk) ) beginbegin if if (clkevent and clk = 1) (clkevent and clk = 1) thenthen if if reset = 1 reset = 1 thenthen data = “00”; data = “00”; elseelse data = in_data; data = in_data; end ifend if; ; end end if; if; end processend process; ;最先判斷時鐘最

8、先判斷時鐘同步復位同步復位同步復位2d觸發(fā)器觸發(fā)器2) 2) 敏感信號表中除時鐘外，還有其它信號異步操作敏感信號表中除時鐘外，還有其它信號異步操作 例：例： processprocess ( (clkclk，resetreset) ) beginbegin if if reset = 1 reset = 1 thenthen data = “00”; data = “00”; elsifelsif (clkevent and clk = 1) (clkevent and clk = 1) thenthen data = in_data; data = in_data; end end if;

9、if; end processend process; ; 最先判斷異步復位最先判斷異步復位同步、異步區(qū)別：敏感信號表、語句順序同步、異步區(qū)別：敏感信號表、語句順序對于判斷時鐘電路對于判斷時鐘電路邊沿，邊沿， 后沒有后沒有“else”else”語句。語句。 2) 2) 計數(shù)器計數(shù)器描述計數(shù)器描述計數(shù)器 (std_logic_vector)(std_logic_vector)，要用到中間信號，要用到中間信號和標準的程序包：和標準的程序包：ieee.std_logic_unsigned ieee.std_logic_unsigned library ieee;use ieee.std_logic_

10、1164.all;use ieee.std_logic_unsigned.all;entity counter10 is port ( clk : in std_logic; load : in std_logic; din : in std_logic_vector(3 downto 0); qout : out std_logic_vector(3 downto 0)； c: out std_logic);end counter10;例：異步置數(shù)例：異步置數(shù)(低有效）的低有效）的10進制計數(shù)器。進制計數(shù)器。architecture art of counter10 is signal te

11、mp : std_logic_vector(3 downto 0);beginprocess (clk, load, din) begin if (load= 0 ) then temp = din; elsif (clkevent and clk= 1) then if (temp = “1001“) then temp = 0000; else temp = temp+1; end if; end if;end process; qout = temp; c = 1 when temp=“1001” else 0; end art;為描述計數(shù)過程，為描述計數(shù)過程，定義中間信號。定義中間信號

12、。 -if (temp=9) then-when temp=9 elseprocess (clk, reset, din) begin if (load= 0 ) then temp = din; elsif (clkevent and clk= 1) then if (temp = 9) then temp = 0000; c = 1; else temp = temp+1; c = 0; end if; end if;end process; qout = temp;end art if (clkevent and clk= 1) then if (temp = m-1) then tem

13、p = 0000; else temp = temp+1; end if; end if ;end process ;q = temp; c = 1 when temp=m-1 else 0;例：六十進制（分、秒）計數(shù)器例：六十進制（分、秒）計數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity clock60 is port ( clk : in std_logic; clr : in std_logic; s1 : out std_logic_vector(3 downto 0);

14、 s10 : out std_logic_vector(2 downto 0); co : out std_logic );end clock60;architecture art of clock60 is signal s1_temp : std_logic_vector(3 downto 0); signal s10_temp : std_logic_vector(2 downto 0);與一般二進制計數(shù)器與一般二進制計數(shù)器不同，分個位十位顯不同，分個位十位顯示，為分、秒計數(shù)示，為分、秒計數(shù)begin process (clk, clr) begin if (clr= 1) then s

15、1_temp = “0000”; s10_temp = “000”; elsif (clkevent and clk= 1) then if (s1_temp= 9) then s1_temp= 0000; if (s10_temp = 5) then s10_temp= “000”; else s10_temp = s10_temp+1; end if; else s1_temp = s1_temp+1; end if; end if; end process; s1 = s1_temp; s10 = s10_temp; co = 1 when ( s10_temp=5 and s1_tem

16、p=9) else 0;end art;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity add is port(clk, x,y:in std_logic; qout: out std_logic_vector (2 downto 0); co:out std_logic);end add;architecture behv of add is signal con : std_logic_vector (1 downto 0); signal temp : std_logic_ve

17、ctor (2 downto 0); signal m : integer range 7 downto 0;begin process(x,y) begin con m m m m= 7; end case; end process; ?？煽赜嫈?shù)器?？煽赜嫈?shù)器（由輸入（由輸入x,yx,y控制）控制）m=3,4,6,7 process (clk, m) begin if (clkevent and clk=1) then if (temp = m-1) then temp = 000; else temp =temp+1; end if; end if; end process; qout =

18、 temp ; co = 1 when temp=m-1 else 0 ; end behv;m=3,4,6,7例：設計例：設計5000分頻器分頻器library ieee;use ieee.std_logic_1164.all;entity fp is port ( clk : in std_logic; clkout : out std_logic);end fp;architecturearchitecture art art ofof fpfp is is signal temp: integer range 0 to 4999;beginbegin processprocess (c

19、lk)(clk) begin begin if if (clkevent and clk=1) (clkevent and clk=1) thenthen if if ( temp=4999) ( temp=4999) thenthen temp = 0 ; temp = 0 ; else else temp = temp+1; temp = temp+1; end ifend if; ;end if;end if;end processend process; ;clkout = 1 when ( temp2500) else 0; end end art;art;（占空比（占空比5050）

20、例：例：8位環(huán)形移位寄存器（左、右移、異步置數(shù)）位環(huán)形移位寄存器（左、右移、異步置數(shù)）librarylibrary ieee; ieee;use use ieee.std_logic_1164.ieee.std_logic_1164.allall; ;entity entity shfrt shfrt is is port port ( clk ,load,con: ( clk ,load,con: in in std_logic;std_logic; din: din: in in std_logic_vector (7 downto 0);std_logic_vector (7 downt

21、o 0); qout qout : : out std_logic_vector (7 downto 0) std_logic_vector (7 downto 0) ); );endend shfrt; shfrt;architecturearchitecture art art of of shfrtshfrt is is signal signal q_temp: std_logic_vector (7 downto 0);q_temp: std_logic_vector (7 downto 0); beginbegin process process (clk,load,din) (c

22、lk,load,din) beginbegin if if load=1 load=1 thenthen q_temp = din; q_temp = din; elsif elsif (clkevent (clkevent andand clk= 1) clk= 1) thenthen if if con=1 con=1 then then q_temp = q_temp (6 q_temp = q_temp (6 downtodownto 0) & q_temp(7) ;0) & q_temp(7) ; elseelse q_temp = q_temp(0) & q

23、_temp (7 q_temp = q_temp(0) & q_temp (7 downtodownto1);1); end ifend if; ; end ifend if; ; endend process process; ; qout = q_temp; qout = q_temp;end end art;art;例：環(huán)型順序脈沖發(fā)生器例：環(huán)型順序脈沖發(fā)生器(4位）位）library ieee;use ieee.std_logic_1164.all;entity index is port ( clk ,ld: in std_logic; y : out std_logic_v

24、ector (3 downto 0) );end index;architecture art of index is signal q: std_logic_vector (3 downto 0);begin process process (clk) (clk) beginbegin if if (clkevent (clkevent and and clk= 1)clk= 1) thenthen if if ld=0 ld=0 thenthen q = “1000” ; q = “1000” ; elseelse q = q (0) & q (3 q = q (0) &

25、q (3 downto downto1);1); end ifend if; ; end ifend if; ; endend process process; ; y = q ; y = q ; end art;3) 3) 狀態(tài)機狀態(tài)機 用戶自定義數(shù)據(jù)類型用戶自定義數(shù)據(jù)類型利用用戶自定義數(shù)據(jù)類型枚舉類型實現(xiàn)。利用用戶自定義數(shù)據(jù)類型枚舉類型實現(xiàn)。type type 數(shù)據(jù)類型名數(shù)據(jù)類型名 is is 數(shù)據(jù)類型定義（枚舉）數(shù)據(jù)類型定義（枚舉）; ; 語法格式：語法格式：綜合器自動實現(xiàn)枚舉類型元素的編碼綜合器自動實現(xiàn)枚舉類型元素的編碼type statetype is (s0, s1, s2, s3

26、);signal present_state, next_state : statetype; type week is (sun, mon, tue, wed, thu, fri, sat);signal day : week ; day = sun; present_state 1 = 順序處理語句順序處理語句1111；語句；語句1212； when when 表達式值表達式值3 3 = = 順序處理語句順序處理語句3131；語句；語句32;32; end caseend case；moore moore 型狀態(tài)機的描述型狀態(tài)機的描述library library ieee;ieee;us

27、euse ieee.std_logic_1164.all;ieee.std_logic_1164.all;entityentity moore moore isis portport ( clk,x : ( clk,x : inin std_logic; std_logic; y: y: outout std_logic ); std_logic );endend moore; moore;architecturearchitecture behv behv ofof moore moore isis typetype state state isis (s0, s1, s2, s3); (s

28、0, s1, s2, s3); signal signal current_state, next_state: state; current_state, next_state: state;beginbegin第一進程，完成狀態(tài)第一進程，完成狀態(tài)轉換，必須飽含時鐘轉換，必須飽含時鐘敏感信號敏感信號reg:reg: processprocess (clk) (clk) beginbegin if (clkevent and clk=1 )(clkevent and clk=1 ) then then current_state = next_state; current_state y y

29、= 0; ifif x = 0 x = 0 thenthen next_state = s0; next_state = s0; elseelse next_state = s1; next_state y y = 1; ifif x = 0 x = 0 thenthen next_state = s2; next_state = s2; else else next_state = s1; next_state y y = 0; ifif x = 0 x = 0 thenthen next_state = s3; next_state = s3; elseelse next_state =

30、s2; next_state y y = 0; if if x = 0 x = 0 then then next_state = s1; next_state = s1; elseelse next_state = s0; next_state = s0; end ifend if; ; end end case; case; endend process; process; end end behy; behy;摩爾型摩爾型librarylibrary ieee; ieee;use use ieee.std_logic_1164.all;ieee.std_logic_1164.all;ent

31、ityentity mealy mealy isis portport ( clk , x : ( clk , x : inin std_logic; std_logic; y: y: outout std_logic ); std_logic );end end mealy;mealy;architecturearchitecture behv behv ofof mealy mealy isis typetype state state isis (s0, s1, s2, s3); (s0, s1, s2, s3); signalsignal current_state, next_sta

32、te: state; current_state, next_state: state;beginbegin reg:reg: process process (clk) (clk) beginbegin ifif (clkevent and clk=1 ) (clkevent and clk=1 ) thenthen current_state = next_state; current_state if x = 0 then next_state = s0; y = 0; else next_state = s1; y if x = 0 then next_state = s0; y =

33、0; else next_state = s2; y if x = 0 then next_state = s0; y = 0; else next_state = s3; y if x = 0 then next_state = s0; y = 0; else next_state = s3; y = 當前名稱當前名稱 （或，直接位置映射）（或，直接位置映射）一位全加器的原理圖basoabco library ieee ;-或門邏輯描述或門邏輯描述 use ieee.std_logic_1164.all; entity or2a is port (a, b :in std_logic; c

34、: out std_logic ); end or2a ； architecture art1 of or2a is begin c = a or b ; end art1;library ieee; -半加器描述半加器描述use ieee.std_logic_1164.all; entity h_adder is port (a, b : in std_logic; co, so : out std_logic); end adder; architecture art2 of adder is begin so = a xor b ; co e(a=e，b=cinb=cin，co=fco=

35、f，so=sum);so=sum); u3 : or2a u3 : or2a portport map map (d(d，f f，cout);cout);元件例化元件例化 end end art3;art3;librarylibrary ieee; ieee;use use ieee.std_logic_1164.all;ieee.std_logic_1164.all;entityentity count4 count4 isis portport ( clk , x : ( clk , x : inin std_logic; std_logic; qout : qout : out std_

36、logic _vector (1 downto 0); y: y: outout std_logic ); std_logic );end end count4;count4;architecturearchitecture behv behv ofof count4 count4 isis typetype state state isis (s0, s1, s2, s3); (s0, s1, s2, s3); signalsignal c_state, n_state : state; c_state, n_state : state;beginbegin reg:reg: process process (clk) (clk) beginbegin ifif (clkevent and clk=1 ) (clkevent and clk=1 ) thenthen c_state = n_state; c_state qout = “00” ; if x = 0 then n_s