verilog__串并轉(zhuǎn)換

1、 V erilog作業(yè)姓名:zzz班級(jí):zzzz學(xué)號(hào):zzzz報(bào)告日期:2010年10月30日作業(yè)題目要求:實(shí)現(xiàn)8位的并行數(shù)據(jù)轉(zhuǎn)換為串行的數(shù)據(jù)。題目分析:并行轉(zhuǎn)串行,只要把每個(gè)輸入按從高到低的順序輸出即可。即每個(gè)時(shí)鐘脈沖輸出一個(gè)數(shù)據(jù)。但是下面的代碼有一個(gè)的問(wèn)題,不能解決在8為數(shù)據(jù)串行輸出的過(guò)程當(dāng)中如果又有一個(gè)并行的輸入數(shù)據(jù)輸入,沒(méi)有做到緩沖處理。也許這個(gè)緩沖處理可以在調(diào)用此模塊時(shí)在外部實(shí)現(xiàn)吧。功能代碼:module para_to_serial_8bit(para_in,clock,reset,ser_out;input7:0para_in;input reset,clock;output s

2、er_out;reg ser_out;reg7:0data;always(posedge clock or negedge resetbeginif(resetbeginser_out<=1'b0;data<=para_in;endelse begindata<=data6:0,data7;ser_out<=data7;endendendmodule測(cè)試代碼:module test_para_to_ser;reg7:0para_in;reg clock,reset;wire out;para_to_serial_8bit f1(.para_in(para_in,

3、.clock(clock,.reset(reset,.ser_out(out;initial$monitor($time,"in_8bit=%b,reset=%b,ser_out=%b,data=%b",para_in,reset,out,f1.data; initial beginclock=1'b0;reset=1'b0;#3reset=1'b1;#300$stop;endinitialpara_in=8'b1010_0100;always#5clock=clock; endmodule測(cè)試結(jié)果: 測(cè)試波形如下: 作業(yè)二題目要求:實(shí)現(xiàn)8位

4、的串行數(shù)據(jù)轉(zhuǎn)換為并行的數(shù)據(jù)。題目分析:8位串行數(shù)據(jù)轉(zhuǎn)換為并行數(shù)據(jù),需要一個(gè)模為8的計(jì)數(shù)器,當(dāng)計(jì)到8個(gè)時(shí)鐘脈沖時(shí),把之前的8個(gè)數(shù)據(jù)全部輸出,然后從新接收。功能模塊代碼:模8計(jì)數(shù)器:module counter_mod_8(clock,reset,Q;input clock;/posedge effectiveinput reset;/negedge effectiveoutput2:0Q;reg2:0Q;always(posedge clock or negedge resetbeginif(resetQ<=3'd0;elseQ<=Q+1;endendmodul e串轉(zhuǎn)并模塊

5、:module ser_to_par_8bit(ser_in,clk,rst,out;input ser_in,clk,rst;output7:0out;wire7:0out;reg7:0par_out;wire2:0count;counter_mod_8f1(.clock(clk,.reset(rst,.Q(count;always(posedge clk or negedge rstbeginif(rstpar_out<=8'b0000_0000;else beginpar_out<=par_out6:0,ser_in;endendassign out=(count=7

6、?par_out:8'b0000_0000;endmodule測(cè)試模塊代碼:module test_ser_par;reg7:0data;wire data_in;reg clock,reset;wire7:0out;initial beginclock=1'b0;reset=1'b0;#3reset=1'b1;data=8'b1001_1101;#300$stop;endalways#5clock=clock;always(posedge clockdata=data6:0,data7;assign data_in=data7;ser_to_par_8

7、bit a(.ser_in(data_in,.clk(clock,.rst(reset,.out(out;initial$monitor($time,"reset=%b,data=%b,data_in=%b,out=%b",reset,data,data_in,out; endmodule測(cè)試結(jié)果： 測(cè)試波形： 作業(yè)三 題目：可變模計(jì)數(shù)器，當(dāng)控制信號(hào)為 1 時(shí)，模值為 16，當(dāng)控制信號(hào)為 0 是模值 為 32。 功能模塊代碼： / contr = 1 mod =16; contr =0 mod =32 module count_mod_chg(clk,reset,contr

8、,Q; input clk,reset,contr; output 4:0 Q; reg wire 4:0 Q; 4:0 last; assign last =(contr ? 5'b01111:5'b11111; always(posedge clk or negedge reset begin if(reset | Q = last Q <= 5'b00000; else Q = Q + 1; end endmodule 測(cè)試模塊代碼： module test_count_mod_chg; reg clock,reset; reg control; wire 4:0 out; count_mod_chg counter1(.clk(clock,.reset(reset,.contr(control,.Q(out; initial $monitor($time,"reset= %b,control= %b,out= %b",reset,control,out; initial begin clock = 1'b0; forever #5 clock = c